rtl8821ce/include/gspi_ops.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017 Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  *****************************************************************************/
  15 #ifndef __GSPI_OPS_H__
  16 #define __GSPI_OPS_H__
  17
  18 /* follwing defination is based on
  19  * GSPI spec of RTL8723, we temp
  20  * suppose that it will be the same
  21  * for diff chips of GSPI, if not
  22  * we should move it to HAL folder */
  23 #define SPI_LOCAL_DOMAIN                                0x0
  24 #define WLAN_IOREG_DOMAIN                       0x8
  25 #define FW_FIFO_DOMAIN                          0x4
  26 #define TX_HIQ_DOMAIN                                   0xc
  27 #define TX_MIQ_DOMAIN                                   0xd
  28 #define TX_LOQ_DOMAIN                                   0xe
  29 #define RX_RXFIFO_DOMAIN                                0x1f
  30
  31 /* IO Bus domain address mapping */
  32 #define DEFUALT_OFFSET                                  0x0
  33 #define SPI_LOCAL_OFFSET                                0x10250000
  34 #define WLAN_IOREG_OFFSET                       0x10260000
  35 #define FW_FIFO_OFFSET                          0x10270000
  36 #define TX_HIQ_OFFSET                                   0x10310000
  37 #define TX_MIQ_OFFSET                                   0x1032000
  38 #define TX_LOQ_OFFSET                                   0x10330000
  39 #define RX_RXOFF_OFFSET                         0x10340000
  40
  41 /* SPI Local registers */
  42 #define SPI_REG_TX_CTRL                                 0x0000 /* SPI Tx Control */
  43 #define SPI_REG_STATUS_RECOVERY         0x0004
  44 #define SPI_REG_INT_TIMEOUT                     0x0006
  45 #define SPI_REG_HIMR                                    0x0014 /* SPI Host Interrupt Mask */
  46 #define SPI_REG_HISR                                    0x0018 /* SPI Host Interrupt Service Routine */
  47 #define SPI_REG_RX0_REQ_LEN                     0x001C /* RXDMA Request Length */
  48 #define SPI_REG_FREE_TXPG                               0x0020 /* Free Tx Buffer Page */
  49 #define SPI_REG_HCPWM1                                  0x0024 /* HCI Current Power Mode 1 */
  50 #define SPI_REG_HCPWM2                                  0x0026 /* HCI Current Power Mode 2 */
  51 #define SPI_REG_HTSFR_INFO                              0x0030 /* HTSF Informaion */
  52 #define SPI_REG_HRPWM1                                  0x0080 /* HCI Request Power Mode 1 */
  53 #define SPI_REG_HRPWM2                                  0x0082 /* HCI Request Power Mode 2 */
  54 #define SPI_REG_HPS_CLKR                                0x0084 /* HCI Power Save Clock */
  55 #define SPI_REG_HSUS_CTRL                               0x0086 /* SPI HCI Suspend Control */
  56 #define SPI_REG_HIMR_ON                         0x0090 /* SPI Host Extension Interrupt Mask Always */
  57 #define SPI_REG_HISR_ON                         0x0091 /* SPI Host Extension Interrupt Status Always */
  58 #define SPI_REG_CFG                                             0x00F0 /* SPI Configuration Register */
  59
  60 #define SPI_TX_CTRL                             (SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET)
  61 #define SPI_STATUS_RECOVERY                     (SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET)
  62 #define SPI_INT_TIMEOUT                                 (SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET)
  63 #define SPI_HIMR                                (SPI_REG_HIMR | SPI_LOCAL_OFFSET)
  64 #define SPI_HISR                                (SPI_REG_HISR | SPI_LOCAL_OFFSET)
  65 #define SPI_RX0_REQ_LEN_1_BYTE          (SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET)
  66 #define SPI_FREE_TXPG                   (SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET)
  67
  68 #define SPI_HIMR_DISABLED                               0
  69
  70 /* SPI HIMR MASK diff with SDIO */
  71 #define SPI_HISR_RX_REQUEST                     BIT(0)
  72 #define SPI_HISR_AVAL                                   BIT(1)
  73 #define SPI_HISR_TXERR                                  BIT(2)
  74 #define SPI_HISR_RXERR                                  BIT(3)
  75 #define SPI_HISR_TXFOVW                         BIT(4)
  76 #define SPI_HISR_RXFOVW                         BIT(5)
  77 #define SPI_HISR_TXBCNOK                                BIT(6)
  78 #define SPI_HISR_TXBCNERR                               BIT(7)
  79 #define SPI_HISR_BCNERLY_INT                    BIT(16)
  80 #define SPI_HISR_ATIMEND                                BIT(17)
  81 #define SPI_HISR_ATIMEND_E                              BIT(18)
  82 #define SPI_HISR_CTWEND                         BIT(19)
  83 #define SPI_HISR_C2HCMD                         BIT(20)
  84 #define SPI_HISR_CPWM1                                  BIT(21)
  85 #define SPI_HISR_CPWM2                                  BIT(22)
  86 #define SPI_HISR_HSISR_IND                              BIT(23)
  87 #define SPI_HISR_GTINT3_IND                             BIT(24)
  88 #define SPI_HISR_GTINT4_IND                             BIT(25)
  89 #define SPI_HISR_PSTIMEOUT                              BIT(26)
  90 #define SPI_HISR_OCPINT                                 BIT(27)
  91 #define SPI_HISR_TSF_BIT32_TOGGLE               BIT(29)
  92
  93 #define MASK_SPI_HISR_CLEAR             (SPI_HISR_TXERR |\
  94                 SPI_HISR_RXERR |\
  95                 SPI_HISR_TXFOVW |\
  96                 SPI_HISR_RXFOVW |\
  97                 SPI_HISR_TXBCNOK |\
  98                 SPI_HISR_TXBCNERR |\
  99                 SPI_HISR_C2HCMD |\
 100                 SPI_HISR_CPWM1 |\
 101                 SPI_HISR_CPWM2 |\
 102                 SPI_HISR_HSISR_IND |\
 103                 SPI_HISR_GTINT3_IND |\
 104                 SPI_HISR_GTINT4_IND |\
 105                 SPI_HISR_PSTIMEOUT |\
 106                 SPI_HISR_OCPINT)
 107
 108 #define REG_LEN_FORMAT(pcmd, x)                         SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */
 109 #define REG_ADDR_FORMAT(pcmd, x)                        SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */
 110 #define REG_DOMAIN_ID_FORMAT(pcmd, x)           SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
 111 #define REG_FUN_FORMAT(pcmd, x)                         SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
 112 #define REG_RW_FORMAT(pcmd, x)                          SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
 113
 114 #define FIFO_LEN_FORMAT(pcmd, x)                        SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24)
 115  * #define FIFO_ADDR_FORMAT(pcmd,x)                     SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */
 116 #define FIFO_DOMAIN_ID_FORMAT(pcmd, x)  SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */
 117 #define FIFO_FUN_FORMAT(pcmd, x)                        SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */
 118 #define FIFO_RW_FORMAT(pcmd, x)                         SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */
 119
 120
 121 /* get status dword0 */
 122 #define GET_STATUS_PUB_PAGE_NUM(status)         LE_BITS_TO_4BYTE(status, 24, 8)
 123 #define GET_STATUS_HI_PAGE_NUM(status)          LE_BITS_TO_4BYTE(status, 18, 6)
 124 #define GET_STATUS_MID_PAGE_NUM(status)         LE_BITS_TO_4BYTE(status, 12, 6)
 125 #define GET_STATUS_LOW_PAGE_NUM(status)         LE_BITS_TO_4BYTE(status, 6, 6)
 126 #define GET_STATUS_HISR_HI6BIT(status)                  LE_BITS_TO_4BYTE(status, 0, 6)
 127
 128 /* get status dword1 */
 129 #define GET_STATUS_HISR_MID8BIT(status)         LE_BITS_TO_4BYTE(status + 4, 24, 8)
 130 #define GET_STATUS_HISR_LOW8BIT(status)         LE_BITS_TO_4BYTE(status + 4, 16, 8)
 131 #define GET_STATUS_ERROR(status)                                LE_BITS_TO_4BYTE(status + 4, 17, 1)
 132 #define GET_STATUS_INT(status)                          LE_BITS_TO_4BYTE(status + 4, 16, 1)
 133 #define GET_STATUS_RX_LENGTH(status)                    LE_BITS_TO_4BYTE(status + 4, 0, 16)
 134
 135
 136 #define RXDESC_SIZE     24
 137
 138
 139 struct spi_more_data {
 140         unsigned long more_data;
 141         unsigned long len;
 142 };
 143
 144 #ifdef CONFIG_RTL8188E
 145         void rtl8188es_set_hal_ops(PADAPTER padapter);
 146         #define set_hal_ops rtl8188es_set_hal_ops
 147 #endif
 148 extern void spi_set_chip_endian(PADAPTER padapter);
 149 extern unsigned int spi_write8_endian(ADAPTER *Adapter, unsigned int addr, unsigned int buf, u32 big);
 150 extern void spi_set_intf_ops(_adapter *padapter, struct _io_ops *pops);
 151 extern void spi_set_chip_endian(PADAPTER padapter);
 152 extern void InitInterrupt8723ASdio(PADAPTER padapter);
 153 extern void InitSysInterrupt8723ASdio(PADAPTER padapter);
 154 extern void EnableInterrupt8723ASdio(PADAPTER padapter);
 155 extern void DisableInterrupt8723ASdio(PADAPTER padapter);
 156 extern void spi_int_hdl(PADAPTER padapter);
 157 extern u8 HalQueryTxBufferStatus8723ASdio(PADAPTER padapter);
 158 #ifdef CONFIG_RTL8723B
 159         extern void InitInterrupt8723BSdio(PADAPTER padapter);
 160         extern void InitSysInterrupt8723BSdio(PADAPTER padapter);
 161         extern void EnableInterrupt8723BSdio(PADAPTER padapter);
 162         extern void DisableInterrupt8723BSdio(PADAPTER padapter);
 163         extern u8 HalQueryTxBufferStatus8723BSdio(PADAPTER padapter);
 164 #endif
 165
 166 #ifdef CONFIG_RTL8188E
 167         extern void InitInterrupt8188EGspi(PADAPTER padapter);
 168         extern void EnableInterrupt8188EGspi(PADAPTER padapter);
 169         extern void DisableInterrupt8188EGspi(PADAPTER padapter);
 170         extern void UpdateInterruptMask8188EGspi(PADAPTER padapter, u32 AddMSR, u32 RemoveMSR);
 171         extern u8 HalQueryTxBufferStatus8189EGspi(PADAPTER padapter);
 172         extern u8 HalQueryTxOQTBufferStatus8189EGspi(PADAPTER padapter);
 173         extern void ClearInterrupt8188EGspi(PADAPTER padapter);
 174         extern u8 CheckIPSStatus(PADAPTER padapter);
 175 #endif /* CONFIG_RTL8188E */
 176 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
 177         extern u8 RecvOnePkt(PADAPTER padapter);
 178 #endif /* CONFIG_WOWLAN */
 179
 180 #endif /* __GSPI_OPS_H__ */