3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
95 #if defined(__linux__) || defined(__NetBSD__)
98 #define DRM_MAX_MINOR 15
100 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
101 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
102 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
103 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
105 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
106 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
107 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
108 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
109 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
111 #if defined(__linux__)
112 typedef unsigned int drm_handle_t;
114 #include <sys/types.h>
115 typedef unsigned long drm_handle_t; /**< To mapped regions */
117 typedef unsigned int drm_context_t; /**< GLXContext handle */
118 typedef unsigned int drm_drawable_t;
119 typedef unsigned int drm_magic_t; /**< Magic for authentication */
124 * \warning If you change this structure, make sure you change
125 * XF86DRIClipRectRec in the server as well
127 * \note KW: Actually it's illegal to change either for
128 * backwards-compatibility reasons.
130 struct drm_clip_rect {
138 * Drawable information.
140 struct drm_drawable_info {
141 unsigned int num_rects;
142 struct drm_clip_rect *rects;
148 struct drm_tex_region {
151 unsigned char in_use;
152 unsigned char padding;
159 * The lock structure is a simple cache-line aligned integer. To avoid
160 * processor bus contention on a multiprocessor system, there should not be any
161 * other data stored in the same cache line.
164 __volatile__ unsigned int lock; /**< lock variable */
165 char padding[60]; /**< Pad to cache line */
168 /* This is beyond ugly, and only works on GCC. However, it allows me to use
169 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
170 * fix is to use uint32_t instead of size_t, but that fix will break existing
171 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
172 * eventually happen, though. I chose 'unsigned long' to be the fallback type
173 * because that works on all the platforms I know about. Hopefully, the
174 * real fix will happen before that bites us.
178 # define DRM_SIZE_T __SIZE_TYPE__
180 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
181 # define DRM_SIZE_T unsigned long
185 * DRM_IOCTL_VERSION ioctl argument type.
187 * \sa drmGetVersion().
190 int version_major; /**< Major version */
191 int version_minor; /**< Minor version */
192 int version_patchlevel; /**< Patch level */
193 DRM_SIZE_T name_len; /**< Length of name buffer */
194 char __user *name; /**< Name of driver */
195 DRM_SIZE_T date_len; /**< Length of date buffer */
196 char __user *date; /**< User-space buffer to hold date */
197 DRM_SIZE_T desc_len; /**< Length of desc buffer */
198 char __user *desc; /**< User-space buffer to hold desc */
202 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
204 * \sa drmGetBusid() and drmSetBusId().
207 DRM_SIZE_T unique_len; /**< Length of unique */
208 char __user *unique; /**< Unique name for driver instantiation */
214 int count; /**< Length of user-space structures */
215 struct drm_version __user *version;
223 * DRM_IOCTL_CONTROL ioctl argument type.
225 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
238 * Type of memory to map.
241 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
242 _DRM_REGISTERS = 1, /**< no caching, no core dump */
243 _DRM_SHM = 2, /**< shared, cached */
244 _DRM_AGP = 3, /**< AGP/GART */
245 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
246 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
251 * Memory mapping flags.
254 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
255 _DRM_READ_ONLY = 0x02,
256 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
257 _DRM_KERNEL = 0x08, /**< kernel requires access */
258 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
259 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
260 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
263 struct drm_ctx_priv_map {
264 unsigned int ctx_id; /**< Context requesting private mapping */
265 void *handle; /**< Handle of map */
269 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
275 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
276 unsigned long size; /**< Requested physical size (bytes) */
277 enum drm_map_type type; /**< Type of memory to map */
278 enum drm_map_flags flags; /**< Flags */
279 void *handle; /**< User-space: "Handle" to pass to mmap() */
280 /**< Kernel-space: kernel-virtual address */
281 int mtrr; /**< MTRR slot used */
286 * DRM_IOCTL_GET_CLIENT ioctl argument type.
289 int idx; /**< Which client desired? */
290 int auth; /**< Is client authenticated? */
291 unsigned long pid; /**< Process ID */
292 unsigned long uid; /**< User ID */
293 unsigned long magic; /**< Magic */
294 unsigned long iocs; /**< Ioctl count */
304 _DRM_STAT_VALUE, /**< Generic value */
305 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
306 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
308 _DRM_STAT_IRQ, /**< IRQ */
309 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
310 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
311 _DRM_STAT_DMA, /**< DMA */
312 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
313 _DRM_STAT_MISSED /**< Missed DMA opportunity */
314 /* Add to the *END* of the list */
318 * DRM_IOCTL_GET_STATS ioctl argument type.
324 enum drm_stat_type type;
329 * Hardware locking flags.
331 enum drm_lock_flags {
332 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
333 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
334 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
335 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
336 /* These *HALT* flags aren't supported yet
337 -- they will be used to support the
338 full-screen DGA-like mode. */
339 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
340 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
344 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
346 * \sa drmGetLock() and drmUnlock().
350 enum drm_lock_flags flags;
357 * These values \e must match xf86drm.h.
362 /* Flags for DMA buffer dispatch */
363 _DRM_DMA_BLOCK = 0x01, /**<
364 * Block until buffer dispatched.
366 * \note The buffer may not yet have
367 * been processed by the hardware --
368 * getting a hardware lock with the
369 * hardware quiescent will ensure
370 * that the buffer has been
373 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
374 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
376 /* Flags for DMA buffer request */
377 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
378 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
379 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
383 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
387 struct drm_buf_desc {
388 int count; /**< Number of buffers of this size */
389 int size; /**< Size in bytes */
390 int low_mark; /**< Low water mark */
391 int high_mark; /**< High water mark */
393 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
394 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
395 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
396 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
397 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
399 unsigned long agp_start; /**<
400 * Start address of where the AGP buffers are
401 * in the AGP aperture
406 * DRM_IOCTL_INFO_BUFS ioctl argument type.
408 struct drm_buf_info {
409 int count; /**< Number of buffers described in list */
410 struct drm_buf_desc __user *list; /**< List of buffer descriptions */
414 * DRM_IOCTL_FREE_BUFS ioctl argument type.
416 struct drm_buf_free {
427 int idx; /**< Index into the master buffer list */
428 int total; /**< Buffer size */
429 int used; /**< Amount of buffer in use (for DMA) */
430 void __user *address; /**< Address of buffer */
434 * DRM_IOCTL_MAP_BUFS ioctl argument type.
437 int count; /**< Length of the buffer list */
438 #if defined(__cplusplus)
439 void __user *c_virtual;
441 void __user *virtual; /**< Mmap'd area in user-virtual */
443 struct drm_buf_pub __user *list; /**< Buffer information */
447 * DRM_IOCTL_DMA ioctl argument type.
449 * Indices here refer to the offset into the buffer list in drm_buf_get.
454 int context; /**< Context handle */
455 int send_count; /**< Number of buffers to send */
456 int __user *send_indices; /**< List of handles to buffers */
457 int __user *send_sizes; /**< Lengths of data to send */
458 enum drm_dma_flags flags; /**< Flags */
459 int request_count; /**< Number of buffers requested */
460 int request_size; /**< Desired size for buffers */
461 int __user *request_indices; /**< Buffer information */
462 int __user *request_sizes;
463 int granted_count; /**< Number of buffers granted */
467 _DRM_CONTEXT_PRESERVED = 0x01,
468 _DRM_CONTEXT_2DONLY = 0x02
472 * DRM_IOCTL_ADD_CTX ioctl argument type.
474 * \sa drmCreateContext() and drmDestroyContext().
477 drm_context_t handle;
478 enum drm_ctx_flags flags;
482 * DRM_IOCTL_RES_CTX ioctl argument type.
486 struct drm_ctx __user *contexts;
490 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
493 drm_drawable_t handle;
497 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
500 DRM_DRAWABLE_CLIPRECTS,
501 } drm_drawable_info_type_t;
503 struct drm_update_draw {
504 drm_drawable_t handle;
507 unsigned long long data;
511 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
518 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
520 * \sa drmGetInterruptFromBusID().
522 struct drm_irq_busid {
523 int irq; /**< IRQ number */
524 int busnum; /**< bus number */
525 int devnum; /**< device number */
526 int funcnum; /**< function number */
529 enum drm_vblank_seq_type {
530 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
531 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
532 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
533 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
534 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
535 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
538 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
539 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
540 _DRM_VBLANK_NEXTONMISS)
542 struct drm_wait_vblank_request {
543 enum drm_vblank_seq_type type;
544 unsigned int sequence;
545 unsigned long signal;
548 struct drm_wait_vblank_reply {
549 enum drm_vblank_seq_type type;
550 unsigned int sequence;
556 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
558 * \sa drmWaitVBlank().
560 union drm_wait_vblank {
561 struct drm_wait_vblank_request request;
562 struct drm_wait_vblank_reply reply;
566 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
568 * \sa drmAgpEnable().
570 struct drm_agp_mode {
571 unsigned long mode; /**< AGP mode */
575 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
577 * \sa drmAgpAlloc() and drmAgpFree().
579 struct drm_agp_buffer {
580 unsigned long size; /**< In bytes -- will round to page boundary */
581 unsigned long handle; /**< Used for binding / unbinding */
582 unsigned long type; /**< Type of memory to allocate */
583 unsigned long physical; /**< Physical used by i810 */
587 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
589 * \sa drmAgpBind() and drmAgpUnbind().
591 struct drm_agp_binding {
592 unsigned long handle; /**< From drm_agp_buffer */
593 unsigned long offset; /**< In bytes -- will round to page boundary */
597 * DRM_IOCTL_AGP_INFO ioctl argument type.
599 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
600 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
601 * drmAgpVendorId() and drmAgpDeviceId().
603 struct drm_agp_info {
604 int agp_version_major;
605 int agp_version_minor;
607 unsigned long aperture_base; /**< physical address */
608 unsigned long aperture_size; /**< bytes */
609 unsigned long memory_allowed; /**< bytes */
610 unsigned long memory_used;
612 /** \name PCI information */
614 unsigned short id_vendor;
615 unsigned short id_device;
620 * DRM_IOCTL_SG_ALLOC ioctl argument type.
622 struct drm_scatter_gather {
623 unsigned long size; /**< In bytes -- will round to page boundary */
624 unsigned long handle; /**< Used for mapping / unmapping */
628 * DRM_IOCTL_SET_VERSION ioctl argument type.
630 struct drm_set_version {
638 #define DRM_FENCE_FLAG_EMIT 0x00000001
639 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
640 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
641 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
642 #define DRM_FENCE_FLAG_NO_USER 0x00000010
644 /* Reserved for driver use */
645 #define DRM_FENCE_MASK_DRIVER 0xFF000000
647 #define DRM_FENCE_TYPE_EXE 0x00000001
649 struct drm_fence_arg {
651 unsigned int fence_class;
654 unsigned int signaled;
656 unsigned int sequence;
658 uint64_t expand_pad[2]; /*Future expansion */
661 /* Buffer permissions, referring to how the GPU uses the buffers.
662 * these translate to fence types used for the buffers.
663 * Typically a texture buffer is read, A destination buffer is write and
664 * a command (batch-) buffer is exe. Can be or-ed together.
667 #define DRM_BO_FLAG_READ (1ULL << 0)
668 #define DRM_BO_FLAG_WRITE (1ULL << 1)
669 #define DRM_BO_FLAG_EXE (1ULL << 2)
672 * Status flags. Can be read to determine the actual state of a buffer.
673 * Can also be set in the buffer mask before validation.
677 * Mask: Never evict this buffer. Not even with force. This type of buffer is only
678 * available to root and must be manually removed before buffer manager shutdown
682 #define DRM_BO_FLAG_NO_EVICT (1ULL << 4)
685 * Mask: Require that the buffer is placed in mappable memory when validated.
686 * If not set the buffer may or may not be in mappable memory when validated.
687 * Flags: If set, the buffer is in mappable memory.
689 #define DRM_BO_FLAG_MAPPABLE (1ULL << 5)
691 /* Mask: The buffer should be shareable with other processes.
692 * Flags: The buffer is shareable with other processes.
694 #define DRM_BO_FLAG_SHAREABLE (1ULL << 6)
696 /* Mask: If set, place the buffer in cache-coherent memory if available.
697 * If clear, never place the buffer in cache coherent memory if validated.
698 * Flags: The buffer is currently in cache-coherent memory.
700 #define DRM_BO_FLAG_CACHED (1ULL << 7)
702 /* Mask: Make sure that every time this buffer is validated,
703 * it ends up on the same location provided that the memory mask is the same.
704 * The buffer will also not be evicted when claiming space for
705 * other buffers. Basically a pinned buffer but it may be thrown out as
706 * part of buffer manager shutdown or locking.
707 * Flags: Acknowledge.
709 #define DRM_BO_FLAG_NO_MOVE (1ULL << 8)
711 /* Mask: Make sure the buffer is in cached memory when mapped for reading.
712 * Flags: Acknowledge.
714 #define DRM_BO_FLAG_READ_CACHED (1ULL << 19)
716 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
717 * Flags: Acknowledge.
719 #define DRM_BO_FLAG_FORCE_CACHING (1ULL << 13)
722 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
723 * Flags: Acknowledge.
725 #define DRM_BO_FLAG_FORCE_MAPPABLE (1ULL << 14)
726 #define DRM_BO_FLAG_TILE (1ULL << 15)
729 * Memory type flags that can be or'ed together in the mask, but only
730 * one appears in flags.
734 #define DRM_BO_FLAG_MEM_LOCAL (1ULL << 24)
735 /* Translation table memory */
736 #define DRM_BO_FLAG_MEM_TT (1ULL << 25)
738 #define DRM_BO_FLAG_MEM_VRAM (1ULL << 26)
739 /* Up to the driver to define. */
740 #define DRM_BO_FLAG_MEM_PRIV0 (1ULL << 27)
741 #define DRM_BO_FLAG_MEM_PRIV1 (1ULL << 28)
742 #define DRM_BO_FLAG_MEM_PRIV2 (1ULL << 29)
743 #define DRM_BO_FLAG_MEM_PRIV3 (1ULL << 30)
744 #define DRM_BO_FLAG_MEM_PRIV4 (1ULL << 31)
745 /* We can add more of these now with a 64-bit flag type */
747 /* Memory flag mask */
748 #define DRM_BO_MASK_MEM 0x00000000FF000000ULL
749 #define DRM_BO_MASK_MEMTYPE 0x00000000FF0000A0ULL
751 /* Driver-private flags */
752 #define DRM_BO_MASK_DRIVER 0xFFFF000000000000ULL
754 /* Don't block on validate and map */
755 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
756 /* Don't place this buffer on the unfenced list.*/
757 #define DRM_BO_HINT_DONT_FENCE 0x00000004
758 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
760 #define DRM_BO_INIT_MAGIC 0xfe769812
761 #define DRM_BO_INIT_MAJOR 0
762 #define DRM_BO_INIT_MINOR 1
765 struct drm_bo_info_req {
770 unsigned int fence_class;
771 unsigned int desired_tile_stride;
772 unsigned int tile_info;
776 struct drm_bo_create_req {
779 uint64_t buffer_start;
781 unsigned int page_alignment;
789 #define DRM_BO_REP_BUSY 0x00000001
791 struct drm_bo_info_rep {
797 uint64_t buffer_start;
799 unsigned int fence_flags;
800 unsigned int rep_flags;
801 unsigned int page_alignment;
802 unsigned int desired_tile_stride;
803 unsigned int hw_tile_stride;
804 unsigned int tile_info;
806 uint64_t expand_pad[4]; /*Future expansion */
809 struct drm_bo_arg_rep {
810 struct drm_bo_info_rep bo_info;
815 struct drm_bo_create_arg {
817 struct drm_bo_create_req req;
818 struct drm_bo_info_rep rep;
822 struct drm_bo_handle_arg {
826 struct drm_bo_reference_info_arg {
828 struct drm_bo_handle_arg req;
829 struct drm_bo_info_rep rep;
833 struct drm_bo_map_wait_idle_arg {
835 struct drm_bo_info_req req;
836 struct drm_bo_info_rep rep;
840 struct drm_bo_op_req {
846 unsigned int arg_handle;
847 struct drm_bo_info_req bo_req;
851 struct drm_bo_op_arg {
854 struct drm_bo_op_req req;
855 struct drm_bo_arg_rep rep;
862 #define DRM_BO_MEM_LOCAL 0
863 #define DRM_BO_MEM_TT 1
864 #define DRM_BO_MEM_VRAM 2
865 #define DRM_BO_MEM_PRIV0 3
866 #define DRM_BO_MEM_PRIV1 4
867 #define DRM_BO_MEM_PRIV2 5
868 #define DRM_BO_MEM_PRIV3 6
869 #define DRM_BO_MEM_PRIV4 7
871 #define DRM_BO_MEM_TYPES 8 /* For now. */
873 struct drm_mm_type_arg {
874 unsigned int mem_type;
878 struct drm_mm_init_arg {
882 unsigned int mem_type;
888 * \name Ioctls Definitions
892 #define DRM_IOCTL_BASE 'd'
893 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
894 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
895 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
896 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
898 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
899 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
900 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
901 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
902 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
903 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
904 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
905 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
907 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
908 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
909 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
910 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
911 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
912 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
913 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
914 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
915 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
916 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
917 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
919 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
921 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
922 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
924 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
925 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
926 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
927 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
928 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
929 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
930 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
931 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
932 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
933 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
934 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
935 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
936 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
938 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
939 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
940 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
941 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
942 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
943 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
944 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
945 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
947 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, struct drm_scatter_gather)
948 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
950 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
952 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
954 #define DRM_IOCTL_MM_INIT DRM_IOWR(0xc0, struct drm_mm_init_arg)
955 #define DRM_IOCTL_MM_TAKEDOWN DRM_IOWR(0xc1, struct drm_mm_type_arg)
956 #define DRM_IOCTL_MM_LOCK DRM_IOWR(0xc2, struct drm_mm_type_arg)
957 #define DRM_IOCTL_MM_UNLOCK DRM_IOWR(0xc3, struct drm_mm_type_arg)
959 #define DRM_IOCTL_FENCE_CREATE DRM_IOWR(0xc4, struct drm_fence_arg)
960 #define DRM_IOCTL_FENCE_REFERENCE DRM_IOWR(0xc6, struct drm_fence_arg)
961 #define DRM_IOCTL_FENCE_UNREFERENCE DRM_IOWR(0xc7, struct drm_fence_arg)
962 #define DRM_IOCTL_FENCE_SIGNALED DRM_IOWR(0xc8, struct drm_fence_arg)
963 #define DRM_IOCTL_FENCE_FLUSH DRM_IOWR(0xc9, struct drm_fence_arg)
964 #define DRM_IOCTL_FENCE_WAIT DRM_IOWR(0xca, struct drm_fence_arg)
965 #define DRM_IOCTL_FENCE_EMIT DRM_IOWR(0xcb, struct drm_fence_arg)
966 #define DRM_IOCTL_FENCE_BUFFERS DRM_IOWR(0xcc, struct drm_fence_arg)
968 #define DRM_IOCTL_BO_CREATE DRM_IOWR(0xcd, struct drm_bo_create_arg)
969 #define DRM_IOCTL_BO_MAP DRM_IOWR(0xcf, struct drm_bo_map_wait_idle_arg)
970 #define DRM_IOCTL_BO_UNMAP DRM_IOWR(0xd0, struct drm_bo_handle_arg)
971 #define DRM_IOCTL_BO_REFERENCE DRM_IOWR(0xd1, struct drm_bo_reference_info_arg)
972 #define DRM_IOCTL_BO_UNREFERENCE DRM_IOWR(0xd2, struct drm_bo_handle_arg)
973 #define DRM_IOCTL_BO_SETSTATUS DRM_IOWR(0xd3, struct drm_bo_map_wait_idle_arg)
974 #define DRM_IOCTL_BO_INFO DRM_IOWR(0xd4, struct drm_bo_reference_info_arg)
975 #define DRM_IOCTL_BO_WAIT_IDLE DRM_IOWR(0xd5, struct drm_bo_map_wait_idle_arg)
981 * Device specific ioctls should only be in their respective headers
982 * The device specific ioctl range is from 0x40 to 0x99.
983 * Generic IOCTLS restart at 0xA0.
985 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
986 * drmCommandReadWrite().
988 #define DRM_COMMAND_BASE 0x40
989 #define DRM_COMMAND_END 0xA0
992 #if !defined(__KERNEL__) || defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__)
993 typedef struct drm_clip_rect drm_clip_rect_t;
994 typedef struct drm_drawable_info drm_drawable_info_t;
995 typedef struct drm_tex_region drm_tex_region_t;
996 typedef struct drm_hw_lock drm_hw_lock_t;
997 typedef struct drm_version drm_version_t;
998 typedef struct drm_unique drm_unique_t;
999 typedef struct drm_list drm_list_t;
1000 typedef struct drm_block drm_block_t;
1001 typedef struct drm_control drm_control_t;
1002 typedef enum drm_map_type drm_map_type_t;
1003 typedef enum drm_map_flags drm_map_flags_t;
1004 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1005 typedef struct drm_map drm_map_t;
1006 typedef struct drm_client drm_client_t;
1007 typedef enum drm_stat_type drm_stat_type_t;
1008 typedef struct drm_stats drm_stats_t;
1009 typedef enum drm_lock_flags drm_lock_flags_t;
1010 typedef struct drm_lock drm_lock_t;
1011 typedef enum drm_dma_flags drm_dma_flags_t;
1012 typedef struct drm_buf_desc drm_buf_desc_t;
1013 typedef struct drm_buf_info drm_buf_info_t;
1014 typedef struct drm_buf_free drm_buf_free_t;
1015 typedef struct drm_buf_pub drm_buf_pub_t;
1016 typedef struct drm_buf_map drm_buf_map_t;
1017 typedef struct drm_dma drm_dma_t;
1018 typedef union drm_wait_vblank drm_wait_vblank_t;
1019 typedef struct drm_agp_mode drm_agp_mode_t;
1020 typedef enum drm_ctx_flags drm_ctx_flags_t;
1021 typedef struct drm_ctx drm_ctx_t;
1022 typedef struct drm_ctx_res drm_ctx_res_t;
1023 typedef struct drm_draw drm_draw_t;
1024 typedef struct drm_update_draw drm_update_draw_t;
1025 typedef struct drm_auth drm_auth_t;
1026 typedef struct drm_irq_busid drm_irq_busid_t;
1027 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1028 typedef struct drm_agp_buffer drm_agp_buffer_t;
1029 typedef struct drm_agp_binding drm_agp_binding_t;
1030 typedef struct drm_agp_info drm_agp_info_t;
1031 typedef struct drm_scatter_gather drm_scatter_gather_t;
1032 typedef struct drm_set_version drm_set_version_t;
1034 typedef struct drm_fence_arg drm_fence_arg_t;
1035 typedef struct drm_mm_type_arg drm_mm_type_arg_t;
1036 typedef struct drm_mm_init_arg drm_mm_init_arg_t;
1037 typedef enum drm_bo_type drm_bo_type_t;