3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #include <sys/ioccom.h>
84 #define DRM_IOCTL_NR(n) ((n) & 0xff)
85 #define DRM_IOC_VOID IOC_VOID
86 #define DRM_IOC_READ IOC_OUT
87 #define DRM_IOC_WRITE IOC_IN
88 #define DRM_IOC_READWRITE IOC_INOUT
89 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
95 #if defined(__linux__) || defined(__NetBSD__)
98 #define DRM_MAX_MINOR 15
100 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
101 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
102 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
103 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
105 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
106 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
107 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
108 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
109 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
111 #if defined(__linux__)
112 typedef unsigned int drm_handle_t;
114 #include <sys/types.h>
115 typedef unsigned long drm_handle_t; /**< To mapped regions */
117 typedef unsigned int drm_context_t; /**< GLXContext handle */
118 typedef unsigned int drm_drawable_t;
119 typedef unsigned int drm_magic_t; /**< Magic for authentication */
124 * \warning If you change this structure, make sure you change
125 * XF86DRIClipRectRec in the server as well
127 * \note KW: Actually it's illegal to change either for
128 * backwards-compatibility reasons.
130 struct drm_clip_rect {
140 struct drm_tex_region {
143 unsigned char in_use;
144 unsigned char padding;
151 * The lock structure is a simple cache-line aligned integer. To avoid
152 * processor bus contention on a multiprocessor system, there should not be any
153 * other data stored in the same cache line.
156 __volatile__ unsigned int lock; /**< lock variable */
157 char padding[60]; /**< Pad to cache line */
160 /* This is beyond ugly, and only works on GCC. However, it allows me to use
161 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
162 * fix is to use uint32_t instead of size_t, but that fix will break existing
163 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
164 * eventually happen, though. I chose 'unsigned long' to be the fallback type
165 * because that works on all the platforms I know about. Hopefully, the
166 * real fix will happen before that bites us.
170 # define DRM_SIZE_T __SIZE_TYPE__
172 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
173 # define DRM_SIZE_T unsigned long
177 * DRM_IOCTL_VERSION ioctl argument type.
179 * \sa drmGetVersion().
182 int version_major; /**< Major version */
183 int version_minor; /**< Minor version */
184 int version_patchlevel; /**< Patch level */
185 DRM_SIZE_T name_len; /**< Length of name buffer */
186 char __user *name; /**< Name of driver */
187 DRM_SIZE_T date_len; /**< Length of date buffer */
188 char __user *date; /**< User-space buffer to hold date */
189 DRM_SIZE_T desc_len; /**< Length of desc buffer */
190 char __user *desc; /**< User-space buffer to hold desc */
194 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
196 * \sa drmGetBusid() and drmSetBusId().
199 DRM_SIZE_T unique_len; /**< Length of unique */
200 char __user *unique; /**< Unique name for driver instantiation */
206 int count; /**< Length of user-space structures */
207 struct drm_version __user *version;
215 * DRM_IOCTL_CONTROL ioctl argument type.
217 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
230 * Type of memory to map.
233 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
234 _DRM_REGISTERS = 1, /**< no caching, no core dump */
235 _DRM_SHM = 2, /**< shared, cached */
236 _DRM_AGP = 3, /**< AGP/GART */
237 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
238 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
244 * Memory mapping flags.
247 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
248 _DRM_READ_ONLY = 0x02,
249 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
250 _DRM_KERNEL = 0x08, /**< kernel requires access */
251 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
252 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
253 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
254 _DRM_DRIVER = 0x80 /**< Managed by driver */
257 struct drm_ctx_priv_map {
258 unsigned int ctx_id; /**< Context requesting private mapping */
259 void *handle; /**< Handle of map */
263 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
269 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
270 unsigned long size; /**< Requested physical size (bytes) */
271 enum drm_map_type type; /**< Type of memory to map */
272 enum drm_map_flags flags; /**< Flags */
273 void *handle; /**< User-space: "Handle" to pass to mmap() */
274 /**< Kernel-space: kernel-virtual address */
275 int mtrr; /**< MTRR slot used */
280 * DRM_IOCTL_GET_CLIENT ioctl argument type.
283 int idx; /**< Which client desired? */
284 int auth; /**< Is client authenticated? */
285 unsigned long pid; /**< Process ID */
286 unsigned long uid; /**< User ID */
287 unsigned long magic; /**< Magic */
288 unsigned long iocs; /**< Ioctl count */
298 _DRM_STAT_VALUE, /**< Generic value */
299 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
300 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
302 _DRM_STAT_IRQ, /**< IRQ */
303 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
304 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
305 _DRM_STAT_DMA, /**< DMA */
306 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
307 _DRM_STAT_MISSED /**< Missed DMA opportunity */
308 /* Add to the *END* of the list */
312 * DRM_IOCTL_GET_STATS ioctl argument type.
318 enum drm_stat_type type;
323 * Hardware locking flags.
325 enum drm_lock_flags {
326 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
327 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
328 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
329 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
330 /* These *HALT* flags aren't supported yet
331 -- they will be used to support the
332 full-screen DGA-like mode. */
333 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
334 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
338 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
340 * \sa drmGetLock() and drmUnlock().
344 enum drm_lock_flags flags;
351 * These values \e must match xf86drm.h.
356 /* Flags for DMA buffer dispatch */
357 _DRM_DMA_BLOCK = 0x01, /**<
358 * Block until buffer dispatched.
360 * \note The buffer may not yet have
361 * been processed by the hardware --
362 * getting a hardware lock with the
363 * hardware quiescent will ensure
364 * that the buffer has been
367 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
368 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
370 /* Flags for DMA buffer request */
371 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
372 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
373 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
377 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
381 struct drm_buf_desc {
382 int count; /**< Number of buffers of this size */
383 int size; /**< Size in bytes */
384 int low_mark; /**< Low water mark */
385 int high_mark; /**< High water mark */
387 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
388 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
389 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
390 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
391 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
393 unsigned long agp_start; /**<
394 * Start address of where the AGP buffers are
395 * in the AGP aperture
400 * DRM_IOCTL_INFO_BUFS ioctl argument type.
402 struct drm_buf_info {
403 int count; /**< Number of buffers described in list */
404 struct drm_buf_desc __user *list; /**< List of buffer descriptions */
408 * DRM_IOCTL_FREE_BUFS ioctl argument type.
410 struct drm_buf_free {
421 int idx; /**< Index into the master buffer list */
422 int total; /**< Buffer size */
423 int used; /**< Amount of buffer in use (for DMA) */
424 void __user *address; /**< Address of buffer */
428 * DRM_IOCTL_MAP_BUFS ioctl argument type.
431 int count; /**< Length of the buffer list */
432 #if defined(__cplusplus)
433 void __user *c_virtual;
435 void __user *virtual; /**< Mmap'd area in user-virtual */
437 struct drm_buf_pub __user *list; /**< Buffer information */
441 * DRM_IOCTL_DMA ioctl argument type.
443 * Indices here refer to the offset into the buffer list in drm_buf_get.
448 int context; /**< Context handle */
449 int send_count; /**< Number of buffers to send */
450 int __user *send_indices; /**< List of handles to buffers */
451 int __user *send_sizes; /**< Lengths of data to send */
452 enum drm_dma_flags flags; /**< Flags */
453 int request_count; /**< Number of buffers requested */
454 int request_size; /**< Desired size for buffers */
455 int __user *request_indices; /**< Buffer information */
456 int __user *request_sizes;
457 int granted_count; /**< Number of buffers granted */
461 _DRM_CONTEXT_PRESERVED = 0x01,
462 _DRM_CONTEXT_2DONLY = 0x02
466 * DRM_IOCTL_ADD_CTX ioctl argument type.
468 * \sa drmCreateContext() and drmDestroyContext().
471 drm_context_t handle;
472 enum drm_ctx_flags flags;
476 * DRM_IOCTL_RES_CTX ioctl argument type.
480 struct drm_ctx __user *contexts;
484 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
487 drm_drawable_t handle;
491 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
494 DRM_DRAWABLE_CLIPRECTS,
495 } drm_drawable_info_type_t;
497 struct drm_update_draw {
498 drm_drawable_t handle;
501 unsigned long long data;
505 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
512 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
514 * \sa drmGetInterruptFromBusID().
516 struct drm_irq_busid {
517 int irq; /**< IRQ number */
518 int busnum; /**< bus number */
519 int devnum; /**< device number */
520 int funcnum; /**< function number */
523 enum drm_vblank_seq_type {
524 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
525 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
526 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
527 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
528 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
529 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
532 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
533 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
534 _DRM_VBLANK_NEXTONMISS)
536 struct drm_wait_vblank_request {
537 enum drm_vblank_seq_type type;
538 unsigned int sequence;
539 unsigned long signal;
542 struct drm_wait_vblank_reply {
543 enum drm_vblank_seq_type type;
544 unsigned int sequence;
550 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
552 * \sa drmWaitVBlank().
554 union drm_wait_vblank {
555 struct drm_wait_vblank_request request;
556 struct drm_wait_vblank_reply reply;
560 enum drm_modeset_ctl_cmd {
561 _DRM_PRE_MODESET = 1,
562 _DRM_POST_MODESET = 2,
567 * DRM_IOCTL_MODESET_CTL ioctl argument type
569 * \sa drmModesetCtl().
571 struct drm_modeset_ctl {
577 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
579 * \sa drmAgpEnable().
581 struct drm_agp_mode {
582 unsigned long mode; /**< AGP mode */
586 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
588 * \sa drmAgpAlloc() and drmAgpFree().
590 struct drm_agp_buffer {
591 unsigned long size; /**< In bytes -- will round to page boundary */
592 unsigned long handle; /**< Used for binding / unbinding */
593 unsigned long type; /**< Type of memory to allocate */
594 unsigned long physical; /**< Physical used by i810 */
598 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
600 * \sa drmAgpBind() and drmAgpUnbind().
602 struct drm_agp_binding {
603 unsigned long handle; /**< From drm_agp_buffer */
604 unsigned long offset; /**< In bytes -- will round to page boundary */
608 * DRM_IOCTL_AGP_INFO ioctl argument type.
610 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
611 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
612 * drmAgpVendorId() and drmAgpDeviceId().
614 struct drm_agp_info {
615 int agp_version_major;
616 int agp_version_minor;
618 unsigned long aperture_base; /**< physical address */
619 unsigned long aperture_size; /**< bytes */
620 unsigned long memory_allowed; /**< bytes */
621 unsigned long memory_used;
623 /** \name PCI information */
625 unsigned short id_vendor;
626 unsigned short id_device;
631 * DRM_IOCTL_SG_ALLOC ioctl argument type.
633 struct drm_scatter_gather {
634 unsigned long size; /**< In bytes -- will round to page boundary */
635 unsigned long handle; /**< Used for mapping / unmapping */
639 * DRM_IOCTL_SET_VERSION ioctl argument type.
641 struct drm_set_version {
648 struct drm_gem_close {
649 /** Handle of the object to be closed. */
654 struct drm_gem_flink {
655 /** Handle for the object being named */
658 /** Returned global name */
662 struct drm_gem_open {
663 /** Name of object being opened */
666 /** Returned handle for the object */
669 /** Returned size of the object */
673 #include "drm_mode.h"
676 * \name Ioctls Definitions
680 #define DRM_IOCTL_BASE 'd'
681 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
682 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
683 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
684 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
686 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
687 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
688 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
689 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
690 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
691 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
692 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
693 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
694 #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
696 #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
697 #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
698 #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
700 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
701 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
702 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
703 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
704 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
705 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
706 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
707 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
708 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
709 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
710 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
712 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
714 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
715 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
717 #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
718 #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
720 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
721 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
722 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
723 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
724 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
725 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
726 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
727 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
728 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
729 #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
730 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
731 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
732 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
734 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
735 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
736 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
737 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
738 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
739 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
740 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
741 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
743 #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
744 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
746 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
748 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
750 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
752 #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
753 #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
754 #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
755 #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
756 #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
758 #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
760 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
761 #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
762 #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
763 #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
764 #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
765 #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
767 #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
768 #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
769 #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, uint32_t)
770 #define DRM_IOCTL_MODE_REPLACEFB DRM_IOWR(0xB0, struct drm_mode_fb_cmd)
775 * Device specific ioctls should only be in their respective headers
776 * The device specific ioctl range is from 0x40 to 0x99.
777 * Generic IOCTLS restart at 0xA0.
779 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
780 * drmCommandReadWrite().
782 #define DRM_COMMAND_BASE 0x40
783 #define DRM_COMMAND_END 0xA0
787 typedef struct drm_clip_rect drm_clip_rect_t;
788 typedef struct drm_tex_region drm_tex_region_t;
789 typedef struct drm_hw_lock drm_hw_lock_t;
790 typedef struct drm_version drm_version_t;
791 typedef struct drm_unique drm_unique_t;
792 typedef struct drm_list drm_list_t;
793 typedef struct drm_block drm_block_t;
794 typedef struct drm_control drm_control_t;
795 typedef enum drm_map_type drm_map_type_t;
796 typedef enum drm_map_flags drm_map_flags_t;
797 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
798 typedef struct drm_map drm_map_t;
799 typedef struct drm_client drm_client_t;
800 typedef enum drm_stat_type drm_stat_type_t;
801 typedef struct drm_stats drm_stats_t;
802 typedef enum drm_lock_flags drm_lock_flags_t;
803 typedef struct drm_lock drm_lock_t;
804 typedef enum drm_dma_flags drm_dma_flags_t;
805 typedef struct drm_buf_desc drm_buf_desc_t;
806 typedef struct drm_buf_info drm_buf_info_t;
807 typedef struct drm_buf_free drm_buf_free_t;
808 typedef struct drm_buf_pub drm_buf_pub_t;
809 typedef struct drm_buf_map drm_buf_map_t;
810 typedef struct drm_dma drm_dma_t;
811 typedef union drm_wait_vblank drm_wait_vblank_t;
812 typedef struct drm_agp_mode drm_agp_mode_t;
813 typedef enum drm_ctx_flags drm_ctx_flags_t;
814 typedef struct drm_ctx drm_ctx_t;
815 typedef struct drm_ctx_res drm_ctx_res_t;
816 typedef struct drm_draw drm_draw_t;
817 typedef struct drm_update_draw drm_update_draw_t;
818 typedef struct drm_auth drm_auth_t;
819 typedef struct drm_irq_busid drm_irq_busid_t;
820 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
821 typedef struct drm_agp_buffer drm_agp_buffer_t;
822 typedef struct drm_agp_binding drm_agp_binding_t;
823 typedef struct drm_agp_info drm_agp_info_t;
824 typedef struct drm_scatter_gather drm_scatter_gather_t;
825 typedef struct drm_set_version drm_set_version_t;