3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
69 # define DEPRECATED __attribute__ ((deprecated))
74 #if defined(__linux__)
75 #include <asm/ioctl.h> /* For _IO* macros */
76 #define DRM_IOCTL_NR(n) _IOC_NR(n)
77 #define DRM_IOC_VOID _IOC_NONE
78 #define DRM_IOC_READ _IOC_READ
79 #define DRM_IOC_WRITE _IOC_WRITE
80 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
81 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
82 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
83 #if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
84 /* Prevent name collision when including sys/ioccom.h */
86 #include <sys/ioccom.h>
87 #define ioctl(a,b,c) xf86ioctl(a,b,c)
89 #include <sys/ioccom.h>
90 #endif /* __FreeBSD__ && xf86ioctl */
91 #define DRM_IOCTL_NR(n) ((n) & 0xff)
92 #define DRM_IOC_VOID IOC_VOID
93 #define DRM_IOC_READ IOC_OUT
94 #define DRM_IOC_WRITE IOC_IN
95 #define DRM_IOC_READWRITE IOC_INOUT
96 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
99 #define XFREE86_VERSION(major,minor,patch,snap) \
100 ((major << 16) | (minor << 8) | patch)
102 #ifndef CONFIG_XFREE86_VERSION
103 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
106 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
107 #define DRM_PROC_DEVICES "/proc/devices"
108 #define DRM_PROC_MISC "/proc/misc"
109 #define DRM_PROC_DRM "/proc/drm"
110 #define DRM_DEV_DRM "/dev/drm"
111 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
112 #define DRM_DEV_UID 0
113 #define DRM_DEV_GID 0
116 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
120 #if defined(__linux__) || defined(__NetBSD__)
121 #define DRM_MAJOR 226
123 #define DRM_MAX_MINOR 15
125 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
126 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
127 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
128 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
130 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
131 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
132 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
133 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
134 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
136 #if defined(__linux__)
137 #if defined(__KERNEL__)
138 typedef __u64 drm_u64_t;
140 typedef unsigned long long drm_u64_t;
143 typedef unsigned int drm_handle_t;
145 #include <sys/types.h>
146 typedef u_int64_t drm_u64_t;
147 typedef unsigned long drm_handle_t; /**< To mapped regions */
149 typedef unsigned int drm_context_t; /**< GLXContext handle */
150 typedef unsigned int drm_drawable_t;
151 typedef unsigned int drm_magic_t; /**< Magic for authentication */
156 * \warning If you change this structure, make sure you change
157 * XF86DRIClipRectRec in the server as well
159 * \note KW: Actually it's illegal to change either for
160 * backwards-compatibility reasons.
162 typedef struct drm_clip_rect {
170 * Drawable information.
172 typedef struct drm_drawable_info {
173 unsigned int num_rects;
174 drm_clip_rect_t *rects;
175 } drm_drawable_info_t;
180 typedef struct drm_tex_region {
183 unsigned char in_use;
184 unsigned char padding;
191 * The lock structure is a simple cache-line aligned integer. To avoid
192 * processor bus contention on a multiprocessor system, there should not be any
193 * other data stored in the same cache line.
195 typedef struct drm_hw_lock {
196 __volatile__ unsigned int lock; /**< lock variable */
197 char padding[60]; /**< Pad to cache line */
200 /* This is beyond ugly, and only works on GCC. However, it allows me to use
201 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
202 * fix is to use uint32_t instead of size_t, but that fix will break existing
203 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
204 * eventually happen, though. I chose 'unsigned long' to be the fallback type
205 * because that works on all the platforms I know about. Hopefully, the
206 * real fix will happen before that bites us.
210 # define DRM_SIZE_T __SIZE_TYPE__
212 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
213 # define DRM_SIZE_T unsigned long
217 * DRM_IOCTL_VERSION ioctl argument type.
219 * \sa drmGetVersion().
221 typedef struct drm_version {
222 int version_major; /**< Major version */
223 int version_minor; /**< Minor version */
224 int version_patchlevel; /**< Patch level */
225 DRM_SIZE_T name_len; /**< Length of name buffer */
226 char __user *name; /**< Name of driver */
227 DRM_SIZE_T date_len; /**< Length of date buffer */
228 char __user *date; /**< User-space buffer to hold date */
229 DRM_SIZE_T desc_len; /**< Length of desc buffer */
230 char __user *desc; /**< User-space buffer to hold desc */
234 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
236 * \sa drmGetBusid() and drmSetBusId().
238 typedef struct drm_unique {
239 DRM_SIZE_T unique_len; /**< Length of unique */
240 char __user *unique; /**< Unique name for driver instantiation */
245 typedef struct drm_list {
246 int count; /**< Length of user-space structures */
247 drm_version_t __user *version;
250 typedef struct drm_block {
255 * DRM_IOCTL_CONTROL ioctl argument type.
257 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
259 typedef struct drm_control {
270 * Type of memory to map.
272 typedef enum drm_map_type {
273 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
274 _DRM_REGISTERS = 1, /**< no caching, no core dump */
275 _DRM_SHM = 2, /**< shared, cached */
276 _DRM_AGP = 3, /**< AGP/GART */
277 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
278 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
283 * Memory mapping flags.
285 typedef enum drm_map_flags {
286 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
287 _DRM_READ_ONLY = 0x02,
288 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
289 _DRM_KERNEL = 0x08, /**< kernel requires access */
290 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
291 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
292 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
295 typedef struct drm_ctx_priv_map {
296 unsigned int ctx_id; /**< Context requesting private mapping */
297 void *handle; /**< Handle of map */
298 } drm_ctx_priv_map_t;
301 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
306 typedef struct drm_map {
307 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
308 unsigned long size; /**< Requested physical size (bytes) */
309 drm_map_type_t type; /**< Type of memory to map */
310 drm_map_flags_t flags; /**< Flags */
311 void *handle; /**< User-space: "Handle" to pass to mmap() */
312 /**< Kernel-space: kernel-virtual address */
313 int mtrr; /**< MTRR slot used */
318 * DRM_IOCTL_GET_CLIENT ioctl argument type.
320 typedef struct drm_client {
321 int idx; /**< Which client desired? */
322 int auth; /**< Is client authenticated? */
323 unsigned long pid; /**< Process ID */
324 unsigned long uid; /**< User ID */
325 unsigned long magic; /**< Magic */
326 unsigned long iocs; /**< Ioctl count */
336 _DRM_STAT_VALUE, /**< Generic value */
337 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
338 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
340 _DRM_STAT_IRQ, /**< IRQ */
341 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
342 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
343 _DRM_STAT_DMA, /**< DMA */
344 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
345 _DRM_STAT_MISSED /**< Missed DMA opportunity */
346 /* Add to the *END* of the list */
350 * DRM_IOCTL_GET_STATS ioctl argument type.
352 typedef struct drm_stats {
356 drm_stat_type_t type;
361 * Hardware locking flags.
363 typedef enum drm_lock_flags {
364 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
365 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
366 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
367 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
368 /* These *HALT* flags aren't supported yet
369 -- they will be used to support the
370 full-screen DGA-like mode. */
371 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
372 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
376 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
378 * \sa drmGetLock() and drmUnlock().
380 typedef struct drm_lock {
382 drm_lock_flags_t flags;
389 * These values \e must match xf86drm.h.
393 typedef enum drm_dma_flags {
394 /* Flags for DMA buffer dispatch */
395 _DRM_DMA_BLOCK = 0x01, /**<
396 * Block until buffer dispatched.
398 * \note The buffer may not yet have
399 * been processed by the hardware --
400 * getting a hardware lock with the
401 * hardware quiescent will ensure
402 * that the buffer has been
405 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
406 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
408 /* Flags for DMA buffer request */
409 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
410 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
411 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
415 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
419 typedef struct drm_buf_desc {
420 int count; /**< Number of buffers of this size */
421 int size; /**< Size in bytes */
422 int low_mark; /**< Low water mark */
423 int high_mark; /**< High water mark */
425 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
426 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
427 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
428 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
429 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
431 unsigned long agp_start; /**<
432 * Start address of where the AGP buffers are
433 * in the AGP aperture
438 * DRM_IOCTL_INFO_BUFS ioctl argument type.
440 typedef struct drm_buf_info {
441 int count; /**< Number of buffers described in list */
442 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
446 * DRM_IOCTL_FREE_BUFS ioctl argument type.
448 typedef struct drm_buf_free {
458 typedef struct drm_buf_pub {
459 int idx; /**< Index into the master buffer list */
460 int total; /**< Buffer size */
461 int used; /**< Amount of buffer in use (for DMA) */
462 void __user *address; /**< Address of buffer */
466 * DRM_IOCTL_MAP_BUFS ioctl argument type.
468 typedef struct drm_buf_map {
469 int count; /**< Length of the buffer list */
470 #if defined(__cplusplus)
471 void __user *c_virtual;
473 void __user *virtual; /**< Mmap'd area in user-virtual */
475 drm_buf_pub_t __user *list; /**< Buffer information */
479 * DRM_IOCTL_DMA ioctl argument type.
481 * Indices here refer to the offset into the buffer list in drm_buf_get.
485 typedef struct drm_dma {
486 int context; /**< Context handle */
487 int send_count; /**< Number of buffers to send */
488 int __user *send_indices; /**< List of handles to buffers */
489 int __user *send_sizes; /**< Lengths of data to send */
490 drm_dma_flags_t flags; /**< Flags */
491 int request_count; /**< Number of buffers requested */
492 int request_size; /**< Desired size for buffers */
493 int __user *request_indices; /**< Buffer information */
494 int __user *request_sizes;
495 int granted_count; /**< Number of buffers granted */
499 _DRM_CONTEXT_PRESERVED = 0x01,
500 _DRM_CONTEXT_2DONLY = 0x02
504 * DRM_IOCTL_ADD_CTX ioctl argument type.
506 * \sa drmCreateContext() and drmDestroyContext().
508 typedef struct drm_ctx {
509 drm_context_t handle;
510 drm_ctx_flags_t flags;
514 * DRM_IOCTL_RES_CTX ioctl argument type.
516 typedef struct drm_ctx_res {
518 drm_ctx_t __user *contexts;
522 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
524 typedef struct drm_draw {
525 drm_drawable_t handle;
529 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
532 DRM_DRAWABLE_CLIPRECTS,
533 } drm_drawable_info_type_t;
535 typedef struct drm_update_draw {
536 drm_drawable_t handle;
539 unsigned long long data;
543 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
545 typedef struct drm_auth {
550 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
552 * \sa drmGetInterruptFromBusID().
554 typedef struct drm_irq_busid {
555 int irq; /**< IRQ number */
556 int busnum; /**< bus number */
557 int devnum; /**< device number */
558 int funcnum; /**< function number */
562 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
563 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
564 _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */
565 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
566 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
567 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
568 } drm_vblank_seq_type_t;
570 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
571 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
572 _DRM_VBLANK_NEXTONMISS)
574 struct drm_wait_vblank_request {
575 drm_vblank_seq_type_t type;
576 unsigned int sequence;
577 unsigned long signal;
580 struct drm_wait_vblank_reply {
581 drm_vblank_seq_type_t type;
582 unsigned int sequence;
588 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
590 * \sa drmWaitVBlank().
592 typedef union drm_wait_vblank {
593 struct drm_wait_vblank_request request;
594 struct drm_wait_vblank_reply reply;
598 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
600 * \sa drmAgpEnable().
602 typedef struct drm_agp_mode {
603 unsigned long mode; /**< AGP mode */
607 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
609 * \sa drmAgpAlloc() and drmAgpFree().
611 typedef struct drm_agp_buffer {
612 unsigned long size; /**< In bytes -- will round to page boundary */
613 unsigned long handle; /**< Used for binding / unbinding */
614 unsigned long type; /**< Type of memory to allocate */
615 unsigned long physical; /**< Physical used by i810 */
619 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
621 * \sa drmAgpBind() and drmAgpUnbind().
623 typedef struct drm_agp_binding {
624 unsigned long handle; /**< From drm_agp_buffer */
625 unsigned long offset; /**< In bytes -- will round to page boundary */
629 * DRM_IOCTL_AGP_INFO ioctl argument type.
631 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
632 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
633 * drmAgpVendorId() and drmAgpDeviceId().
635 typedef struct drm_agp_info {
636 int agp_version_major;
637 int agp_version_minor;
639 unsigned long aperture_base; /**< physical address */
640 unsigned long aperture_size; /**< bytes */
641 unsigned long memory_allowed; /**< bytes */
642 unsigned long memory_used;
644 /** \name PCI information */
646 unsigned short id_vendor;
647 unsigned short id_device;
652 * DRM_IOCTL_SG_ALLOC ioctl argument type.
654 typedef struct drm_scatter_gather {
655 unsigned long size; /**< In bytes -- will round to page boundary */
656 unsigned long handle; /**< Used for mapping / unmapping */
657 } drm_scatter_gather_t;
660 * DRM_IOCTL_SET_VERSION ioctl argument type.
662 typedef struct drm_set_version {
670 #define DRM_FENCE_FLAG_EMIT 0x00000001
671 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
672 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
673 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
675 /* Reserved for driver use */
676 #define DRM_FENCE_MASK_DRIVER 0xFF000000
678 #define DRM_FENCE_TYPE_EXE 0x00000001
680 typedef struct drm_fence_arg {
686 unsigned expand_pad[4]; /*Future expansion */
691 drm_fence_unreference,
700 /* Buffer permissions, referring to how the GPU uses the buffers.
701 * these translate to fence types used for the buffers.
702 * Typically a texture buffer is read, A destination buffer is write and
703 * a command (batch-) buffer is exe. Can be or-ed together.
706 #define DRM_BO_FLAG_READ 0x00000001
707 #define DRM_BO_FLAG_WRITE 0x00000002
708 #define DRM_BO_FLAG_EXE 0x00000004
711 * Status flags. Can be read to determine the actual state of a buffer.
712 * Can also be set in the buffer mask before validation.
716 * Mask: Never evict this buffer. Not even with force. This type of buffer is only
717 * available to root and must be manually removed before buffer manager shutdown
721 #define DRM_BO_FLAG_NO_EVICT 0x00000010
724 * Mask: Require that the buffer is placed in mappable memory when validated.
725 * If not set the buffer may or may not be in mappable memory when validated.
726 * Flags: If set, the buffer is in mappable memory.
728 #define DRM_BO_FLAG_MAPPABLE 0x00000020
730 /* Mask: The buffer should be shareable with other processes.
731 * Flags: The buffer is shareable with other processes.
733 #define DRM_BO_FLAG_SHAREABLE 0x00000040
735 /* Mask: If set, place the buffer in cache-coherent memory if available.
736 * If clear, never place the buffer in cache coherent memory if validated.
737 * Flags: The buffer is currently in cache-coherent memory.
739 #define DRM_BO_FLAG_CACHED 0x00000080
741 /* Mask: Make sure that every time this buffer is validated,
742 * it ends up on the same location provided that the memory mask is the same.
743 * The buffer will also not be evicted when claiming space for
744 * other buffers. Basically a pinned buffer but it may be thrown out as
745 * part of buffer manager shutdown or locking.
746 * Flags: Acknowledge.
748 #define DRM_BO_FLAG_NO_MOVE 0x00000100
750 /* Mask: Make sure the buffer is in cached memory when mapped for reading.
751 * Flags: Acknowledge.
753 #define DRM_BO_FLAG_READ_CACHED 0x00080000
755 /* Mask: Force DRM_BO_FLAG_CACHED flag strictly also if it is set.
756 * Flags: Acknowledge.
758 #define DRM_BO_FLAG_FORCE_CACHING 0x00002000
761 * Mask: Force DRM_BO_FLAG_MAPPABLE flag strictly also if it is clear.
762 * Flags: Acknowledge.
764 #define DRM_BO_FLAG_FORCE_MAPPABLE 0x00004000
767 * Memory type flags that can be or'ed together in the mask, but only
768 * one appears in flags.
772 #define DRM_BO_FLAG_MEM_LOCAL 0x01000000
773 /* Translation table memory */
774 #define DRM_BO_FLAG_MEM_TT 0x02000000
776 #define DRM_BO_FLAG_MEM_VRAM 0x04000000
777 /* Up to the driver to define. */
778 #define DRM_BO_FLAG_MEM_PRIV0 0x08000000
779 #define DRM_BO_FLAG_MEM_PRIV1 0x10000000
780 #define DRM_BO_FLAG_MEM_PRIV2 0x20000000
781 #define DRM_BO_FLAG_MEM_PRIV3 0x40000000
782 #define DRM_BO_FLAG_MEM_PRIV4 0x80000000
784 /* Memory flag mask */
785 #define DRM_BO_MASK_MEM 0xFF000000
786 #define DRM_BO_MASK_MEMTYPE 0xFF0000A0
788 /* Don't block on validate and map */
789 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
790 /* Don't place this buffer on the unfenced list.*/
791 #define DRM_BO_HINT_DONT_FENCE 0x00000004
792 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
793 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
803 typedef struct drm_bo_arg_request {
804 unsigned handle; /* User space handle */
810 drm_u64_t buffer_start;
811 unsigned page_alignment;
812 unsigned expand_pad[4]; /*Future expansion */
826 } drm_bo_arg_request_t;
833 #define DRM_BO_REP_BUSY 0x00000001
835 typedef struct drm_bo_arg_reply {
841 drm_u64_t arg_handle;
843 drm_u64_t buffer_start;
844 unsigned fence_flags;
846 unsigned page_alignment;
847 unsigned expand_pad[4]; /*Future expansion */
851 typedef struct drm_bo_arg{
855 drm_bo_arg_request_t req;
856 drm_bo_arg_reply_t rep;
860 #define DRM_BO_MEM_LOCAL 0
861 #define DRM_BO_MEM_TT 1
862 #define DRM_BO_MEM_VRAM 2
863 #define DRM_BO_MEM_PRIV0 3
864 #define DRM_BO_MEM_PRIV1 4
865 #define DRM_BO_MEM_PRIV2 5
866 #define DRM_BO_MEM_PRIV3 6
867 #define DRM_BO_MEM_PRIV4 7
869 #define DRM_BO_MEM_TYPES 8 /* For now. */
871 typedef union drm_mm_init_arg{
883 unsigned expand_pad[8]; /*Future expansion */
886 drm_handle_t mm_sarea;
887 unsigned expand_pad[8]; /*Future expansion */
892 * \name Ioctls Definitions
896 #define DRM_IOCTL_BASE 'd'
897 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
898 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
899 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
900 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
902 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
903 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
904 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
905 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
906 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
907 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
908 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
909 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
911 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
912 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
913 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
914 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
915 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
916 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
917 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
918 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
919 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
920 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
921 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
923 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
925 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
926 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
928 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
929 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
930 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
931 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
932 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
933 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
934 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
935 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
936 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
937 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
938 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
939 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
940 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
942 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
943 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
944 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
945 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
946 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
947 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
948 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
949 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
951 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
952 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
954 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
956 #define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
957 #define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
958 #define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
960 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
965 * Device specific ioctls should only be in their respective headers
966 * The device specific ioctl range is from 0x40 to 0x99.
967 * Generic IOCTLS restart at 0xA0.
969 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
970 * drmCommandReadWrite().
972 #define DRM_COMMAND_BASE 0x40
973 #define DRM_COMMAND_END 0xA0