3 * Header for the Direct Rendering Manager
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
39 * The Direct Rendering Manager (DRM) is a device-independent kernel-level
40 * device driver that provides support for the XFree86 Direct Rendering
41 * Infrastructure (DRI).
43 * The DRM supports the Direct Rendering Infrastructure (DRI) in four major
45 * -# The DRM provides synchronized access to the graphics hardware via
46 * the use of an optimized two-tiered lock.
47 * -# The DRM enforces the DRI security policy for access to the graphics
48 * hardware by only allowing authenticated X11 clients access to
49 * restricted regions of memory.
50 * -# The DRM provides a generic DMA engine, complete with multiple
51 * queues and the ability to detect the need for an OpenGL context
53 * -# The DRM is extensible via the use of small device-specific modules
54 * that rely extensively on the API exported by the DRM module.
66 # define DEPRECATED __attribute__ ((deprecated))
71 #if defined(__linux__)
72 #include <asm/ioctl.h> /* For _IO* macros */
73 #define DRM_IOCTL_NR(n) _IOC_NR(n)
74 #define DRM_IOC_VOID _IOC_NONE
75 #define DRM_IOC_READ _IOC_READ
76 #define DRM_IOC_WRITE _IOC_WRITE
77 #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
78 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
79 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__)
80 #if (defined(__FreeBSD__) || defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
81 /* Prevent name collision when including sys/ioccom.h */
83 #include <sys/ioccom.h>
84 #define ioctl(a,b,c) xf86ioctl(a,b,c)
86 #include <sys/ioccom.h>
87 #endif /* __FreeBSD__ && xf86ioctl */
88 #define DRM_IOCTL_NR(n) ((n) & 0xff)
89 #define DRM_IOC_VOID IOC_VOID
90 #define DRM_IOC_READ IOC_OUT
91 #define DRM_IOC_WRITE IOC_IN
92 #define DRM_IOC_READWRITE IOC_INOUT
93 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
96 #define XFREE86_VERSION(major,minor,patch,snap) \
97 ((major << 16) | (minor << 8) | patch)
99 #ifndef CONFIG_XFREE86_VERSION
100 #define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
103 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
104 #define DRM_PROC_DEVICES "/proc/devices"
105 #define DRM_PROC_MISC "/proc/misc"
106 #define DRM_PROC_DRM "/proc/drm"
107 #define DRM_DEV_DRM "/dev/drm"
108 #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP)
109 #define DRM_DEV_UID 0
110 #define DRM_DEV_GID 0
113 #if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
117 #if defined(__linux__) || defined(__NetBSD__)
118 #define DRM_MAJOR 226
120 #define DRM_MAX_MINOR 15
122 #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
123 #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
124 #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
125 #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
127 #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
128 #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
129 #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
130 #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
131 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
133 #if defined(__linux__)
134 #if defined(__KERNEL__)
135 typedef __u64 drm_u64_t;
137 typedef unsigned long long drm_u64_t;
140 typedef unsigned int drm_handle_t;
142 typedef unsigned long drm_handle_t; /**< To mapped regions */
144 typedef unsigned int drm_context_t; /**< GLXContext handle */
145 typedef unsigned int drm_drawable_t;
146 typedef unsigned int drm_magic_t; /**< Magic for authentication */
151 * \warning If you change this structure, make sure you change
152 * XF86DRIClipRectRec in the server as well
154 * \note KW: Actually it's illegal to change either for
155 * backwards-compatibility reasons.
157 typedef struct drm_clip_rect {
165 * Drawable information.
167 typedef struct drm_drawable_info {
168 unsigned int num_rects;
169 drm_clip_rect_t *rects;
170 } drm_drawable_info_t;
175 typedef struct drm_tex_region {
178 unsigned char in_use;
179 unsigned char padding;
186 * The lock structure is a simple cache-line aligned integer. To avoid
187 * processor bus contention on a multiprocessor system, there should not be any
188 * other data stored in the same cache line.
190 typedef struct drm_hw_lock {
191 __volatile__ unsigned int lock; /**< lock variable */
192 char padding[60]; /**< Pad to cache line */
195 /* This is beyond ugly, and only works on GCC. However, it allows me to use
196 * drm.h in places (i.e., in the X-server) where I can't use size_t. The real
197 * fix is to use uint32_t instead of size_t, but that fix will break existing
198 * LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That *will*
199 * eventually happen, though. I chose 'unsigned long' to be the fallback type
200 * because that works on all the platforms I know about. Hopefully, the
201 * real fix will happen before that bites us.
205 # define DRM_SIZE_T __SIZE_TYPE__
207 # warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
208 # define DRM_SIZE_T unsigned long
212 * DRM_IOCTL_VERSION ioctl argument type.
214 * \sa drmGetVersion().
216 typedef struct drm_version {
217 int version_major; /**< Major version */
218 int version_minor; /**< Minor version */
219 int version_patchlevel; /**< Patch level */
220 DRM_SIZE_T name_len; /**< Length of name buffer */
221 char __user *name; /**< Name of driver */
222 DRM_SIZE_T date_len; /**< Length of date buffer */
223 char __user *date; /**< User-space buffer to hold date */
224 DRM_SIZE_T desc_len; /**< Length of desc buffer */
225 char __user *desc; /**< User-space buffer to hold desc */
229 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
231 * \sa drmGetBusid() and drmSetBusId().
233 typedef struct drm_unique {
234 DRM_SIZE_T unique_len; /**< Length of unique */
235 char __user *unique; /**< Unique name for driver instantiation */
240 typedef struct drm_list {
241 int count; /**< Length of user-space structures */
242 drm_version_t __user *version;
245 typedef struct drm_block {
250 * DRM_IOCTL_CONTROL ioctl argument type.
252 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
254 typedef struct drm_control {
265 * Type of memory to map.
267 typedef enum drm_map_type {
268 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
269 _DRM_REGISTERS = 1, /**< no caching, no core dump */
270 _DRM_SHM = 2, /**< shared, cached */
271 _DRM_AGP = 3, /**< AGP/GART */
272 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
273 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
278 * Memory mapping flags.
280 typedef enum drm_map_flags {
281 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
282 _DRM_READ_ONLY = 0x02,
283 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
284 _DRM_KERNEL = 0x08, /**< kernel requires access */
285 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
286 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
287 _DRM_REMOVABLE = 0x40 /**< Removable mapping */
290 typedef struct drm_ctx_priv_map {
291 unsigned int ctx_id; /**< Context requesting private mapping */
292 void *handle; /**< Handle of map */
293 } drm_ctx_priv_map_t;
296 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
301 typedef struct drm_map {
302 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
303 unsigned long size; /**< Requested physical size (bytes) */
304 drm_map_type_t type; /**< Type of memory to map */
305 drm_map_flags_t flags; /**< Flags */
306 void *handle; /**< User-space: "Handle" to pass to mmap() */
307 /**< Kernel-space: kernel-virtual address */
308 int mtrr; /**< MTRR slot used */
313 * DRM_IOCTL_GET_CLIENT ioctl argument type.
315 typedef struct drm_client {
316 int idx; /**< Which client desired? */
317 int auth; /**< Is client authenticated? */
318 unsigned long pid; /**< Process ID */
319 unsigned long uid; /**< User ID */
320 unsigned long magic; /**< Magic */
321 unsigned long iocs; /**< Ioctl count */
331 _DRM_STAT_VALUE, /**< Generic value */
332 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
333 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
335 _DRM_STAT_IRQ, /**< IRQ */
336 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
337 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
338 _DRM_STAT_DMA, /**< DMA */
339 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
340 _DRM_STAT_MISSED /**< Missed DMA opportunity */
341 /* Add to the *END* of the list */
345 * DRM_IOCTL_GET_STATS ioctl argument type.
347 typedef struct drm_stats {
351 drm_stat_type_t type;
356 * Hardware locking flags.
358 typedef enum drm_lock_flags {
359 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
360 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
361 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
362 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
363 /* These *HALT* flags aren't supported yet
364 -- they will be used to support the
365 full-screen DGA-like mode. */
366 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
367 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
371 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
373 * \sa drmGetLock() and drmUnlock().
375 typedef struct drm_lock {
377 drm_lock_flags_t flags;
384 * These values \e must match xf86drm.h.
388 typedef enum drm_dma_flags {
389 /* Flags for DMA buffer dispatch */
390 _DRM_DMA_BLOCK = 0x01, /**<
391 * Block until buffer dispatched.
393 * \note The buffer may not yet have
394 * been processed by the hardware --
395 * getting a hardware lock with the
396 * hardware quiescent will ensure
397 * that the buffer has been
400 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
401 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
403 /* Flags for DMA buffer request */
404 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
405 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
406 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
410 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
414 typedef struct drm_buf_desc {
415 int count; /**< Number of buffers of this size */
416 int size; /**< Size in bytes */
417 int low_mark; /**< Low water mark */
418 int high_mark; /**< High water mark */
420 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
421 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
422 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
423 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
424 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
426 unsigned long agp_start; /**<
427 * Start address of where the AGP buffers are
428 * in the AGP aperture
433 * DRM_IOCTL_INFO_BUFS ioctl argument type.
435 typedef struct drm_buf_info {
436 int count; /**< Number of buffers described in list */
437 drm_buf_desc_t __user *list; /**< List of buffer descriptions */
441 * DRM_IOCTL_FREE_BUFS ioctl argument type.
443 typedef struct drm_buf_free {
453 typedef struct drm_buf_pub {
454 int idx; /**< Index into the master buffer list */
455 int total; /**< Buffer size */
456 int used; /**< Amount of buffer in use (for DMA) */
457 void __user *address; /**< Address of buffer */
461 * DRM_IOCTL_MAP_BUFS ioctl argument type.
463 typedef struct drm_buf_map {
464 int count; /**< Length of the buffer list */
465 #if defined(__cplusplus)
466 void __user *c_virtual;
468 void __user *virtual; /**< Mmap'd area in user-virtual */
470 drm_buf_pub_t __user *list; /**< Buffer information */
474 * DRM_IOCTL_DMA ioctl argument type.
476 * Indices here refer to the offset into the buffer list in drm_buf_get.
480 typedef struct drm_dma {
481 int context; /**< Context handle */
482 int send_count; /**< Number of buffers to send */
483 int __user *send_indices; /**< List of handles to buffers */
484 int __user *send_sizes; /**< Lengths of data to send */
485 drm_dma_flags_t flags; /**< Flags */
486 int request_count; /**< Number of buffers requested */
487 int request_size; /**< Desired size for buffers */
488 int __user *request_indices; /**< Buffer information */
489 int __user *request_sizes;
490 int granted_count; /**< Number of buffers granted */
494 _DRM_CONTEXT_PRESERVED = 0x01,
495 _DRM_CONTEXT_2DONLY = 0x02
499 * DRM_IOCTL_ADD_CTX ioctl argument type.
501 * \sa drmCreateContext() and drmDestroyContext().
503 typedef struct drm_ctx {
504 drm_context_t handle;
505 drm_ctx_flags_t flags;
509 * DRM_IOCTL_RES_CTX ioctl argument type.
511 typedef struct drm_ctx_res {
513 drm_ctx_t __user *contexts;
517 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
519 typedef struct drm_draw {
520 drm_drawable_t handle;
524 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
527 DRM_DRAWABLE_CLIPRECTS,
528 } drm_drawable_info_type_t;
530 typedef struct drm_update_draw {
531 drm_drawable_t handle;
534 unsigned long long data;
538 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
540 typedef struct drm_auth {
545 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
547 * \sa drmGetInterruptFromBusID().
549 typedef struct drm_irq_busid {
550 int irq; /**< IRQ number */
551 int busnum; /**< bus number */
552 int devnum; /**< device number */
553 int funcnum; /**< function number */
557 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
558 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
559 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
560 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
561 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
562 } drm_vblank_seq_type_t;
564 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
565 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
566 _DRM_VBLANK_NEXTONMISS)
568 struct drm_wait_vblank_request {
569 drm_vblank_seq_type_t type;
570 unsigned int sequence;
571 unsigned long signal;
574 struct drm_wait_vblank_reply {
575 drm_vblank_seq_type_t type;
576 unsigned int sequence;
582 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
584 * \sa drmWaitVBlank().
586 typedef union drm_wait_vblank {
587 struct drm_wait_vblank_request request;
588 struct drm_wait_vblank_reply reply;
592 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
594 * \sa drmAgpEnable().
596 typedef struct drm_agp_mode {
597 unsigned long mode; /**< AGP mode */
601 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
603 * \sa drmAgpAlloc() and drmAgpFree().
605 typedef struct drm_agp_buffer {
606 unsigned long size; /**< In bytes -- will round to page boundary */
607 unsigned long handle; /**< Used for binding / unbinding */
608 unsigned long type; /**< Type of memory to allocate */
609 unsigned long physical; /**< Physical used by i810 */
613 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
615 * \sa drmAgpBind() and drmAgpUnbind().
617 typedef struct drm_agp_binding {
618 unsigned long handle; /**< From drm_agp_buffer */
619 unsigned long offset; /**< In bytes -- will round to page boundary */
623 * DRM_IOCTL_AGP_INFO ioctl argument type.
625 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
626 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
627 * drmAgpVendorId() and drmAgpDeviceId().
629 typedef struct drm_agp_info {
630 int agp_version_major;
631 int agp_version_minor;
633 unsigned long aperture_base; /**< physical address */
634 unsigned long aperture_size; /**< bytes */
635 unsigned long memory_allowed; /**< bytes */
636 unsigned long memory_used;
638 /** \name PCI information */
640 unsigned short id_vendor;
641 unsigned short id_device;
646 * DRM_IOCTL_SG_ALLOC ioctl argument type.
648 typedef struct drm_scatter_gather {
649 unsigned long size; /**< In bytes -- will round to page boundary */
650 unsigned long handle; /**< Used for mapping / unmapping */
651 } drm_scatter_gather_t;
654 * DRM_IOCTL_SET_VERSION ioctl argument type.
656 typedef struct drm_set_version {
665 #define DRM_FENCE_FLAG_EMIT 0x00000001
666 #define DRM_FENCE_FLAG_SHAREABLE 0x00000002
667 #define DRM_FENCE_FLAG_WAIT_LAZY 0x00000004
668 #define DRM_FENCE_FLAG_WAIT_IGNORE_SIGNALS 0x00000008
670 /* Reserved for driver use */
671 #define DRM_FENCE_MASK_DRIVER 0xFF000000
673 #define DRM_FENCE_TYPE_EXE 0x00000001
675 typedef struct drm_fence_arg {
681 unsigned expand_pad[4]; /*Future expansion */
686 drm_fence_unreference,
695 /* Buffer permissions, referring to how the GPU uses the buffers.
696 these translate to fence types used for the buffers.
697 Typically a texture buffer is read, A destination buffer is write and
698 a command (batch-) buffer is exe. Can be or-ed together. */
700 #define DRM_BO_FLAG_READ 0x00000001
701 #define DRM_BO_FLAG_WRITE 0x00000002
702 #define DRM_BO_FLAG_EXE 0x00000004
705 * Status flags. Can be read to determine the actual state of a buffer.
709 * Cannot evict this buffer. Not even with force. This type of buffer should
710 * only be available for root, and must be manually removed before buffer
711 * manager shutdown or swapout.
713 #define DRM_BO_FLAG_NO_EVICT 0x00000010
714 /* Always keep a system memory shadow to a vram buffer */
715 #define DRM_BO_FLAG_SHADOW_VRAM 0x00000020
716 /* The buffer is shareable with other processes */
717 #define DRM_BO_FLAG_SHAREABLE 0x00000040
718 /* The buffer is currently cached */
719 #define DRM_BO_FLAG_CACHED 0x00000080
720 /* Make sure that every time this buffer is validated, it ends up on the same
721 * location. The buffer will also not be evicted when claiming space for
722 * other buffers. Basically a pinned buffer but it may be thrown out as
723 * part of buffer manager shutdown or swapout. Not supported yet.*/
724 #define DRM_BO_FLAG_NO_MOVE 0x00000100
726 /* Make sure the buffer is in cached memory when mapped for reading */
727 #define DRM_BO_FLAG_READ_CACHED 0x00080000
728 /* When there is a choice between VRAM and TT, prefer VRAM.
729 The default behaviour is to prefer TT. */
730 #define DRM_BO_FLAG_PREFER_VRAM 0x00040000
731 /* Bind this buffer cached if the hardware supports it. */
732 #define DRM_BO_FLAG_BIND_CACHED 0x0002000
735 #define DRM_BO_FLAG_MEM_LOCAL 0x01000000
736 /* Translation table memory */
737 #define DRM_BO_FLAG_MEM_TT 0x02000000
739 #define DRM_BO_FLAG_MEM_VRAM 0x04000000
740 /* Unmappable Vram memory */
741 #define DRM_BO_FLAG_MEM_VRAM_NM 0x08000000
742 /* Memory flag mask */
743 #define DRM_BO_MASK_MEM 0xFF000000
745 /* When creating a buffer, Avoid system storage even if allowed */
746 #define DRM_BO_HINT_AVOID_LOCAL 0x00000001
747 /* Don't block on validate and map */
748 #define DRM_BO_HINT_DONT_BLOCK 0x00000002
749 /* Don't place this buffer on the unfenced list.*/
750 #define DRM_BO_HINT_DONT_FENCE 0x00000004
751 #define DRM_BO_HINT_WAIT_LAZY 0x00000008
752 #define DRM_BO_HINT_ALLOW_UNFENCED_MAP 0x00000010
755 /* Driver specific flags. Could be for example rendering engine */
756 #define DRM_BO_MASK_DRIVER 0x00F00000
765 typedef struct drm_bo_arg_request {
766 unsigned handle; /* User space handle */
772 drm_u64_t buffer_start;
773 unsigned page_alignment;
774 unsigned expand_pad[4]; /*Future expansion */
788 } drm_bo_arg_request_t;
795 #define DRM_BO_REP_BUSY 0x00000001
797 typedef struct drm_bo_arg_reply {
803 drm_u64_t arg_handle;
805 drm_u64_t buffer_start;
806 unsigned fence_flags;
808 unsigned page_alignment;
809 unsigned expand_pad[4]; /*Future expansion */
813 typedef struct drm_bo_arg{
817 drm_bo_arg_request_t req;
818 drm_bo_arg_reply_t rep;
822 #define DRM_BO_MEM_LOCAL 0
823 #define DRM_BO_MEM_TT 1
824 #define DRM_BO_MEM_VRAM 2
825 #define DRM_BO_MEM_VRAM_NM 3
826 #define DRM_BO_MEM_TYPES 2 /* For now. */
828 typedef union drm_mm_init_arg{
840 unsigned expand_pad[8]; /*Future expansion */
843 drm_handle_t mm_sarea;
844 unsigned expand_pad[8]; /*Future expansion */
851 * \name Ioctls Definitions
855 #define DRM_IOCTL_BASE 'd'
856 #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
857 #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
858 #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
859 #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
861 #define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
862 #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
863 #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
864 #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
865 #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
866 #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
867 #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
868 #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
870 #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
871 #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
872 #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
873 #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
874 #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
875 #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
876 #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
877 #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
878 #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
879 #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
880 #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
882 #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
884 #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
885 #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
887 #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
888 #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
889 #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
890 #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
891 #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
892 #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
893 #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
894 #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
895 #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
896 #define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
897 #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
898 #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
899 #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
901 #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
902 #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
903 #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
904 #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
905 #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
906 #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
907 #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
908 #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
910 #define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
911 #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
913 #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
916 #define DRM_IOCTL_FENCE DRM_IOWR(0x3b, drm_fence_arg_t)
917 #define DRM_IOCTL_BUFOBJ DRM_IOWR(0x3d, drm_bo_arg_t)
918 #define DRM_IOCTL_MM_INIT DRM_IOWR(0x3e, drm_mm_init_arg_t)
921 #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
926 * Device specific ioctls should only be in their respective headers
927 * The device specific ioctl range is from 0x40 to 0x99.
928 * Generic IOCTLS restart at 0xA0.
930 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
931 * drmCommandReadWrite().
933 #define DRM_COMMAND_BASE 0x40
934 #define DRM_COMMAND_END 0xA0