1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
41 drm_i915_private_t *dev_priv = dev->dev_private;
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
44 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
45 u32 last_acthd = I915_READ(acthd_reg);
49 for (i = 0; i < 100000; i++) {
50 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
51 acthd = I915_READ(acthd_reg);
52 ring->space = ring->head - (ring->tail + 8);
54 ring->space += ring->Size;
58 if (ring->head != last_head)
61 if (acthd != last_acthd)
64 last_head = ring->head;
66 msleep_interruptible (10);
72 int i915_init_hardware_status(struct drm_device *dev)
74 drm_i915_private_t *dev_priv = dev->dev_private;
75 /* Program Hardware Status Page */
76 dev_priv->status_page_dmah =
77 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
79 if (!dev_priv->status_page_dmah) {
80 DRM_ERROR("Can not allocate hardware status page\n");
83 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
84 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
86 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
88 I915_WRITE(0x02080, dev_priv->dma_status_page);
89 DRM_DEBUG("Enabled hardware status page\n");
93 void i915_free_hardware_status(struct drm_device *dev)
95 drm_i915_private_t *dev_priv = dev->dev_private;
96 if (dev_priv->status_page_dmah) {
97 drm_pci_free(dev, dev_priv->status_page_dmah);
98 dev_priv->status_page_dmah = NULL;
99 /* Need to rewrite hardware status page */
100 I915_WRITE(0x02080, 0x1ffff000);
103 if (dev_priv->status_gfx_addr) {
104 dev_priv->status_gfx_addr = 0;
105 drm_core_ioremapfree(&dev_priv->hws_map, dev);
106 I915_WRITE(0x02080, 0x1ffff000);
110 #if I915_RING_VALIDATE
112 * Validate the cached ring tail value
114 * If the X server writes to the ring and DRM doesn't
115 * reload the head and tail pointers, it will end up writing
116 * data to the wrong place in the ring, causing havoc.
118 void i915_ring_validate(struct drm_device *dev, const char *func, int line)
120 drm_i915_private_t *dev_priv = dev->dev_private;
121 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
122 u32 tail = I915_READ(LP_RING+RING_TAIL) & HEAD_ADDR;
123 u32 head = I915_READ(LP_RING+RING_HEAD) & HEAD_ADDR;
125 if (tail != ring->tail) {
126 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n",
128 ring->head, head, ring->tail, tail);
134 void i915_kernel_lost_context(struct drm_device * dev)
136 drm_i915_private_t *dev_priv = dev->dev_private;
137 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
139 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
140 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
141 ring->space = ring->head - (ring->tail + 8);
143 ring->space += ring->Size;
146 static int i915_dma_cleanup(struct drm_device * dev)
148 drm_i915_private_t *dev_priv = dev->dev_private;
149 /* Make sure interrupts are disabled here because the uninstall ioctl
150 * may not have been called from userspace and after dev_private
151 * is freed, it's too late.
153 if (dev->irq_enabled)
154 drm_irq_uninstall(dev);
156 if (dev_priv->ring.virtual_start) {
157 drm_core_ioremapfree(&dev_priv->ring.map, dev);
158 dev_priv->ring.virtual_start = 0;
159 dev_priv->ring.map.handle = 0;
160 dev_priv->ring.map.size = 0;
163 if (I915_NEED_GFX_HWS(dev))
164 i915_free_hardware_status(dev);
169 #if defined(I915_HAVE_BUFFER)
170 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
171 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
172 #define DRI2_SAREA_BLOCK_NEXT(p) \
173 ((void *) ((unsigned char *) (p) + \
174 DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
176 #define DRI2_SAREA_BLOCK_END 0x0000
177 #define DRI2_SAREA_BLOCK_LOCK 0x0001
178 #define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002
181 setup_dri2_sarea(struct drm_device * dev,
182 struct drm_file *file_priv,
183 drm_i915_init_t * init)
185 drm_i915_private_t *dev_priv = dev->dev_private;
187 unsigned int *p, *end, *next;
189 mutex_lock(&dev->struct_mutex);
191 drm_lookup_buffer_object(file_priv,
192 init->sarea_handle, 1);
193 mutex_unlock(&dev->struct_mutex);
195 if (!dev_priv->sarea_bo) {
196 DRM_ERROR("did not find sarea bo\n");
200 ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
201 dev_priv->sarea_bo->num_pages,
202 &dev_priv->sarea_kmap);
204 DRM_ERROR("could not map sarea bo\n");
208 p = dev_priv->sarea_kmap.virtual;
209 end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
210 while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
211 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
212 case DRI2_SAREA_BLOCK_LOCK:
213 dev->lock.hw_lock = (void *) (p + 1);
214 dev->sigdata.lock = dev->lock.hw_lock;
217 next = DRI2_SAREA_BLOCK_NEXT(p);
218 if (next <= p || end < next) {
219 DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
230 static int i915_initialize(struct drm_device * dev,
231 struct drm_file *file_priv,
232 drm_i915_init_t * init)
234 drm_i915_private_t *dev_priv = dev->dev_private;
235 #if defined(I915_HAVE_BUFFER)
238 dev_priv->sarea = drm_getsarea(dev);
239 if (!dev_priv->sarea) {
240 DRM_ERROR("can not find sarea!\n");
241 i915_dma_cleanup(dev);
245 #ifdef I915_HAVE_BUFFER
246 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
249 if (init->sarea_priv_offset)
250 dev_priv->sarea_priv = (drm_i915_sarea_t *)
251 ((u8 *) dev_priv->sarea->handle +
252 init->sarea_priv_offset);
254 /* No sarea_priv for you! */
255 dev_priv->sarea_priv = NULL;
258 if (init->ring_size != 0) {
259 dev_priv->ring.Size = init->ring_size;
260 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
262 dev_priv->ring.map.offset = init->ring_start;
263 dev_priv->ring.map.size = init->ring_size;
264 dev_priv->ring.map.type = 0;
265 dev_priv->ring.map.flags = 0;
266 dev_priv->ring.map.mtrr = 0;
268 drm_core_ioremap(&dev_priv->ring.map, dev);
270 if (dev_priv->ring.map.handle == NULL) {
271 i915_dma_cleanup(dev);
272 DRM_ERROR("can not ioremap virtual address for"
277 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
280 dev_priv->cpp = init->cpp;
282 if (dev_priv->sarea_priv)
283 dev_priv->sarea_priv->pf_current_page = 0;
285 /* We are using separate values as placeholders for mechanisms for
286 * private backbuffer/depthbuffer usage.
289 /* Allow hardware batchbuffers unless told otherwise.
291 dev_priv->allow_batchbuffer = 1;
293 /* Enable vblank on pipe A for older X servers
295 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
297 #ifdef I915_HAVE_BUFFER
298 mutex_init(&dev_priv->cmdbuf_mutex);
300 #if defined(I915_HAVE_BUFFER)
301 if (init->func == I915_INIT_DMA2) {
302 ret = setup_dri2_sarea(dev, file_priv, init);
304 i915_dma_cleanup(dev);
305 DRM_ERROR("could not set up dri2 sarea\n");
314 static int i915_dma_resume(struct drm_device * dev)
316 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
320 if (!dev_priv->sarea) {
321 DRM_ERROR("can not find sarea!\n");
325 if (dev_priv->ring.map.handle == NULL) {
326 DRM_ERROR("can not ioremap virtual address for"
331 /* Program Hardware Status Page */
332 if (!dev_priv->hw_status_page) {
333 DRM_ERROR("Can not find hardware status page\n");
336 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
338 if (dev_priv->status_gfx_addr != 0)
339 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
341 I915_WRITE(0x02080, dev_priv->dma_status_page);
342 DRM_DEBUG("Enabled hardware status page\n");
347 static int i915_dma_init(struct drm_device *dev, void *data,
348 struct drm_file *file_priv)
350 drm_i915_init_t *init = data;
353 switch (init->func) {
356 retcode = i915_initialize(dev, file_priv, init);
358 case I915_CLEANUP_DMA:
359 retcode = i915_dma_cleanup(dev);
361 case I915_RESUME_DMA:
362 retcode = i915_dma_resume(dev);
372 /* Implement basically the same security restrictions as hardware does
373 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
375 * Most of the calculations below involve calculating the size of a
376 * particular instruction. It's important to get the size right as
377 * that tells us where the next instruction to check is. Any illegal
378 * instruction detected will be given a size of zero, which is a
379 * signal to abort the rest of the buffer.
381 static int do_validate_cmd(int cmd)
383 switch (((cmd >> 29) & 0x7)) {
385 switch ((cmd >> 23) & 0x3f) {
387 return 1; /* MI_NOOP */
389 return 1; /* MI_FLUSH */
391 return 0; /* disallow everything else */
395 return 0; /* reserved */
397 return (cmd & 0xff) + 2; /* 2d commands */
399 if (((cmd >> 24) & 0x1f) <= 0x18)
402 switch ((cmd >> 24) & 0x1f) {
406 switch ((cmd >> 16) & 0xff) {
408 return (cmd & 0x1f) + 2;
410 return (cmd & 0xf) + 2;
412 return (cmd & 0xffff) + 2;
416 return (cmd & 0xffff) + 1;
420 if ((cmd & (1 << 23)) == 0) /* inline vertices */
421 return (cmd & 0x1ffff) + 2;
422 else if (cmd & (1 << 17)) /* indirect random */
423 if ((cmd & 0xffff) == 0)
424 return 0; /* unknown length, too hard */
426 return (((cmd & 0xffff) + 1) / 2) + 1;
428 return 2; /* indirect sequential */
439 static int validate_cmd(int cmd)
441 int ret = do_validate_cmd(cmd);
443 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
448 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
451 drm_i915_private_t *dev_priv = dev->dev_private;
455 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
458 BEGIN_LP_RING((dwords+1)&~1);
460 for (i = 0; i < dwords;) {
463 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
466 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
472 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
488 int i915_emit_box(struct drm_device * dev,
489 struct drm_clip_rect __user * boxes,
490 int i, int DR1, int DR4)
492 drm_i915_private_t *dev_priv = dev->dev_private;
493 struct drm_clip_rect box;
496 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
500 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
501 DRM_ERROR("Bad box %d,%d..%d,%d\n",
502 box.x1, box.y1, box.x2, box.y2);
508 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
509 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
510 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
515 OUT_RING(GFX_OP_DRAWRECT_INFO);
517 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
518 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
527 /* XXX: Emitting the counter should really be moved to part of the IRQ
528 * emit. For now, do it in both places:
531 void i915_emit_breadcrumb(struct drm_device *dev)
533 drm_i915_private_t *dev_priv = dev->dev_private;
536 if (++dev_priv->counter > BREADCRUMB_MASK) {
537 dev_priv->counter = 1;
538 DRM_DEBUG("Breadcrumb counter wrapped around\n");
541 if (dev_priv->sarea_priv)
542 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
545 OUT_RING(MI_STORE_DWORD_INDEX);
546 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
547 OUT_RING(dev_priv->counter);
553 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
555 drm_i915_private_t *dev_priv = dev->dev_private;
556 uint32_t flush_cmd = MI_FLUSH;
561 i915_kernel_lost_context(dev);
574 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
575 drm_i915_cmdbuffer_t * cmd)
577 #ifdef I915_HAVE_FENCE
578 drm_i915_private_t *dev_priv = dev->dev_private;
580 int nbox = cmd->num_cliprects;
581 int i = 0, count, ret;
584 DRM_ERROR("alignment\n");
588 i915_kernel_lost_context(dev);
590 count = nbox ? nbox : 1;
592 for (i = 0; i < count; i++) {
594 ret = i915_emit_box(dev, cmd->cliprects, i,
600 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
605 i915_emit_breadcrumb(dev);
606 #ifdef I915_HAVE_FENCE
607 if (unlikely((dev_priv->counter & 0xFF) == 0))
608 drm_fence_flush_old(dev, 0, dev_priv->counter);
613 int i915_dispatch_batchbuffer(struct drm_device * dev,
614 drm_i915_batchbuffer_t * batch)
616 drm_i915_private_t *dev_priv = dev->dev_private;
617 struct drm_clip_rect __user *boxes = batch->cliprects;
618 int nbox = batch->num_cliprects;
622 if ((batch->start | batch->used) & 0x7) {
623 DRM_ERROR("alignment\n");
627 i915_kernel_lost_context(dev);
629 count = nbox ? nbox : 1;
631 for (i = 0; i < count; i++) {
633 int ret = i915_emit_box(dev, boxes, i,
634 batch->DR1, batch->DR4);
639 if (IS_I830(dev) || IS_845G(dev)) {
641 OUT_RING(MI_BATCH_BUFFER);
642 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
643 OUT_RING(batch->start + batch->used - 4);
649 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
650 OUT_RING(batch->start);
652 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
653 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
659 i915_emit_breadcrumb(dev);
660 #ifdef I915_HAVE_FENCE
661 if (unlikely((dev_priv->counter & 0xFF) == 0))
662 drm_fence_flush_old(dev, 0, dev_priv->counter);
667 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
669 drm_i915_private_t *dev_priv = dev->dev_private;
670 u32 num_pages, current_page, next_page, dspbase;
671 int shift = 2 * plane, x, y;
674 /* Calculate display base offset */
675 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
676 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
677 next_page = (current_page + 1) % num_pages;
682 dspbase = dev_priv->sarea_priv->front_offset;
685 dspbase = dev_priv->sarea_priv->back_offset;
688 dspbase = dev_priv->sarea_priv->third_offset;
693 x = dev_priv->sarea_priv->planeA_x;
694 y = dev_priv->sarea_priv->planeA_y;
696 x = dev_priv->sarea_priv->planeB_x;
697 y = dev_priv->sarea_priv->planeB_y;
700 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
702 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
707 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
708 MI_WAIT_FOR_PLANE_A_FLIP)));
709 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
710 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
711 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
715 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
716 dev_priv->sarea_priv->pf_current_page |= next_page << shift;
719 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
721 drm_i915_private_t *dev_priv = dev->dev_private;
724 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
725 planes, dev_priv->sarea_priv->pf_current_page);
727 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
729 for (i = 0; i < 2; i++)
730 if (planes & (1 << i))
731 i915_do_dispatch_flip(dev, i, sync);
733 i915_emit_breadcrumb(dev);
734 #ifdef I915_HAVE_FENCE
735 if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
736 drm_fence_flush_old(dev, 0, dev_priv->counter);
740 int i915_quiescent(struct drm_device *dev)
742 drm_i915_private_t *dev_priv = dev->dev_private;
745 i915_kernel_lost_context(dev);
746 ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
749 i915_kernel_lost_context (dev);
750 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
753 dev_priv->ring.space);
758 static int i915_flush_ioctl(struct drm_device *dev, void *data,
759 struct drm_file *file_priv)
762 LOCK_TEST_WITH_RETURN(dev, file_priv);
764 return i915_quiescent(dev);
767 static int i915_batchbuffer(struct drm_device *dev, void *data,
768 struct drm_file *file_priv)
770 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
771 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
772 dev_priv->sarea_priv;
773 drm_i915_batchbuffer_t *batch = data;
776 if (!dev_priv->allow_batchbuffer) {
777 DRM_ERROR("Batchbuffer ioctl disabled\n");
781 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
782 batch->start, batch->used, batch->num_cliprects);
784 LOCK_TEST_WITH_RETURN(dev, file_priv);
786 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
787 batch->num_cliprects *
788 sizeof(struct drm_clip_rect)))
791 ret = i915_dispatch_batchbuffer(dev, batch);
793 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
797 static int i915_cmdbuffer(struct drm_device *dev, void *data,
798 struct drm_file *file_priv)
800 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
801 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
802 dev_priv->sarea_priv;
803 drm_i915_cmdbuffer_t *cmdbuf = data;
806 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
807 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
809 LOCK_TEST_WITH_RETURN(dev, file_priv);
811 if (cmdbuf->num_cliprects &&
812 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
813 cmdbuf->num_cliprects *
814 sizeof(struct drm_clip_rect))) {
815 DRM_ERROR("Fault accessing cliprects\n");
819 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
821 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
825 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
829 #if defined(DRM_DEBUG_CODE)
830 #define DRM_DEBUG_RELOCATION (drm_debug != 0)
832 #define DRM_DEBUG_RELOCATION 0
835 static int i915_do_cleanup_pageflip(struct drm_device * dev)
837 drm_i915_private_t *dev_priv = dev->dev_private;
838 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
842 for (i = 0, planes = 0; i < 2; i++)
843 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
844 dev_priv->sarea_priv->pf_current_page =
845 (dev_priv->sarea_priv->pf_current_page &
846 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
852 i915_dispatch_flip(dev, planes, 0);
857 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
859 drm_i915_flip_t *param = data;
863 LOCK_TEST_WITH_RETURN(dev, file_priv);
865 /* This is really planes */
866 if (param->pipes & ~0x3) {
867 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
872 i915_dispatch_flip(dev, param->pipes, 0);
878 static int i915_getparam(struct drm_device *dev, void *data,
879 struct drm_file *file_priv)
881 drm_i915_private_t *dev_priv = dev->dev_private;
882 drm_i915_getparam_t *param = data;
886 DRM_ERROR("called with no initialization\n");
890 switch (param->param) {
891 case I915_PARAM_IRQ_ACTIVE:
892 value = dev->irq_enabled ? 1 : 0;
894 case I915_PARAM_ALLOW_BATCHBUFFER:
895 value = dev_priv->allow_batchbuffer ? 1 : 0;
897 case I915_PARAM_LAST_DISPATCH:
898 value = READ_BREADCRUMB(dev_priv);
900 case I915_PARAM_CHIPSET_ID:
901 value = dev->pci_device;
904 DRM_ERROR("Unknown parameter %d\n", param->param);
908 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
909 DRM_ERROR("DRM_COPY_TO_USER failed\n");
916 static int i915_setparam(struct drm_device *dev, void *data,
917 struct drm_file *file_priv)
919 drm_i915_private_t *dev_priv = dev->dev_private;
920 drm_i915_setparam_t *param = data;
923 DRM_ERROR("called with no initialization\n");
927 switch (param->param) {
928 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
930 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
931 dev_priv->tex_lru_log_granularity = param->value;
933 case I915_SETPARAM_ALLOW_BATCHBUFFER:
934 dev_priv->allow_batchbuffer = param->value;
937 DRM_ERROR("unknown parameter %d\n", param->param);
944 drm_i915_mmio_entry_t mmio_table[] = {
945 [MMIO_REGS_PS_DEPTH_COUNT] = {
946 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
952 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
954 static int i915_mmio(struct drm_device *dev, void *data,
955 struct drm_file *file_priv)
958 drm_i915_private_t *dev_priv = dev->dev_private;
959 drm_i915_mmio_entry_t *e;
960 drm_i915_mmio_t *mmio = data;
965 DRM_ERROR("called with no initialization\n");
969 if (mmio->reg >= mmio_table_size)
972 e = &mmio_table[mmio->reg];
973 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
975 switch (mmio->read_write) {
977 if (!(e->flag & I915_MMIO_MAY_READ))
979 for (i = 0; i < e->size / 4; i++)
980 buf[i] = I915_READ(e->offset + i * 4);
981 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
982 DRM_ERROR("DRM_COPY_TO_USER failed\n");
987 case I915_MMIO_WRITE:
988 if (!(e->flag & I915_MMIO_MAY_WRITE))
990 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
991 DRM_ERROR("DRM_COPY_TO_USER failed\n");
994 for (i = 0; i < e->size / 4; i++)
995 I915_WRITE(e->offset + i * 4, buf[i]);
1001 static int i915_set_status_page(struct drm_device *dev, void *data,
1002 struct drm_file *file_priv)
1004 drm_i915_private_t *dev_priv = dev->dev_private;
1005 drm_i915_hws_addr_t *hws = data;
1007 if (!I915_NEED_GFX_HWS(dev))
1011 DRM_ERROR("called with no initialization\n");
1014 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1016 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1018 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1019 dev_priv->hws_map.size = 4*1024;
1020 dev_priv->hws_map.type = 0;
1021 dev_priv->hws_map.flags = 0;
1022 dev_priv->hws_map.mtrr = 0;
1024 drm_core_ioremap(&dev_priv->hws_map, dev);
1025 if (dev_priv->hws_map.handle == NULL) {
1026 i915_dma_cleanup(dev);
1027 dev_priv->status_gfx_addr = 0;
1028 DRM_ERROR("can not ioremap virtual address for"
1029 " G33 hw status page\n");
1032 dev_priv->hw_status_page = dev_priv->hws_map.handle;
1034 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1035 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1036 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1037 dev_priv->status_gfx_addr);
1038 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1042 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1044 struct drm_i915_private *dev_priv;
1045 unsigned long base, size;
1046 int ret = 0, num_pipes = 2, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1048 /* i915 has 4 more counters */
1050 dev->types[6] = _DRM_STAT_IRQ;
1051 dev->types[7] = _DRM_STAT_PRIMARY;
1052 dev->types[8] = _DRM_STAT_SECONDARY;
1053 dev->types[9] = _DRM_STAT_DMA;
1055 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1056 if (dev_priv == NULL)
1059 memset(dev_priv, 0, sizeof(drm_i915_private_t));
1061 dev->dev_private = (void *)dev_priv;
1062 dev_priv->dev = dev;
1064 /* Add register map (needed for suspend/resume) */
1065 base = drm_get_resource_start(dev, mmio_bar);
1066 size = drm_get_resource_len(dev, mmio_bar);
1068 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1069 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1074 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1075 intel_init_chipset_flush_compat(dev);
1077 intel_opregion_init(dev);
1081 if (!I915_NEED_GFX_HWS(dev)) {
1082 ret = i915_init_hardware_status(dev);
1087 I915_WRITE16(HWSTAM, 0xeffe);
1088 I915_WRITE16(IMR, 0x0);
1089 I915_WRITE16(IER, 0x0);
1091 DRM_SPININIT(&dev_priv->swaps_lock, "swap");
1092 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
1093 dev_priv->swaps_pending = 0;
1095 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
1096 dev_priv->user_irq_refcount = 0;
1097 dev_priv->irq_mask_reg = ~0;
1099 ret = drm_vblank_init(dev, num_pipes);
1103 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1104 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1106 i915_enable_interrupt(dev);
1107 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1110 * Initialize the hardware status page IRQ location.
1113 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1118 int i915_driver_unload(struct drm_device *dev)
1120 struct drm_i915_private *dev_priv = dev->dev_private;
1124 dev_priv->vblank_pipe = 0;
1126 dev_priv->irq_enabled = 0;
1127 I915_WRITE(HWSTAM, 0xffffffff);
1128 I915_WRITE(IMR, 0xffffffff);
1129 I915_WRITE(IER, 0x0);
1131 temp = I915_READ(PIPEASTAT);
1132 I915_WRITE(PIPEASTAT, temp);
1133 temp = I915_READ(PIPEBSTAT);
1134 I915_WRITE(PIPEBSTAT, temp);
1135 temp = I915_READ(IIR);
1136 I915_WRITE(IIR, temp);
1139 i915_free_hardware_status(dev);
1141 drm_rmmap(dev, dev_priv->mmio_map);
1144 intel_opregion_free(dev);
1147 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1150 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1151 intel_fini_chipset_flush_compat(dev);
1157 void i915_driver_lastclose(struct drm_device * dev)
1159 drm_i915_private_t *dev_priv = dev->dev_private;
1161 /* agp off can use this to get called before dev_priv */
1165 #ifdef I915_HAVE_BUFFER
1166 if (dev_priv->val_bufs) {
1167 vfree(dev_priv->val_bufs);
1168 dev_priv->val_bufs = NULL;
1171 i915_gem_lastclose(dev);
1173 if (drm_getsarea(dev) && dev_priv->sarea_priv)
1174 i915_do_cleanup_pageflip(dev);
1175 if (dev_priv->agp_heap)
1176 i915_mem_takedown(&(dev_priv->agp_heap));
1177 #if defined(I915_HAVE_BUFFER)
1178 if (dev_priv->sarea_kmap.virtual) {
1179 drm_bo_kunmap(&dev_priv->sarea_kmap);
1180 dev_priv->sarea_kmap.virtual = NULL;
1181 dev->lock.hw_lock = NULL;
1182 dev->sigdata.lock = NULL;
1185 if (dev_priv->sarea_bo) {
1186 mutex_lock(&dev->struct_mutex);
1187 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
1188 mutex_unlock(&dev->struct_mutex);
1189 dev_priv->sarea_bo = NULL;
1192 i915_dma_cleanup(dev);
1195 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1197 struct drm_i915_file_private *i915_file_priv;
1200 i915_file_priv = (struct drm_i915_file_private *)
1201 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
1203 if (!i915_file_priv)
1206 file_priv->driver_priv = i915_file_priv;
1208 i915_file_priv->mm.last_gem_seqno = 0;
1209 i915_file_priv->mm.last_gem_throttle_seqno = 0;
1214 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1216 drm_i915_private_t *dev_priv = dev->dev_private;
1217 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1220 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1222 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1224 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
1227 struct drm_ioctl_desc i915_ioctls[] = {
1228 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1229 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1230 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1231 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1232 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1233 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1234 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1235 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1236 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1237 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1238 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1239 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1240 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1241 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1242 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1243 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1244 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1245 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1246 #ifdef I915_HAVE_BUFFER
1247 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1249 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
1250 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1251 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1252 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1253 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1254 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1255 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH),
1256 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH),
1257 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1258 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1259 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1260 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1261 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1262 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1263 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1264 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1267 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1270 * Determine if the device really is AGP or not.
1272 * All Intel graphics chipsets are treated as AGP, even if they are really
1275 * \param dev The device to be tested.
1278 * A value of 1 is always retured to indictate every i9x5 is AGP.
1280 int i915_driver_device_is_agp(struct drm_device * dev)
1285 int i915_driver_firstopen(struct drm_device *dev)
1287 #ifdef I915_HAVE_BUFFER
1288 drm_bo_driver_init(dev);