1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
41 struct drm_i915_private *dev_priv = dev->dev_private;
42 struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
46 for (i = 0; i < 10000; i++) {
47 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
48 ring->space = ring->head - (ring->tail + 8);
50 ring->space += ring->Size;
54 if (ring->head != last_head)
57 last_head = ring->head;
64 void i915_kernel_lost_context(struct drm_device * dev)
66 struct drm_i915_private *dev_priv = dev->dev_private;
67 struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
69 /* we should never lose context on the ring with modesetting
70 * as we don't expose it to userspace */
71 if (drm_core_check_feature(dev, DRIVER_MODESET))
74 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
75 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
76 ring->space = ring->head - (ring->tail + 8);
78 ring->space += ring->Size;
81 int i915_dma_cleanup(struct drm_device * dev)
83 struct drm_i915_private *dev_priv = dev->dev_private;
85 if (drm_core_check_feature(dev, DRIVER_MODESET))
88 /* Make sure interrupts are disabled here because the uninstall ioctl
89 * may not have been called from userspace and after dev_private
90 * is freed, it's too late.
93 drm_irq_uninstall(dev);
95 if (dev_priv->ring.virtual_start) {
96 drm_core_ioremapfree(&dev_priv->ring.map, dev);
97 dev_priv->ring.virtual_start = 0;
98 dev_priv->ring.map.handle = 0;
99 dev_priv->ring.map.size = 0;
100 dev_priv->ring.Size = 0;
103 if (dev_priv->status_page_dmah) {
104 drm_pci_free(dev, dev_priv->status_page_dmah);
105 dev_priv->status_page_dmah = NULL;
106 /* Need to rewrite hardware status page */
107 I915_WRITE(0x02080, 0x1ffff000);
110 if (dev_priv->status_gfx_addr) {
111 dev_priv->status_gfx_addr = 0;
112 drm_core_ioremapfree(&dev_priv->hws_map, dev);
113 I915_WRITE(0x02080, 0x1ffff000);
121 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
122 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
123 #define DRI2_SAREA_BLOCK_NEXT(p) \
124 ((void *) ((unsigned char *) (p) + \
125 DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
127 #define DRI2_SAREA_BLOCK_END 0x0000
128 #define DRI2_SAREA_BLOCK_LOCK 0x0001
129 #define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002
132 setup_dri2_sarea(struct drm_device * dev,
133 struct drm_file *file_priv,
134 drm_i915_init_t * init)
136 struct drm_i915_private *dev_priv = dev->dev_private;
138 unsigned int *p, *end, *next;
140 mutex_lock(&dev->struct_mutex);
142 drm_lookup_buffer_object(file_priv,
143 init->sarea_handle, 1);
144 mutex_unlock(&dev->struct_mutex);
146 if (!dev_priv->sarea_bo) {
147 DRM_ERROR("did not find sarea bo\n");
151 ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
152 dev_priv->sarea_bo->num_pages,
153 &dev_priv->sarea_kmap);
155 DRM_ERROR("could not map sarea bo\n");
159 p = dev_priv->sarea_kmap.virtual;
160 end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
161 while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
162 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
163 case DRI2_SAREA_BLOCK_LOCK:
164 dev->primary->master->lock.hw_lock = (void *) (p + 1);
165 dev->sigdata.lock = dev->primary->master->lock.hw_lock;
168 next = DRI2_SAREA_BLOCK_NEXT(p);
169 if (next <= p || end < next) {
170 DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
181 static int i915_initialize(struct drm_device * dev,
182 struct drm_file *file_priv,
183 drm_i915_init_t * init)
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
188 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
189 if (init->mmio_offset != 0)
190 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
191 if (!dev_priv->mmio_map) {
192 i915_dma_cleanup(dev);
193 DRM_ERROR("can not find mmio map!\n");
199 #ifdef I915_HAVE_BUFFER
200 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
203 if (!dev_priv->ring.Size) {
204 dev_priv->ring.Start = init->ring_start;
205 dev_priv->ring.End = init->ring_end;
206 dev_priv->ring.Size = init->ring_size;
207 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
209 dev_priv->ring.map.offset = init->ring_start;
210 dev_priv->ring.map.size = init->ring_size;
211 dev_priv->ring.map.type = 0;
212 dev_priv->ring.map.flags = 0;
213 dev_priv->ring.map.mtrr = 0;
215 drm_core_ioremap(&dev_priv->ring.map, dev);
217 if (dev_priv->ring.map.handle == NULL) {
218 i915_dma_cleanup(dev);
219 DRM_ERROR("can not ioremap virtual address for"
223 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
227 dev_priv->cpp = init->cpp;
228 master_priv->sarea_priv->pf_current_page = 0;
230 /* We are using separate values as placeholders for mechanisms for
231 * private backbuffer/depthbuffer usage.
233 dev_priv->use_mi_batchbuffer_start = 0;
234 if (IS_I965G(dev)) /* 965 doesn't support older method */
235 dev_priv->use_mi_batchbuffer_start = 1;
237 /* Allow hardware batchbuffers unless told otherwise.
239 dev_priv->allow_batchbuffer = 1;
241 /* Enable vblank on pipe A for older X servers
243 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
245 /* Program Hardware Status Page */
246 if (!I915_NEED_GFX_HWS(dev)) {
247 dev_priv->status_page_dmah =
248 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
250 if (!dev_priv->status_page_dmah) {
251 i915_dma_cleanup(dev);
252 DRM_ERROR("Can not allocate hardware status page\n");
255 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
256 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
258 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
260 I915_WRITE(0x02080, dev_priv->dma_status_page);
262 DRM_DEBUG("Enabled hardware status page\n");
263 #ifdef I915_HAVE_BUFFER
264 mutex_init(&dev_priv->cmdbuf_mutex);
267 if (init->func == I915_INIT_DMA2) {
268 int ret = setup_dri2_sarea(dev, file_priv, init);
270 i915_dma_cleanup(dev);
271 DRM_ERROR("could not set up dri2 sarea\n");
279 static int i915_dma_resume(struct drm_device * dev)
281 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
285 if (drm_core_check_feature(dev, DRIVER_MODESET))
288 if (!dev_priv->mmio_map) {
289 DRM_ERROR("can not find mmio map!\n");
293 if (dev_priv->ring.map.handle == NULL) {
294 DRM_ERROR("can not ioremap virtual address for"
299 /* Program Hardware Status Page */
300 if (!dev_priv->hw_status_page) {
301 DRM_ERROR("Can not find hardware status page\n");
304 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
306 if (dev_priv->status_gfx_addr != 0)
307 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
309 I915_WRITE(0x02080, dev_priv->dma_status_page);
310 DRM_DEBUG("Enabled hardware status page\n");
315 static int i915_dma_init(struct drm_device *dev, void *data,
316 struct drm_file *file_priv)
318 struct drm_i915_init *init = data;
321 switch (init->func) {
324 retcode = i915_initialize(dev, file_priv, init);
326 case I915_CLEANUP_DMA:
327 retcode = i915_dma_cleanup(dev);
329 case I915_RESUME_DMA:
330 retcode = i915_dma_resume(dev);
340 /* Implement basically the same security restrictions as hardware does
341 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
343 * Most of the calculations below involve calculating the size of a
344 * particular instruction. It's important to get the size right as
345 * that tells us where the next instruction to check is. Any illegal
346 * instruction detected will be given a size of zero, which is a
347 * signal to abort the rest of the buffer.
349 static int do_validate_cmd(int cmd)
351 switch (((cmd >> 29) & 0x7)) {
353 switch ((cmd >> 23) & 0x3f) {
355 return 1; /* MI_NOOP */
357 return 1; /* MI_FLUSH */
359 return 0; /* disallow everything else */
363 return 0; /* reserved */
365 return (cmd & 0xff) + 2; /* 2d commands */
367 if (((cmd >> 24) & 0x1f) <= 0x18)
370 switch ((cmd >> 24) & 0x1f) {
374 switch ((cmd >> 16) & 0xff) {
376 return (cmd & 0x1f) + 2;
378 return (cmd & 0xf) + 2;
380 return (cmd & 0xffff) + 2;
384 return (cmd & 0xffff) + 1;
388 if ((cmd & (1 << 23)) == 0) /* inline vertices */
389 return (cmd & 0x1ffff) + 2;
390 else if (cmd & (1 << 17)) /* indirect random */
391 if ((cmd & 0xffff) == 0)
392 return 0; /* unknown length, too hard */
394 return (((cmd & 0xffff) + 1) / 2) + 1;
396 return 2; /* indirect sequential */
407 static int validate_cmd(int cmd)
409 int ret = do_validate_cmd(cmd);
411 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
416 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
419 struct drm_i915_private *dev_priv = dev->dev_private;
423 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
426 BEGIN_LP_RING((dwords+1)&~1);
428 for (i = 0; i < dwords;) {
431 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
434 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
440 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
456 static int i915_emit_box(struct drm_device * dev,
457 struct drm_clip_rect __user * boxes,
458 int i, int DR1, int DR4)
460 struct drm_i915_private *dev_priv = dev->dev_private;
461 struct drm_clip_rect box;
464 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
468 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
469 DRM_ERROR("Bad box %d,%d..%d,%d\n",
470 box.x1, box.y1, box.x2, box.y2);
476 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
477 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
478 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
483 OUT_RING(GFX_OP_DRAWRECT_INFO);
485 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
486 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
495 /* XXX: Emitting the counter should really be moved to part of the IRQ
496 * emit. For now, do it in both places:
499 void i915_emit_breadcrumb(struct drm_device *dev)
501 struct drm_i915_private *dev_priv = dev->dev_private;
502 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
505 if (++dev_priv->counter > BREADCRUMB_MASK) {
506 dev_priv->counter = 1;
507 DRM_DEBUG("Breadcrumb counter wrapped around\n");
510 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
513 OUT_RING(CMD_STORE_DWORD_IDX);
515 OUT_RING(dev_priv->counter);
521 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
523 struct drm_i915_private *dev_priv = dev->dev_private;
524 uint32_t flush_cmd = CMD_MI_FLUSH;
529 i915_kernel_lost_context(dev);
542 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
543 struct drm_i915_cmdbuffer * cmd)
545 #ifdef I915_HAVE_FENCE
546 struct drm_i915_private *dev_priv = dev->dev_private;
548 int nbox = cmd->num_cliprects;
549 int i = 0, count, ret;
552 DRM_ERROR("alignment\n");
556 i915_kernel_lost_context(dev);
558 count = nbox ? nbox : 1;
560 for (i = 0; i < count; i++) {
562 ret = i915_emit_box(dev, cmd->cliprects, i,
568 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
573 i915_emit_breadcrumb(dev);
574 #ifdef I915_HAVE_FENCE
575 if (unlikely((dev_priv->counter & 0xFF) == 0))
576 drm_fence_flush_old(dev, 0, dev_priv->counter);
581 int i915_dispatch_batchbuffer(struct drm_device * dev,
582 drm_i915_batchbuffer_t * batch)
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 struct drm_clip_rect __user *boxes = batch->cliprects;
586 int nbox = batch->num_cliprects;
590 if ((batch->start | batch->used) & 0x7) {
591 DRM_ERROR("alignment\n");
595 i915_kernel_lost_context(dev);
597 count = nbox ? nbox : 1;
599 for (i = 0; i < count; i++) {
601 int ret = i915_emit_box(dev, boxes, i,
602 batch->DR1, batch->DR4);
607 if (dev_priv->use_mi_batchbuffer_start) {
610 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
611 OUT_RING(batch->start);
613 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
614 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
620 OUT_RING(MI_BATCH_BUFFER);
621 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
622 OUT_RING(batch->start + batch->used - 4);
628 i915_emit_breadcrumb(dev);
629 #ifdef I915_HAVE_FENCE
630 if (unlikely((dev_priv->counter & 0xFF) == 0))
631 drm_fence_flush_old(dev, 0, dev_priv->counter);
636 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
640 u32 num_pages, current_page, next_page, dspbase;
641 int shift = 2 * plane, x, y;
644 /* Calculate display base offset */
645 num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
646 current_page = (master_priv->sarea_priv->pf_current_page >> shift) & 0x3;
647 next_page = (current_page + 1) % num_pages;
652 dspbase = master_priv->sarea_priv->front_offset;
655 dspbase = master_priv->sarea_priv->back_offset;
658 dspbase = master_priv->sarea_priv->third_offset;
663 x = master_priv->sarea_priv->planeA_x;
664 y = master_priv->sarea_priv->planeA_y;
666 x = master_priv->sarea_priv->planeB_x;
667 y = master_priv->sarea_priv->planeB_y;
670 dspbase += (y * master_priv->sarea_priv->pitch + x) * dev_priv->cpp;
672 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
677 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
678 MI_WAIT_FOR_PLANE_A_FLIP)));
679 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
680 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
681 OUT_RING(master_priv->sarea_priv->pitch * dev_priv->cpp);
685 master_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
686 master_priv->sarea_priv->pf_current_page |= next_page << shift;
689 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
695 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
696 planes, master_priv->sarea_priv->pf_current_page);
698 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
700 for (i = 0; i < 2; i++)
701 if (planes & (1 << i))
702 i915_do_dispatch_flip(dev, i, sync);
704 i915_emit_breadcrumb(dev);
705 #ifdef I915_HAVE_FENCE
706 if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
707 drm_fence_flush_old(dev, 0, dev_priv->counter);
711 int i915_quiescent(struct drm_device *dev)
713 struct drm_i915_private *dev_priv = dev->dev_private;
715 i915_kernel_lost_context(dev);
716 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
719 static int i915_flush_ioctl(struct drm_device *dev, void *data,
720 struct drm_file *file_priv)
723 LOCK_TEST_WITH_RETURN(dev, file_priv);
725 return i915_quiescent(dev);
728 static int i915_batchbuffer(struct drm_device *dev, void *data,
729 struct drm_file *file_priv)
731 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
732 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
733 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
734 master_priv->sarea_priv;
735 drm_i915_batchbuffer_t *batch = data;
738 if (!dev_priv->allow_batchbuffer) {
739 DRM_ERROR("Batchbuffer ioctl disabled\n");
743 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
744 batch->start, batch->used, batch->num_cliprects);
746 LOCK_TEST_WITH_RETURN(dev, file_priv);
748 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
749 batch->num_cliprects *
750 sizeof(struct drm_clip_rect)))
753 ret = i915_dispatch_batchbuffer(dev, batch);
755 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
759 static int i915_cmdbuffer(struct drm_device *dev, void *data,
760 struct drm_file *file_priv)
762 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
763 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
764 struct drm_i915_sarea *sarea_priv = (struct drm_i915_sarea *)
765 master_priv->sarea_priv;
766 struct drm_i915_cmdbuffer *cmdbuf = data;
769 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
770 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
772 LOCK_TEST_WITH_RETURN(dev, file_priv);
774 if (cmdbuf->num_cliprects &&
775 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
776 cmdbuf->num_cliprects *
777 sizeof(struct drm_clip_rect))) {
778 DRM_ERROR("Fault accessing cliprects\n");
782 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
784 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
788 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
793 #define DRM_DEBUG_RELOCATION (drm_debug != 0)
795 #define DRM_DEBUG_RELOCATION 0
798 int i915_do_cleanup_pageflip(struct drm_device * dev)
800 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
801 int i, planes, num_pages;
804 num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
805 for (i = 0, planes = 0; i < 2; i++) {
806 if (master_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
807 master_priv->sarea_priv->pf_current_page =
808 (master_priv->sarea_priv->pf_current_page &
809 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
816 i915_dispatch_flip(dev, planes, 0);
821 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
823 struct drm_i915_flip *param = data;
827 LOCK_TEST_WITH_RETURN(dev, file_priv);
829 /* This is really planes */
830 if (param->pipes & ~0x3) {
831 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
836 i915_dispatch_flip(dev, param->pipes, 0);
842 static int i915_getparam(struct drm_device *dev, void *data,
843 struct drm_file *file_priv)
845 struct drm_i915_private *dev_priv = dev->dev_private;
846 struct drm_i915_getparam *param = data;
850 DRM_ERROR("called with no initialization\n");
854 switch (param->param) {
855 case I915_PARAM_IRQ_ACTIVE:
856 value = dev->irq ? 1 : 0;
858 case I915_PARAM_ALLOW_BATCHBUFFER:
859 value = dev_priv->allow_batchbuffer ? 1 : 0;
861 case I915_PARAM_LAST_DISPATCH:
862 value = READ_BREADCRUMB(dev_priv);
864 case I915_PARAM_CHIPSET_ID:
865 value = dev->pci_device;
868 DRM_ERROR("Unknown parameter %d\n", param->param);
872 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
873 DRM_ERROR("DRM_COPY_TO_USER failed\n");
880 static int i915_setparam(struct drm_device *dev, void *data,
881 struct drm_file *file_priv)
883 struct drm_i915_private *dev_priv = dev->dev_private;
884 drm_i915_setparam_t *param = data;
887 DRM_ERROR("called with no initialization\n");
891 switch (param->param) {
892 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
894 dev_priv->use_mi_batchbuffer_start = param->value;
896 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
897 dev_priv->tex_lru_log_granularity = param->value;
899 case I915_SETPARAM_ALLOW_BATCHBUFFER:
900 dev_priv->allow_batchbuffer = param->value;
903 DRM_ERROR("unknown parameter %d\n", param->param);
910 drm_i915_mmio_entry_t mmio_table[] = {
911 [MMIO_REGS_PS_DEPTH_COUNT] = {
912 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
916 [MMIO_REGS_DOVSTA] = {
921 [MMIO_REGS_GAMMA] = {
922 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
926 [MMIO_REGS_FENCE] = {
927 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
931 [MMIO_REGS_FENCE_NEW] = {
932 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
938 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
940 static int i915_mmio(struct drm_device *dev, void *data,
941 struct drm_file *file_priv)
944 struct drm_i915_private *dev_priv = dev->dev_private;
945 drm_i915_mmio_entry_t *e;
946 drm_i915_mmio_t *mmio = data;
951 DRM_ERROR("called with no initialization\n");
955 if (mmio->reg >= mmio_table_size)
958 e = &mmio_table[mmio->reg];
959 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
961 switch (mmio->read_write) {
963 if (!(e->flag & I915_MMIO_MAY_READ))
965 for (i = 0; i < e->size / 4; i++)
966 buf[i] = I915_READ(e->offset + i * 4);
967 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
968 DRM_ERROR("DRM_COPY_TO_USER failed\n");
973 case I915_MMIO_WRITE:
974 if (!(e->flag & I915_MMIO_MAY_WRITE))
976 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
977 DRM_ERROR("DRM_COPY_TO_USER failed\n");
980 for (i = 0; i < e->size / 4; i++)
981 I915_WRITE(e->offset + i * 4, buf[i]);
987 static int i915_set_status_page(struct drm_device *dev, void *data,
988 struct drm_file *file_priv)
990 struct drm_i915_private *dev_priv = dev->dev_private;
991 drm_i915_hws_addr_t *hws = data;
993 if (!I915_NEED_GFX_HWS(dev))
997 DRM_ERROR("called with no initialization\n");
1000 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1002 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1004 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1005 dev_priv->hws_map.size = 4*1024;
1006 dev_priv->hws_map.type = 0;
1007 dev_priv->hws_map.flags = 0;
1008 dev_priv->hws_map.mtrr = 0;
1010 drm_core_ioremap(&dev_priv->hws_map, dev);
1011 if (dev_priv->hws_map.handle == NULL) {
1012 i915_dma_cleanup(dev);
1013 dev_priv->status_gfx_addr = 0;
1014 DRM_ERROR("can not ioremap virtual address for"
1015 " G33 hw status page\n");
1018 dev_priv->hw_status_page = dev_priv->hws_map.handle;
1020 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1021 I915_WRITE(I915REG_HWS_PGA, dev_priv->status_gfx_addr);
1022 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1023 dev_priv->status_gfx_addr);
1024 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1028 struct drm_ioctl_desc i915_ioctls[] = {
1029 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1030 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1031 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1032 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1033 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1034 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1035 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1036 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1037 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1038 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1039 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1040 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1041 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1042 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1043 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1044 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1045 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1046 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1047 #ifdef I915_HAVE_BUFFER
1048 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1052 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1055 * Determine if the device really is AGP or not.
1057 * All Intel graphics chipsets are treated as AGP, even if they are really
1060 * \param dev The device to be tested.
1063 * A value of 1 is always retured to indictate every i9x5 is AGP.
1065 int i915_driver_device_is_agp(struct drm_device * dev)