shared-core/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 /* Really want an OS-independent resettable timer.  Would like to have
  35  * this loop run for (eg) 3 sec, but have the timer reset every time
  36  * the head pointer changes, so that EBUSY only happens if the ring
  37  * actually stalls for (eg) 3 seconds.
  38  */
  39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
  40 {
  41         struct drm_i915_private *dev_priv = dev->dev_private;
  42         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
  43         u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  44         int i;
  45
  46         for (i = 0; i < 10000; i++) {
  47                 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  48                 ring->space = ring->head - (ring->tail + 8);
  49                 if (ring->space < 0)
  50                         ring->space += ring->Size;
  51                 if (ring->space >= n)
  52                         return 0;
  53
  54                 if (ring->head != last_head)
  55                         i = 0;
  56
  57                 last_head = ring->head;
  58                 DRM_UDELAY(1);
  59         }
  60
  61         return -EBUSY;
  62 }
  63
  64 void i915_kernel_lost_context(struct drm_device * dev)
  65 {
  66         struct drm_i915_private *dev_priv = dev->dev_private;
  67         struct drm_i915_ring_buffer *ring = &(dev_priv->ring);
  68
  69         /* we should never lose context on the ring with modesetting
  70          * as we don't expose it to userspace */
  71         if (drm_core_check_feature(dev, DRIVER_MODESET))
  72                 return;
  73
  74         ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
  75         ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
  76         ring->space = ring->head - (ring->tail + 8);
  77         if (ring->space < 0)
  78                 ring->space += ring->Size;
  79 }
  80
  81 int i915_dma_cleanup(struct drm_device * dev)
  82 {
  83         struct drm_i915_private *dev_priv = dev->dev_private;
  84
  85         if (drm_core_check_feature(dev, DRIVER_MODESET))
  86                 return 0;
  87
  88         /* Make sure interrupts are disabled here because the uninstall ioctl
  89          * may not have been called from userspace and after dev_private
  90          * is freed, it's too late.
  91          */
  92         if (dev->irq)
  93                 drm_irq_uninstall(dev);
  94
  95         if (dev_priv->ring.virtual_start) {
  96                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
  97                 dev_priv->ring.virtual_start = 0;
  98                 dev_priv->ring.map.handle = 0;
  99                 dev_priv->ring.map.size = 0;
 100                 dev_priv->ring.Size = 0;
 101         }
 102
 103         if (dev_priv->status_page_dmah) {
 104                 drm_pci_free(dev, dev_priv->status_page_dmah);
 105                 dev_priv->status_page_dmah = NULL;
 106                 /* Need to rewrite hardware status page */
 107                 I915_WRITE(0x02080, 0x1ffff000);
 108         }
 109
 110         if (dev_priv->status_gfx_addr) {
 111                 dev_priv->status_gfx_addr = 0;
 112                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 113                 I915_WRITE(0x02080, 0x1ffff000);
 114         }
 115
 116
 117         return 0;
 118 }
 119
 120
 121 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
 122 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
 123 #define DRI2_SAREA_BLOCK_NEXT(p)                                \
 124         ((void *) ((unsigned char *) (p) +                      \
 125                    DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
 126
 127 #define DRI2_SAREA_BLOCK_END            0x0000
 128 #define DRI2_SAREA_BLOCK_LOCK           0x0001
 129 #define DRI2_SAREA_BLOCK_EVENT_BUFFER   0x0002
 130
 131 static int
 132 setup_dri2_sarea(struct drm_device * dev,
 133                  struct drm_file *file_priv,
 134                  drm_i915_init_t * init)
 135 {
 136         struct drm_i915_private *dev_priv = dev->dev_private;
 137         int ret;
 138         unsigned int *p, *end, *next;
 139
 140         mutex_lock(&dev->struct_mutex);
 141         dev_priv->sarea_bo =
 142                 drm_lookup_buffer_object(file_priv,
 143                                          init->sarea_handle, 1);
 144         mutex_unlock(&dev->struct_mutex);
 145
 146         if (!dev_priv->sarea_bo) {
 147                 DRM_ERROR("did not find sarea bo\n");
 148                 return -EINVAL;
 149         }
 150
 151         ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
 152                           dev_priv->sarea_bo->num_pages,
 153                           &dev_priv->sarea_kmap);
 154         if (ret) {
 155                 DRM_ERROR("could not map sarea bo\n");
 156                 return ret;
 157         }
 158
 159         p = dev_priv->sarea_kmap.virtual;
 160         end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
 161         while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
 162                 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
 163                 case DRI2_SAREA_BLOCK_LOCK:
 164                         dev->primary->master->lock.hw_lock = (void *) (p + 1);
 165                         dev->sigdata.lock = dev->primary->master->lock.hw_lock;
 166                         break;
 167                 }
 168                 next = DRI2_SAREA_BLOCK_NEXT(p);
 169                 if (next <= p || end < next) {
 170                         DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
 171                                   next, p, end);
 172                         return -EINVAL;
 173                 }
 174                 p = next;
 175         }
 176
 177         return 0;
 178 }
 179
 180
 181 static int i915_initialize(struct drm_device * dev,
 182                            struct drm_file *file_priv,
 183                            drm_i915_init_t * init)
 184 {
 185         struct drm_i915_private *dev_priv = dev->dev_private;
 186         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 187
 188         if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
 189                 if (init->mmio_offset != 0)
 190                         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
 191                 if (!dev_priv->mmio_map) {
 192                         i915_dma_cleanup(dev);
 193                         DRM_ERROR("can not find mmio map!\n");
 194                         return -EINVAL;
 195                 }
 196         }
 197
 198
 199 #ifdef I915_HAVE_BUFFER
 200         dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 201 #endif
 202
 203         if (!dev_priv->ring.Size) {
 204                 dev_priv->ring.Start = init->ring_start;
 205                 dev_priv->ring.End = init->ring_end;
 206                 dev_priv->ring.Size = init->ring_size;
 207                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 208
 209                 dev_priv->ring.map.offset = init->ring_start;
 210                 dev_priv->ring.map.size = init->ring_size;
 211                 dev_priv->ring.map.type = 0;
 212                 dev_priv->ring.map.flags = 0;
 213                 dev_priv->ring.map.mtrr = 0;
 214
 215                 drm_core_ioremap(&dev_priv->ring.map, dev);
 216
 217                 if (dev_priv->ring.map.handle == NULL) {
 218                         i915_dma_cleanup(dev);
 219                         DRM_ERROR("can not ioremap virtual address for"
 220                                   " ring buffer\n");
 221                         return -ENOMEM;
 222                 }
 223                 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
 224         }
 225
 226
 227         dev_priv->cpp = init->cpp;
 228         master_priv->sarea_priv->pf_current_page = 0;
 229
 230         /* We are using separate values as placeholders for mechanisms for
 231          * private backbuffer/depthbuffer usage.
 232          */
 233         dev_priv->use_mi_batchbuffer_start = 0;
 234         if (IS_I965G(dev)) /* 965 doesn't support older method */
 235                 dev_priv->use_mi_batchbuffer_start = 1;
 236
 237         /* Allow hardware batchbuffers unless told otherwise.
 238          */
 239         dev_priv->allow_batchbuffer = 1;
 240
 241         /* Enable vblank on pipe A for older X servers
 242          */
 243         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
 244
 245         /* Program Hardware Status Page */
 246         if (!I915_NEED_GFX_HWS(dev)) {
 247                 dev_priv->status_page_dmah =
 248                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 249
 250                 if (!dev_priv->status_page_dmah) {
 251                         i915_dma_cleanup(dev);
 252                         DRM_ERROR("Can not allocate hardware status page\n");
 253                         return -ENOMEM;
 254                 }
 255                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 256                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 257
 258                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 259
 260                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 261         }
 262         DRM_DEBUG("Enabled hardware status page\n");
 263 #ifdef I915_HAVE_BUFFER
 264         mutex_init(&dev_priv->cmdbuf_mutex);
 265 #endif
 266
 267         if (init->func == I915_INIT_DMA2) {
 268                 int ret = setup_dri2_sarea(dev, file_priv, init);
 269                 if (ret) {
 270                         i915_dma_cleanup(dev);
 271                         DRM_ERROR("could not set up dri2 sarea\n");
 272                         return ret;
 273                 }
 274         }
 275
 276         return 0;
 277 }
 278
 279 static int i915_dma_resume(struct drm_device * dev)
 280 {
 281         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 282
 283         DRM_DEBUG("\n");
 284
 285         if (drm_core_check_feature(dev, DRIVER_MODESET))
 286                 return 0;
 287
 288         if (!dev_priv->mmio_map) {
 289                 DRM_ERROR("can not find mmio map!\n");
 290                 return -EINVAL;
 291         }
 292
 293         if (dev_priv->ring.map.handle == NULL) {
 294                 DRM_ERROR("can not ioremap virtual address for"
 295                           " ring buffer\n");
 296                 return -ENOMEM;
 297         }
 298
 299         /* Program Hardware Status Page */
 300         if (!dev_priv->hw_status_page) {
 301                 DRM_ERROR("Can not find hardware status page\n");
 302                 return -EINVAL;
 303         }
 304         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
 305
 306         if (dev_priv->status_gfx_addr != 0)
 307                 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
 308         else
 309                 I915_WRITE(0x02080, dev_priv->dma_status_page);
 310         DRM_DEBUG("Enabled hardware status page\n");
 311
 312         return 0;
 313 }
 314
 315 static int i915_dma_init(struct drm_device *dev, void *data,
 316                          struct drm_file *file_priv)
 317 {
 318         struct drm_i915_init *init = data;
 319         int retcode = 0;
 320
 321         switch (init->func) {
 322         case I915_INIT_DMA:
 323         case I915_INIT_DMA2:
 324                 retcode = i915_initialize(dev, file_priv, init);
 325                 break;
 326         case I915_CLEANUP_DMA:
 327                 retcode = i915_dma_cleanup(dev);
 328                 break;
 329         case I915_RESUME_DMA:
 330                 retcode = i915_dma_resume(dev);
 331                 break;
 332         default:
 333                 retcode = -EINVAL;
 334                 break;
 335         }
 336
 337         return retcode;
 338 }
 339
 340 /* Implement basically the same security restrictions as hardware does
 341  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 342  *
 343  * Most of the calculations below involve calculating the size of a
 344  * particular instruction.  It's important to get the size right as
 345  * that tells us where the next instruction to check is.  Any illegal
 346  * instruction detected will be given a size of zero, which is a
 347  * signal to abort the rest of the buffer.
 348  */
 349 static int do_validate_cmd(int cmd)
 350 {
 351         switch (((cmd >> 29) & 0x7)) {
 352         case 0x0:
 353                 switch ((cmd >> 23) & 0x3f) {
 354                 case 0x0:
 355                         return 1;       /* MI_NOOP */
 356                 case 0x4:
 357                         return 1;       /* MI_FLUSH */
 358                 default:
 359                         return 0;       /* disallow everything else */
 360                 }
 361                 break;
 362         case 0x1:
 363                 return 0;       /* reserved */
 364         case 0x2:
 365                 return (cmd & 0xff) + 2;        /* 2d commands */
 366         case 0x3:
 367                 if (((cmd >> 24) & 0x1f) <= 0x18)
 368                         return 1;
 369
 370                 switch ((cmd >> 24) & 0x1f) {
 371                 case 0x1c:
 372                         return 1;
 373                 case 0x1d:
 374                         switch ((cmd >> 16) & 0xff) {
 375                         case 0x3:
 376                                 return (cmd & 0x1f) + 2;
 377                         case 0x4:
 378                                 return (cmd & 0xf) + 2;
 379                         default:
 380                                 return (cmd & 0xffff) + 2;
 381                         }
 382                 case 0x1e:
 383                         if (cmd & (1 << 23))
 384                                 return (cmd & 0xffff) + 1;
 385                         else
 386                                 return 1;
 387                 case 0x1f:
 388                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 389                                 return (cmd & 0x1ffff) + 2;
 390                         else if (cmd & (1 << 17))       /* indirect random */
 391                                 if ((cmd & 0xffff) == 0)
 392                                         return 0;       /* unknown length, too hard */
 393                                 else
 394                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 395                         else
 396                                 return 2;       /* indirect sequential */
 397                 default:
 398                         return 0;
 399                 }
 400         default:
 401                 return 0;
 402         }
 403
 404         return 0;
 405 }
 406
 407 static int validate_cmd(int cmd)
 408 {
 409         int ret = do_validate_cmd(cmd);
 410
 411 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 412
 413         return ret;
 414 }
 415
 416 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
 417                           int dwords)
 418 {
 419         struct drm_i915_private *dev_priv = dev->dev_private;
 420         int i;
 421         RING_LOCALS;
 422
 423         if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
 424                 return -EINVAL;
 425
 426         BEGIN_LP_RING((dwords+1)&~1);
 427
 428         for (i = 0; i < dwords;) {
 429                 int cmd, sz;
 430
 431                 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
 432                         return -EINVAL;
 433
 434                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 435                         return -EINVAL;
 436
 437                 OUT_RING(cmd);
 438
 439                 while (++i, --sz) {
 440                         if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
 441                                                          sizeof(cmd))) {
 442                                 return -EINVAL;
 443                         }
 444                         OUT_RING(cmd);
 445                 }
 446         }
 447
 448         if (dwords & 1)
 449                 OUT_RING(0);
 450
 451         ADVANCE_LP_RING();
 452
 453         return 0;
 454 }
 455
 456 static int i915_emit_box(struct drm_device * dev,
 457                          struct drm_clip_rect __user * boxes,
 458                          int i, int DR1, int DR4)
 459 {
 460         struct drm_i915_private *dev_priv = dev->dev_private;
 461         struct drm_clip_rect box;
 462         RING_LOCALS;
 463
 464         if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
 465                 return -EFAULT;
 466         }
 467
 468         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 469                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 470                           box.x1, box.y1, box.x2, box.y2);
 471                 return -EINVAL;
 472         }
 473
 474         if (IS_I965G(dev)) {
 475                 BEGIN_LP_RING(4);
 476                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 477                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 478                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 479                 OUT_RING(DR4);
 480                 ADVANCE_LP_RING();
 481         } else {
 482                 BEGIN_LP_RING(6);
 483                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 484                 OUT_RING(DR1);
 485                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 486                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 487                 OUT_RING(DR4);
 488                 OUT_RING(0);
 489                 ADVANCE_LP_RING();
 490         }
 491
 492         return 0;
 493 }
 494
 495 /* XXX: Emitting the counter should really be moved to part of the IRQ
 496  * emit. For now, do it in both places:
 497  */
 498
 499 void i915_emit_breadcrumb(struct drm_device *dev)
 500 {
 501         struct drm_i915_private *dev_priv = dev->dev_private;
 502         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 503         RING_LOCALS;
 504
 505         if (++dev_priv->counter > BREADCRUMB_MASK) {
 506                  dev_priv->counter = 1;
 507                  DRM_DEBUG("Breadcrumb counter wrapped around\n");
 508         }
 509
 510         master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 511
 512         BEGIN_LP_RING(4);
 513         OUT_RING(CMD_STORE_DWORD_IDX);
 514         OUT_RING(20);
 515         OUT_RING(dev_priv->counter);
 516         OUT_RING(0);
 517         ADVANCE_LP_RING();
 518 }
 519
 520
 521 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
 522 {
 523         struct drm_i915_private *dev_priv = dev->dev_private;
 524         uint32_t flush_cmd = CMD_MI_FLUSH;
 525         RING_LOCALS;
 526
 527         flush_cmd |= flush;
 528
 529         i915_kernel_lost_context(dev);
 530
 531         BEGIN_LP_RING(4);
 532         OUT_RING(flush_cmd);
 533         OUT_RING(0);
 534         OUT_RING(0);
 535         OUT_RING(0);
 536         ADVANCE_LP_RING();
 537
 538         return 0;
 539 }
 540
 541
 542 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 543                                    struct drm_i915_cmdbuffer * cmd)
 544 {
 545 #ifdef I915_HAVE_FENCE
 546         struct drm_i915_private *dev_priv = dev->dev_private;
 547 #endif
 548         int nbox = cmd->num_cliprects;
 549         int i = 0, count, ret;
 550
 551         if (cmd->sz & 0x3) {
 552                 DRM_ERROR("alignment\n");
 553                 return -EINVAL;
 554         }
 555
 556         i915_kernel_lost_context(dev);
 557
 558         count = nbox ? nbox : 1;
 559
 560         for (i = 0; i < count; i++) {
 561                 if (i < nbox) {
 562                         ret = i915_emit_box(dev, cmd->cliprects, i,
 563                                             cmd->DR1, cmd->DR4);
 564                         if (ret)
 565                                 return ret;
 566                 }
 567
 568                 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
 569                 if (ret)
 570                         return ret;
 571         }
 572
 573         i915_emit_breadcrumb(dev);
 574 #ifdef I915_HAVE_FENCE
 575         if (unlikely((dev_priv->counter & 0xFF) == 0))
 576                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 577 #endif
 578         return 0;
 579 }
 580
 581 int i915_dispatch_batchbuffer(struct drm_device * dev,
 582                               drm_i915_batchbuffer_t * batch)
 583 {
 584         struct drm_i915_private *dev_priv = dev->dev_private;
 585         struct drm_clip_rect __user *boxes = batch->cliprects;
 586         int nbox = batch->num_cliprects;
 587         int i = 0, count;
 588         RING_LOCALS;
 589
 590         if ((batch->start | batch->used) & 0x7) {
 591                 DRM_ERROR("alignment\n");
 592                 return -EINVAL;
 593         }
 594
 595         i915_kernel_lost_context(dev);
 596
 597         count = nbox ? nbox : 1;
 598
 599         for (i = 0; i < count; i++) {
 600                 if (i < nbox) {
 601                         int ret = i915_emit_box(dev, boxes, i,
 602                                                 batch->DR1, batch->DR4);
 603                         if (ret)
 604                                 return ret;
 605                 }
 606
 607                 if (dev_priv->use_mi_batchbuffer_start) {
 608                         BEGIN_LP_RING(2);
 609                         if (IS_I965G(dev)) {
 610                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 611                                 OUT_RING(batch->start);
 612                         } else {
 613                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 614                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 615                         }
 616                         ADVANCE_LP_RING();
 617
 618                 } else {
 619                         BEGIN_LP_RING(4);
 620                         OUT_RING(MI_BATCH_BUFFER);
 621                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 622                         OUT_RING(batch->start + batch->used - 4);
 623                         OUT_RING(0);
 624                         ADVANCE_LP_RING();
 625                 }
 626         }
 627
 628         i915_emit_breadcrumb(dev);
 629 #ifdef I915_HAVE_FENCE
 630         if (unlikely((dev_priv->counter & 0xFF) == 0))
 631                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 632 #endif
 633         return 0;
 634 }
 635
 636 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
 637 {
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 640         u32 num_pages, current_page, next_page, dspbase;
 641         int shift = 2 * plane, x, y;
 642         RING_LOCALS;
 643
 644         /* Calculate display base offset */
 645         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 646         current_page = (master_priv->sarea_priv->pf_current_page >> shift) & 0x3;
 647         next_page = (current_page + 1) % num_pages;
 648
 649         switch (next_page) {
 650         default:
 651         case 0:
 652                 dspbase = master_priv->sarea_priv->front_offset;
 653                 break;
 654         case 1:
 655                 dspbase = master_priv->sarea_priv->back_offset;
 656                 break;
 657         case 2:
 658                 dspbase = master_priv->sarea_priv->third_offset;
 659                 break;
 660         }
 661
 662         if (plane == 0) {
 663                 x = master_priv->sarea_priv->planeA_x;
 664                 y = master_priv->sarea_priv->planeA_y;
 665         } else {
 666                 x = master_priv->sarea_priv->planeB_x;
 667                 y = master_priv->sarea_priv->planeB_y;
 668         }
 669
 670         dspbase += (y * master_priv->sarea_priv->pitch + x) * dev_priv->cpp;
 671
 672         DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
 673                   dspbase);
 674
 675         BEGIN_LP_RING(4);
 676         OUT_RING(sync ? 0 :
 677                  (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
 678                                        MI_WAIT_FOR_PLANE_A_FLIP)));
 679         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
 680                  (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
 681         OUT_RING(master_priv->sarea_priv->pitch * dev_priv->cpp);
 682         OUT_RING(dspbase);
 683         ADVANCE_LP_RING();
 684
 685         master_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
 686         master_priv->sarea_priv->pf_current_page |= next_page << shift;
 687 }
 688
 689 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
 690 {
 691         struct drm_i915_private *dev_priv = dev->dev_private;
 692         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 693         int i;
 694
 695         DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
 696                   planes, master_priv->sarea_priv->pf_current_page);
 697
 698         i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
 699
 700         for (i = 0; i < 2; i++)
 701                 if (planes & (1 << i))
 702                         i915_do_dispatch_flip(dev, i, sync);
 703
 704         i915_emit_breadcrumb(dev);
 705 #ifdef I915_HAVE_FENCE
 706         if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
 707                 drm_fence_flush_old(dev, 0, dev_priv->counter);
 708 #endif
 709 }
 710
 711 int i915_quiescent(struct drm_device *dev)
 712 {
 713         struct drm_i915_private *dev_priv = dev->dev_private;
 714
 715         i915_kernel_lost_context(dev);
 716         return i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
 717 }
 718
 719 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 720                             struct drm_file *file_priv)
 721 {
 722
 723         LOCK_TEST_WITH_RETURN(dev, file_priv);
 724
 725         return i915_quiescent(dev);
 726 }
 727
 728 static int i915_batchbuffer(struct drm_device *dev, void *data,
 729                             struct drm_file *file_priv)
 730 {
 731         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 732         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 733         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 734             master_priv->sarea_priv;
 735         drm_i915_batchbuffer_t *batch = data;
 736         int ret;
 737
 738         if (!dev_priv->allow_batchbuffer) {
 739                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 740                 return -EINVAL;
 741         }
 742
 743         DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
 744                   batch->start, batch->used, batch->num_cliprects);
 745
 746         LOCK_TEST_WITH_RETURN(dev, file_priv);
 747
 748         if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
 749                                                         batch->num_cliprects *
 750                                                         sizeof(struct drm_clip_rect)))
 751                 return -EFAULT;
 752
 753         ret = i915_dispatch_batchbuffer(dev, batch);
 754
 755         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 756         return ret;
 757 }
 758
 759 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 760                           struct drm_file *file_priv)
 761 {
 762         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 763         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 764         struct drm_i915_sarea *sarea_priv = (struct drm_i915_sarea *)
 765                 master_priv->sarea_priv;
 766         struct drm_i915_cmdbuffer *cmdbuf = data;
 767         int ret;
 768
 769         DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 770                   cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 771
 772         LOCK_TEST_WITH_RETURN(dev, file_priv);
 773
 774         if (cmdbuf->num_cliprects &&
 775             DRM_VERIFYAREA_READ(cmdbuf->cliprects,
 776                                 cmdbuf->num_cliprects *
 777                                 sizeof(struct drm_clip_rect))) {
 778                 DRM_ERROR("Fault accessing cliprects\n");
 779                 return -EFAULT;
 780         }
 781
 782         ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
 783         if (ret) {
 784                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 785                 return ret;
 786         }
 787
 788         sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 789         return 0;
 790 }
 791
 792 #if DRM_DEBUG_CODE
 793 #define DRM_DEBUG_RELOCATION    (drm_debug != 0)
 794 #else
 795 #define DRM_DEBUG_RELOCATION    0
 796 #endif
 797
 798 int i915_do_cleanup_pageflip(struct drm_device * dev)
 799 {
 800         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 801         int i, planes, num_pages;
 802
 803         DRM_DEBUG("\n");
 804         num_pages = master_priv->sarea_priv->third_handle ? 3 : 2;
 805         for (i = 0, planes = 0; i < 2; i++) {
 806                 if (master_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
 807                         master_priv->sarea_priv->pf_current_page =
 808                                 (master_priv->sarea_priv->pf_current_page &
 809                                  ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
 810
 811                         planes |= 1 << i;
 812                 }
 813         }
 814
 815         if (planes)
 816                 i915_dispatch_flip(dev, planes, 0);
 817
 818         return 0;
 819 }
 820
 821 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
 822 {
 823         struct drm_i915_flip *param = data;
 824
 825         DRM_DEBUG("\n");
 826
 827         LOCK_TEST_WITH_RETURN(dev, file_priv);
 828
 829         /* This is really planes */
 830         if (param->pipes & ~0x3) {
 831                 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
 832                           param->pipes);
 833                 return -EINVAL;
 834         }
 835
 836         i915_dispatch_flip(dev, param->pipes, 0);
 837
 838         return 0;
 839 }
 840
 841
 842 static int i915_getparam(struct drm_device *dev, void *data,
 843                          struct drm_file *file_priv)
 844 {
 845         struct drm_i915_private *dev_priv = dev->dev_private;
 846         struct drm_i915_getparam *param = data;
 847         int value;
 848
 849         if (!dev_priv) {
 850                 DRM_ERROR("called with no initialization\n");
 851                 return -EINVAL;
 852         }
 853
 854         switch (param->param) {
 855         case I915_PARAM_IRQ_ACTIVE:
 856                 value = dev->irq ? 1 : 0;
 857                 break;
 858         case I915_PARAM_ALLOW_BATCHBUFFER:
 859                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 860                 break;
 861         case I915_PARAM_LAST_DISPATCH:
 862                 value = READ_BREADCRUMB(dev_priv);
 863                 break;
 864         case I915_PARAM_CHIPSET_ID:
 865                 value = dev->pci_device;
 866                 break;
 867         default:
 868                 DRM_ERROR("Unknown parameter %d\n", param->param);
 869                 return -EINVAL;
 870         }
 871
 872         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 873                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 874                 return -EFAULT;
 875         }
 876
 877         return 0;
 878 }
 879
 880 static int i915_setparam(struct drm_device *dev, void *data,
 881                          struct drm_file *file_priv)
 882 {
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         drm_i915_setparam_t *param = data;
 885
 886         if (!dev_priv) {
 887                 DRM_ERROR("called with no initialization\n");
 888                 return -EINVAL;
 889         }
 890
 891         switch (param->param) {
 892         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 893                 if (!IS_I965G(dev))
 894                         dev_priv->use_mi_batchbuffer_start = param->value;
 895                 break;
 896         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 897                 dev_priv->tex_lru_log_granularity = param->value;
 898                 break;
 899         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 900                 dev_priv->allow_batchbuffer = param->value;
 901                 break;
 902         default:
 903                 DRM_ERROR("unknown parameter %d\n", param->param);
 904                 return -EINVAL;
 905         }
 906
 907         return 0;
 908 }
 909
 910 drm_i915_mmio_entry_t mmio_table[] = {
 911         [MMIO_REGS_PS_DEPTH_COUNT] = {
 912                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 913                 0x2350,
 914                 8
 915         },
 916         [MMIO_REGS_DOVSTA] = {
 917                 I915_MMIO_MAY_READ,
 918                 0x30008,
 919                 1
 920         },
 921         [MMIO_REGS_GAMMA] = {
 922                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 923                 0x30010,
 924                 6
 925         },
 926         [MMIO_REGS_FENCE] = {
 927                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 928                 0x2000,
 929                 8
 930         },
 931         [MMIO_REGS_FENCE_NEW] = {
 932                 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
 933                 0x3000,
 934                 16
 935         }
 936 };
 937
 938 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
 939
 940 static int i915_mmio(struct drm_device *dev, void *data,
 941                      struct drm_file *file_priv)
 942 {
 943         uint32_t buf[8];
 944         struct drm_i915_private *dev_priv = dev->dev_private;
 945         drm_i915_mmio_entry_t *e;
 946         drm_i915_mmio_t *mmio = data;
 947         void __iomem *base;
 948         int i;
 949
 950         if (!dev_priv) {
 951                 DRM_ERROR("called with no initialization\n");
 952                 return -EINVAL;
 953         }
 954
 955         if (mmio->reg >= mmio_table_size)
 956                 return -EINVAL;
 957
 958         e = &mmio_table[mmio->reg];
 959         base = (u8 *) dev_priv->mmio_map->handle + e->offset;
 960
 961         switch (mmio->read_write) {
 962         case I915_MMIO_READ:
 963                 if (!(e->flag & I915_MMIO_MAY_READ))
 964                         return -EINVAL;
 965                 for (i = 0; i < e->size / 4; i++)
 966                         buf[i] = I915_READ(e->offset + i * 4);
 967                 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
 968                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 969                         return -EFAULT;
 970                 }
 971                 break;
 972
 973         case I915_MMIO_WRITE:
 974                 if (!(e->flag & I915_MMIO_MAY_WRITE))
 975                         return -EINVAL;
 976                 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
 977                         DRM_ERROR("DRM_COPY_TO_USER failed\n");
 978                         return -EFAULT;
 979                 }
 980                 for (i = 0; i < e->size / 4; i++)
 981                         I915_WRITE(e->offset + i * 4, buf[i]);
 982                 break;
 983         }
 984         return 0;
 985 }
 986
 987 static int i915_set_status_page(struct drm_device *dev, void *data,
 988                                 struct drm_file *file_priv)
 989 {
 990         struct drm_i915_private *dev_priv = dev->dev_private;
 991         drm_i915_hws_addr_t *hws = data;
 992
 993         if (!I915_NEED_GFX_HWS(dev))
 994                 return -EINVAL;
 995
 996         if (!dev_priv) {
 997                 DRM_ERROR("called with no initialization\n");
 998                 return -EINVAL;
 999         }
1000         DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1001
1002         dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1003
1004         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1005         dev_priv->hws_map.size = 4*1024;
1006         dev_priv->hws_map.type = 0;
1007         dev_priv->hws_map.flags = 0;
1008         dev_priv->hws_map.mtrr = 0;
1009
1010         drm_core_ioremap(&dev_priv->hws_map, dev);
1011         if (dev_priv->hws_map.handle == NULL) {
1012                 i915_dma_cleanup(dev);
1013                 dev_priv->status_gfx_addr = 0;
1014                 DRM_ERROR("can not ioremap virtual address for"
1015                                 " G33 hw status page\n");
1016                 return -ENOMEM;
1017         }
1018         dev_priv->hw_status_page = dev_priv->hws_map.handle;
1019
1020         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1021         I915_WRITE(I915REG_HWS_PGA, dev_priv->status_gfx_addr);
1022         DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1023                         dev_priv->status_gfx_addr);
1024         DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1025         return 0;
1026 }
1027
1028 struct drm_ioctl_desc i915_ioctls[] = {
1029         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1030         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1031         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1032         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1033         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1034         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1035         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1036         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1037         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1038         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1039         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1040         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1041         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1042         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1043         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
1044         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1045         DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1046         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1047 #ifdef I915_HAVE_BUFFER
1048         DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1049 #endif
1050 };
1051
1052 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1053
1054 /**
1055  * Determine if the device really is AGP or not.
1056  *
1057  * All Intel graphics chipsets are treated as AGP, even if they are really
1058  * PCI-e.
1059  *
1060  * \param dev   The device to be tested.
1061  *
1062  * \returns
1063  * A value of 1 is always retured to indictate every i9x5 is AGP.
1064  */
1065 int i915_driver_device_is_agp(struct drm_device * dev)
1066 {
1067         return 1;
1068 }
1069