1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 /* Really want an OS-independent resettable timer. Would like to have
35 * this loop run for (eg) 3 sec, but have the timer reset every time
36 * the head pointer changes, so that EBUSY only happens if the ring
37 * actually stalls for (eg) 3 seconds.
39 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
41 drm_i915_private_t *dev_priv = dev->dev_private;
42 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
43 u32 last_head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
44 u32 acthd_reg = IS_I965G(dev) ? I965REG_ACTHD : I915REG_ACTHD;
45 u32 last_acthd = I915_READ(acthd_reg);
49 for (i = 0; i < 100000; i++) {
50 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
51 acthd = I915_READ(acthd_reg);
52 ring->space = ring->head - (ring->tail + 8);
54 ring->space += ring->Size;
58 if (ring->head != last_head)
61 if (acthd != last_acthd)
64 last_head = ring->head;
66 msleep_interruptible (10);
72 #if I915_RING_VALIDATE
74 * Validate the cached ring tail value
76 * If the X server writes to the ring and DRM doesn't
77 * reload the head and tail pointers, it will end up writing
78 * data to the wrong place in the ring, causing havoc.
80 void i915_ring_validate(struct drm_device *dev, const char *func, int line)
82 drm_i915_private_t *dev_priv = dev->dev_private;
83 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
84 u32 tail = I915_READ(LP_RING+RING_TAIL) & HEAD_ADDR;
85 u32 head = I915_READ(LP_RING+RING_HEAD) & HEAD_ADDR;
87 if (tail != ring->tail) {
88 DRM_ERROR("%s:%d head sw %x, hw %x. tail sw %x hw %x\n",
90 ring->head, head, ring->tail, tail);
96 void i915_kernel_lost_context(struct drm_device * dev)
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
101 ring->head = I915_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
102 ring->tail = I915_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
103 ring->space = ring->head - (ring->tail + 8);
105 ring->space += ring->Size;
108 static int i915_dma_cleanup(struct drm_device * dev)
110 drm_i915_private_t *dev_priv = dev->dev_private;
111 /* Make sure interrupts are disabled here because the uninstall ioctl
112 * may not have been called from userspace and after dev_private
113 * is freed, it's too late.
116 drm_irq_uninstall(dev);
118 if (dev_priv->ring.virtual_start) {
119 drm_core_ioremapfree(&dev_priv->ring.map, dev);
120 dev_priv->ring.virtual_start = 0;
121 dev_priv->ring.map.handle = 0;
122 dev_priv->ring.map.size = 0;
125 if (dev_priv->status_page_dmah) {
126 drm_pci_free(dev, dev_priv->status_page_dmah);
127 dev_priv->status_page_dmah = NULL;
128 /* Need to rewrite hardware status page */
129 I915_WRITE(0x02080, 0x1ffff000);
132 if (dev_priv->status_gfx_addr) {
133 dev_priv->status_gfx_addr = 0;
134 drm_core_ioremapfree(&dev_priv->hws_map, dev);
135 I915_WRITE(0x02080, 0x1ffff000);
141 #if defined(I915_HAVE_BUFFER)
142 #define DRI2_SAREA_BLOCK_TYPE(b) ((b) >> 16)
143 #define DRI2_SAREA_BLOCK_SIZE(b) ((b) & 0xffff)
144 #define DRI2_SAREA_BLOCK_NEXT(p) \
145 ((void *) ((unsigned char *) (p) + \
146 DRI2_SAREA_BLOCK_SIZE(*(unsigned int *) p)))
148 #define DRI2_SAREA_BLOCK_END 0x0000
149 #define DRI2_SAREA_BLOCK_LOCK 0x0001
150 #define DRI2_SAREA_BLOCK_EVENT_BUFFER 0x0002
153 setup_dri2_sarea(struct drm_device * dev,
154 struct drm_file *file_priv,
155 drm_i915_init_t * init)
157 drm_i915_private_t *dev_priv = dev->dev_private;
159 unsigned int *p, *end, *next;
161 mutex_lock(&dev->struct_mutex);
163 drm_lookup_buffer_object(file_priv,
164 init->sarea_handle, 1);
165 mutex_unlock(&dev->struct_mutex);
167 if (!dev_priv->sarea_bo) {
168 DRM_ERROR("did not find sarea bo\n");
172 ret = drm_bo_kmap(dev_priv->sarea_bo, 0,
173 dev_priv->sarea_bo->num_pages,
174 &dev_priv->sarea_kmap);
176 DRM_ERROR("could not map sarea bo\n");
180 p = dev_priv->sarea_kmap.virtual;
181 end = (void *) p + (dev_priv->sarea_bo->num_pages << PAGE_SHIFT);
182 while (p < end && DRI2_SAREA_BLOCK_TYPE(*p) != DRI2_SAREA_BLOCK_END) {
183 switch (DRI2_SAREA_BLOCK_TYPE(*p)) {
184 case DRI2_SAREA_BLOCK_LOCK:
185 dev->lock.hw_lock = (void *) (p + 1);
186 dev->sigdata.lock = dev->lock.hw_lock;
189 next = DRI2_SAREA_BLOCK_NEXT(p);
190 if (next <= p || end < next) {
191 DRM_ERROR("malformed dri2 sarea: next is %p should be within %p-%p\n",
202 static int i915_initialize(struct drm_device * dev,
203 struct drm_file *file_priv,
204 drm_i915_init_t * init)
206 drm_i915_private_t *dev_priv = dev->dev_private;
207 #if defined(I915_HAVE_BUFFER)
210 dev_priv->sarea = drm_getsarea(dev);
211 if (!dev_priv->sarea) {
212 DRM_ERROR("can not find sarea!\n");
213 i915_dma_cleanup(dev);
217 #ifdef I915_HAVE_BUFFER
218 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
221 if (init->sarea_priv_offset)
222 dev_priv->sarea_priv = (drm_i915_sarea_t *)
223 ((u8 *) dev_priv->sarea->handle +
224 init->sarea_priv_offset);
226 /* No sarea_priv for you! */
227 dev_priv->sarea_priv = NULL;
230 dev_priv->ring.Start = init->ring_start;
231 dev_priv->ring.End = init->ring_end;
232 dev_priv->ring.Size = init->ring_size;
233 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
235 dev_priv->ring.map.offset = init->ring_start;
236 dev_priv->ring.map.size = init->ring_size;
237 dev_priv->ring.map.type = 0;
238 dev_priv->ring.map.flags = 0;
239 dev_priv->ring.map.mtrr = 0;
241 drm_core_ioremap(&dev_priv->ring.map, dev);
243 if (dev_priv->ring.map.handle == NULL) {
244 i915_dma_cleanup(dev);
245 DRM_ERROR("can not ioremap virtual address for"
250 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
252 dev_priv->cpp = init->cpp;
254 if (dev_priv->sarea_priv)
255 dev_priv->sarea_priv->pf_current_page = 0;
257 /* We are using separate values as placeholders for mechanisms for
258 * private backbuffer/depthbuffer usage.
260 dev_priv->use_mi_batchbuffer_start = 0;
261 if (IS_I965G(dev)) /* 965 doesn't support older method */
262 dev_priv->use_mi_batchbuffer_start = 1;
264 /* Allow hardware batchbuffers unless told otherwise.
266 dev_priv->allow_batchbuffer = 1;
268 /* Enable vblank on pipe A for older X servers
270 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
272 /* Program Hardware Status Page */
273 if (!I915_NEED_GFX_HWS(dev)) {
274 dev_priv->status_page_dmah =
275 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
277 if (!dev_priv->status_page_dmah) {
278 i915_dma_cleanup(dev);
279 DRM_ERROR("Can not allocate hardware status page\n");
282 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
283 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
285 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
287 I915_WRITE(0x02080, dev_priv->dma_status_page);
289 DRM_DEBUG("Enabled hardware status page\n");
290 #ifdef I915_HAVE_BUFFER
291 mutex_init(&dev_priv->cmdbuf_mutex);
293 #if defined(I915_HAVE_BUFFER)
294 if (init->func == I915_INIT_DMA2) {
295 ret = setup_dri2_sarea(dev, file_priv, init);
297 i915_dma_cleanup(dev);
298 DRM_ERROR("could not set up dri2 sarea\n");
307 static int i915_dma_resume(struct drm_device * dev)
309 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
313 if (!dev_priv->sarea) {
314 DRM_ERROR("can not find sarea!\n");
318 if (dev_priv->ring.map.handle == NULL) {
319 DRM_ERROR("can not ioremap virtual address for"
324 /* Program Hardware Status Page */
325 if (!dev_priv->hw_status_page) {
326 DRM_ERROR("Can not find hardware status page\n");
329 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
331 if (dev_priv->status_gfx_addr != 0)
332 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
334 I915_WRITE(0x02080, dev_priv->dma_status_page);
335 DRM_DEBUG("Enabled hardware status page\n");
340 static int i915_dma_init(struct drm_device *dev, void *data,
341 struct drm_file *file_priv)
343 drm_i915_init_t *init = data;
346 switch (init->func) {
349 retcode = i915_initialize(dev, file_priv, init);
351 case I915_CLEANUP_DMA:
352 retcode = i915_dma_cleanup(dev);
354 case I915_RESUME_DMA:
355 retcode = i915_dma_resume(dev);
365 /* Implement basically the same security restrictions as hardware does
366 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
368 * Most of the calculations below involve calculating the size of a
369 * particular instruction. It's important to get the size right as
370 * that tells us where the next instruction to check is. Any illegal
371 * instruction detected will be given a size of zero, which is a
372 * signal to abort the rest of the buffer.
374 static int do_validate_cmd(int cmd)
376 switch (((cmd >> 29) & 0x7)) {
378 switch ((cmd >> 23) & 0x3f) {
380 return 1; /* MI_NOOP */
382 return 1; /* MI_FLUSH */
384 return 0; /* disallow everything else */
388 return 0; /* reserved */
390 return (cmd & 0xff) + 2; /* 2d commands */
392 if (((cmd >> 24) & 0x1f) <= 0x18)
395 switch ((cmd >> 24) & 0x1f) {
399 switch ((cmd >> 16) & 0xff) {
401 return (cmd & 0x1f) + 2;
403 return (cmd & 0xf) + 2;
405 return (cmd & 0xffff) + 2;
409 return (cmd & 0xffff) + 1;
413 if ((cmd & (1 << 23)) == 0) /* inline vertices */
414 return (cmd & 0x1ffff) + 2;
415 else if (cmd & (1 << 17)) /* indirect random */
416 if ((cmd & 0xffff) == 0)
417 return 0; /* unknown length, too hard */
419 return (((cmd & 0xffff) + 1) / 2) + 1;
421 return 2; /* indirect sequential */
432 static int validate_cmd(int cmd)
434 int ret = do_validate_cmd(cmd);
436 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
441 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
444 drm_i915_private_t *dev_priv = dev->dev_private;
448 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
451 BEGIN_LP_RING((dwords+1)&~1);
453 for (i = 0; i < dwords;) {
456 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
459 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
465 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
481 int i915_emit_box(struct drm_device * dev,
482 struct drm_clip_rect __user * boxes,
483 int i, int DR1, int DR4)
485 drm_i915_private_t *dev_priv = dev->dev_private;
486 struct drm_clip_rect box;
489 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
493 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
494 DRM_ERROR("Bad box %d,%d..%d,%d\n",
495 box.x1, box.y1, box.x2, box.y2);
501 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
502 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
503 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
508 OUT_RING(GFX_OP_DRAWRECT_INFO);
510 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
511 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
520 /* XXX: Emitting the counter should really be moved to part of the IRQ
521 * emit. For now, do it in both places:
524 void i915_emit_breadcrumb(struct drm_device *dev)
526 drm_i915_private_t *dev_priv = dev->dev_private;
529 if (++dev_priv->counter > BREADCRUMB_MASK) {
530 dev_priv->counter = 1;
531 DRM_DEBUG("Breadcrumb counter wrapped around\n");
534 if (dev_priv->sarea_priv)
535 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
538 OUT_RING(CMD_STORE_DWORD_IDX);
539 OUT_RING(5 << STORE_DWORD_INDEX_SHIFT);
540 OUT_RING(dev_priv->counter);
546 int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush)
548 drm_i915_private_t *dev_priv = dev->dev_private;
549 uint32_t flush_cmd = CMD_MI_FLUSH;
554 i915_kernel_lost_context(dev);
567 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
568 drm_i915_cmdbuffer_t * cmd)
570 #ifdef I915_HAVE_FENCE
571 drm_i915_private_t *dev_priv = dev->dev_private;
573 int nbox = cmd->num_cliprects;
574 int i = 0, count, ret;
577 DRM_ERROR("alignment\n");
581 i915_kernel_lost_context(dev);
583 count = nbox ? nbox : 1;
585 for (i = 0; i < count; i++) {
587 ret = i915_emit_box(dev, cmd->cliprects, i,
593 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
598 i915_emit_breadcrumb(dev);
599 #ifdef I915_HAVE_FENCE
600 if (unlikely((dev_priv->counter & 0xFF) == 0))
601 drm_fence_flush_old(dev, 0, dev_priv->counter);
606 int i915_dispatch_batchbuffer(struct drm_device * dev,
607 drm_i915_batchbuffer_t * batch)
609 drm_i915_private_t *dev_priv = dev->dev_private;
610 struct drm_clip_rect __user *boxes = batch->cliprects;
611 int nbox = batch->num_cliprects;
615 if ((batch->start | batch->used) & 0x7) {
616 DRM_ERROR("alignment\n");
620 i915_kernel_lost_context(dev);
622 count = nbox ? nbox : 1;
624 for (i = 0; i < count; i++) {
626 int ret = i915_emit_box(dev, boxes, i,
627 batch->DR1, batch->DR4);
632 if (dev_priv->use_mi_batchbuffer_start) {
635 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
636 OUT_RING(batch->start);
638 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
639 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
645 OUT_RING(MI_BATCH_BUFFER);
646 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
647 OUT_RING(batch->start + batch->used - 4);
653 i915_emit_breadcrumb(dev);
654 #ifdef I915_HAVE_FENCE
655 if (unlikely((dev_priv->counter & 0xFF) == 0))
656 drm_fence_flush_old(dev, 0, dev_priv->counter);
661 static void i915_do_dispatch_flip(struct drm_device * dev, int plane, int sync)
663 drm_i915_private_t *dev_priv = dev->dev_private;
664 u32 num_pages, current_page, next_page, dspbase;
665 int shift = 2 * plane, x, y;
668 /* Calculate display base offset */
669 num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
670 current_page = (dev_priv->sarea_priv->pf_current_page >> shift) & 0x3;
671 next_page = (current_page + 1) % num_pages;
676 dspbase = dev_priv->sarea_priv->front_offset;
679 dspbase = dev_priv->sarea_priv->back_offset;
682 dspbase = dev_priv->sarea_priv->third_offset;
687 x = dev_priv->sarea_priv->planeA_x;
688 y = dev_priv->sarea_priv->planeA_y;
690 x = dev_priv->sarea_priv->planeB_x;
691 y = dev_priv->sarea_priv->planeB_y;
694 dspbase += (y * dev_priv->sarea_priv->pitch + x) * dev_priv->cpp;
696 DRM_DEBUG("plane=%d current_page=%d dspbase=0x%x\n", plane, current_page,
701 (MI_WAIT_FOR_EVENT | (plane ? MI_WAIT_FOR_PLANE_B_FLIP :
702 MI_WAIT_FOR_PLANE_A_FLIP)));
703 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | (sync ? 0 : ASYNC_FLIP) |
704 (plane ? DISPLAY_PLANE_B : DISPLAY_PLANE_A));
705 OUT_RING(dev_priv->sarea_priv->pitch * dev_priv->cpp);
709 dev_priv->sarea_priv->pf_current_page &= ~(0x3 << shift);
710 dev_priv->sarea_priv->pf_current_page |= next_page << shift;
713 void i915_dispatch_flip(struct drm_device * dev, int planes, int sync)
715 drm_i915_private_t *dev_priv = dev->dev_private;
718 DRM_DEBUG("planes=0x%x pfCurrentPage=%d\n",
719 planes, dev_priv->sarea_priv->pf_current_page);
721 i915_emit_mi_flush(dev, MI_READ_FLUSH | MI_EXE_FLUSH);
723 for (i = 0; i < 2; i++)
724 if (planes & (1 << i))
725 i915_do_dispatch_flip(dev, i, sync);
727 i915_emit_breadcrumb(dev);
728 #ifdef I915_HAVE_FENCE
729 if (unlikely(!sync && ((dev_priv->counter & 0xFF) == 0)))
730 drm_fence_flush_old(dev, 0, dev_priv->counter);
734 int i915_quiescent(struct drm_device *dev)
736 drm_i915_private_t *dev_priv = dev->dev_private;
739 i915_kernel_lost_context(dev);
740 ret = i915_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
743 i915_kernel_lost_context (dev);
744 DRM_ERROR ("not quiescent head %08x tail %08x space %08x\n",
747 dev_priv->ring.space);
752 static int i915_flush_ioctl(struct drm_device *dev, void *data,
753 struct drm_file *file_priv)
756 LOCK_TEST_WITH_RETURN(dev, file_priv);
758 return i915_quiescent(dev);
761 static int i915_batchbuffer(struct drm_device *dev, void *data,
762 struct drm_file *file_priv)
764 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
765 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
766 dev_priv->sarea_priv;
767 drm_i915_batchbuffer_t *batch = data;
770 if (!dev_priv->allow_batchbuffer) {
771 DRM_ERROR("Batchbuffer ioctl disabled\n");
775 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
776 batch->start, batch->used, batch->num_cliprects);
778 LOCK_TEST_WITH_RETURN(dev, file_priv);
780 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
781 batch->num_cliprects *
782 sizeof(struct drm_clip_rect)))
785 ret = i915_dispatch_batchbuffer(dev, batch);
787 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
791 static int i915_cmdbuffer(struct drm_device *dev, void *data,
792 struct drm_file *file_priv)
794 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
795 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
796 dev_priv->sarea_priv;
797 drm_i915_cmdbuffer_t *cmdbuf = data;
800 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
801 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
803 LOCK_TEST_WITH_RETURN(dev, file_priv);
805 if (cmdbuf->num_cliprects &&
806 DRM_VERIFYAREA_READ(cmdbuf->cliprects,
807 cmdbuf->num_cliprects *
808 sizeof(struct drm_clip_rect))) {
809 DRM_ERROR("Fault accessing cliprects\n");
813 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
815 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
819 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
823 #if defined(DRM_DEBUG_CODE)
824 #define DRM_DEBUG_RELOCATION (drm_debug != 0)
826 #define DRM_DEBUG_RELOCATION 0
829 static int i915_do_cleanup_pageflip(struct drm_device * dev)
831 drm_i915_private_t *dev_priv = dev->dev_private;
832 int i, planes, num_pages = dev_priv->sarea_priv->third_handle ? 3 : 2;
836 for (i = 0, planes = 0; i < 2; i++)
837 if (dev_priv->sarea_priv->pf_current_page & (0x3 << (2 * i))) {
838 dev_priv->sarea_priv->pf_current_page =
839 (dev_priv->sarea_priv->pf_current_page &
840 ~(0x3 << (2 * i))) | ((num_pages - 1) << (2 * i));
846 i915_dispatch_flip(dev, planes, 0);
851 static int i915_flip_bufs(struct drm_device *dev, void *data, struct drm_file *file_priv)
853 drm_i915_flip_t *param = data;
857 LOCK_TEST_WITH_RETURN(dev, file_priv);
859 /* This is really planes */
860 if (param->pipes & ~0x3) {
861 DRM_ERROR("Invalid planes 0x%x, only <= 0x3 is valid\n",
866 i915_dispatch_flip(dev, param->pipes, 0);
872 static int i915_getparam(struct drm_device *dev, void *data,
873 struct drm_file *file_priv)
875 drm_i915_private_t *dev_priv = dev->dev_private;
876 drm_i915_getparam_t *param = data;
880 DRM_ERROR("called with no initialization\n");
884 switch (param->param) {
885 case I915_PARAM_IRQ_ACTIVE:
886 value = dev->irq ? 1 : 0;
888 case I915_PARAM_ALLOW_BATCHBUFFER:
889 value = dev_priv->allow_batchbuffer ? 1 : 0;
891 case I915_PARAM_LAST_DISPATCH:
892 value = READ_BREADCRUMB(dev_priv);
894 case I915_PARAM_CHIPSET_ID:
895 value = dev->pci_device;
898 DRM_ERROR("Unknown parameter %d\n", param->param);
902 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
903 DRM_ERROR("DRM_COPY_TO_USER failed\n");
910 static int i915_setparam(struct drm_device *dev, void *data,
911 struct drm_file *file_priv)
913 drm_i915_private_t *dev_priv = dev->dev_private;
914 drm_i915_setparam_t *param = data;
917 DRM_ERROR("called with no initialization\n");
921 switch (param->param) {
922 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
924 dev_priv->use_mi_batchbuffer_start = param->value;
926 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
927 dev_priv->tex_lru_log_granularity = param->value;
929 case I915_SETPARAM_ALLOW_BATCHBUFFER:
930 dev_priv->allow_batchbuffer = param->value;
933 DRM_ERROR("unknown parameter %d\n", param->param);
940 drm_i915_mmio_entry_t mmio_table[] = {
941 [MMIO_REGS_PS_DEPTH_COUNT] = {
942 I915_MMIO_MAY_READ|I915_MMIO_MAY_WRITE,
948 static int mmio_table_size = sizeof(mmio_table)/sizeof(drm_i915_mmio_entry_t);
950 static int i915_mmio(struct drm_device *dev, void *data,
951 struct drm_file *file_priv)
954 drm_i915_private_t *dev_priv = dev->dev_private;
955 drm_i915_mmio_entry_t *e;
956 drm_i915_mmio_t *mmio = data;
961 DRM_ERROR("called with no initialization\n");
965 if (mmio->reg >= mmio_table_size)
968 e = &mmio_table[mmio->reg];
969 base = (u8 *) dev_priv->mmio_map->handle + e->offset;
971 switch (mmio->read_write) {
973 if (!(e->flag & I915_MMIO_MAY_READ))
975 for (i = 0; i < e->size / 4; i++)
976 buf[i] = I915_READ(e->offset + i * 4);
977 if (DRM_COPY_TO_USER(mmio->data, buf, e->size)) {
978 DRM_ERROR("DRM_COPY_TO_USER failed\n");
983 case I915_MMIO_WRITE:
984 if (!(e->flag & I915_MMIO_MAY_WRITE))
986 if (DRM_COPY_FROM_USER(buf, mmio->data, e->size)) {
987 DRM_ERROR("DRM_COPY_TO_USER failed\n");
990 for (i = 0; i < e->size / 4; i++)
991 I915_WRITE(e->offset + i * 4, buf[i]);
997 static int i915_set_status_page(struct drm_device *dev, void *data,
998 struct drm_file *file_priv)
1000 drm_i915_private_t *dev_priv = dev->dev_private;
1001 drm_i915_hws_addr_t *hws = data;
1003 if (!I915_NEED_GFX_HWS(dev))
1007 DRM_ERROR("called with no initialization\n");
1010 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
1012 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
1014 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1015 dev_priv->hws_map.size = 4*1024;
1016 dev_priv->hws_map.type = 0;
1017 dev_priv->hws_map.flags = 0;
1018 dev_priv->hws_map.mtrr = 0;
1020 drm_core_ioremap(&dev_priv->hws_map, dev);
1021 if (dev_priv->hws_map.handle == NULL) {
1022 i915_dma_cleanup(dev);
1023 dev_priv->status_gfx_addr = 0;
1024 DRM_ERROR("can not ioremap virtual address for"
1025 " G33 hw status page\n");
1028 dev_priv->hw_status_page = dev_priv->hws_map.handle;
1030 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1031 I915_WRITE(0x02080, dev_priv->status_gfx_addr);
1032 DRM_DEBUG("load hws 0x2080 with gfx mem 0x%x\n",
1033 dev_priv->status_gfx_addr);
1034 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
1038 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1040 struct drm_i915_private *dev_priv = dev->dev_private;
1041 unsigned long base, size;
1042 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
1044 /* i915 has 4 more counters */
1046 dev->types[6] = _DRM_STAT_IRQ;
1047 dev->types[7] = _DRM_STAT_PRIMARY;
1048 dev->types[8] = _DRM_STAT_SECONDARY;
1049 dev->types[9] = _DRM_STAT_DMA;
1051 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
1052 if (dev_priv == NULL)
1055 memset(dev_priv, 0, sizeof(drm_i915_private_t));
1057 dev->dev_private = (void *)dev_priv;
1058 dev_priv->dev = dev;
1060 /* Add register map (needed for suspend/resume) */
1061 base = drm_get_resource_start(dev, mmio_bar);
1062 size = drm_get_resource_len(dev, mmio_bar);
1064 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1065 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1067 INIT_LIST_HEAD(&dev_priv->mm.active_list);
1068 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
1069 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
1070 INIT_LIST_HEAD(&dev_priv->mm.request_list);
1071 INIT_WORK(&dev_priv->user_interrupt_task,
1072 i915_user_interrupt_handler);
1073 dev_priv->mm.next_gem_seqno = 1;
1076 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1077 intel_init_chipset_flush_compat(dev);
1084 int i915_driver_unload(struct drm_device *dev)
1086 struct drm_i915_private *dev_priv = dev->dev_private;
1088 if (dev_priv->mmio_map)
1089 drm_rmmap(dev, dev_priv->mmio_map);
1091 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
1094 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
1095 intel_fini_chipset_flush_compat(dev);
1101 void i915_driver_lastclose(struct drm_device * dev)
1103 drm_i915_private_t *dev_priv = dev->dev_private;
1105 /* agp off can use this to get called before dev_priv */
1109 #ifdef I915_HAVE_BUFFER
1110 if (dev_priv->val_bufs) {
1111 vfree(dev_priv->val_bufs);
1112 dev_priv->val_bufs = NULL;
1115 i915_gem_lastclose(dev);
1117 if (drm_getsarea(dev) && dev_priv->sarea_priv)
1118 i915_do_cleanup_pageflip(dev);
1119 if (dev_priv->agp_heap)
1120 i915_mem_takedown(&(dev_priv->agp_heap));
1121 #if defined(I915_HAVE_BUFFER)
1122 if (dev_priv->sarea_kmap.virtual) {
1123 drm_bo_kunmap(&dev_priv->sarea_kmap);
1124 dev_priv->sarea_kmap.virtual = NULL;
1125 dev->lock.hw_lock = NULL;
1126 dev->sigdata.lock = NULL;
1129 if (dev_priv->sarea_bo) {
1130 mutex_lock(&dev->struct_mutex);
1131 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
1132 mutex_unlock(&dev->struct_mutex);
1133 dev_priv->sarea_bo = NULL;
1136 i915_dma_cleanup(dev);
1139 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1141 drm_i915_private_t *dev_priv = dev->dev_private;
1142 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
1145 struct drm_ioctl_desc i915_ioctls[] = {
1146 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1147 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1148 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
1149 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1150 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1151 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1152 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
1153 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1154 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
1155 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
1156 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1157 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1158 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1159 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1160 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1161 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1162 DRM_IOCTL_DEF(DRM_I915_MMIO, i915_mmio, DRM_AUTH),
1163 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
1164 #ifdef I915_HAVE_BUFFER
1165 DRM_IOCTL_DEF(DRM_I915_EXECBUFFER, i915_execbuffer, DRM_AUTH),
1167 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH),
1168 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1169 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1170 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1171 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1174 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1177 * Determine if the device really is AGP or not.
1179 * All Intel graphics chipsets are treated as AGP, even if they are really
1182 * \param dev The device to be tested.
1185 * A value of 1 is always retured to indictate every i9x5 is AGP.
1187 int i915_driver_device_is_agp(struct drm_device * dev)
1192 int i915_driver_firstopen(struct drm_device *dev)
1194 #ifdef I915_HAVE_BUFFER
1195 drm_bo_driver_init(dev);