2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 /* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init {
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03,
48 /* Since this struct isn't versioned, just used a new
49 * 'func' code to indicate the presence of dri2 sarea
53 unsigned int mmio_offset;
54 int sarea_priv_offset;
55 unsigned int ring_start;
56 unsigned int ring_end;
57 unsigned int ring_size;
58 unsigned int front_offset;
59 unsigned int back_offset;
60 unsigned int depth_offset;
64 unsigned int pitch_bits;
65 unsigned int back_pitch;
66 unsigned int depth_pitch;
69 unsigned int sarea_handle;
72 typedef struct drm_i915_sarea {
73 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
74 int last_upload; /* last time texture was uploaded */
75 int last_enqueue; /* last time a buffer was enqueued */
76 int last_dispatch; /* age of the most recently dispatched buffer */
77 int ctxOwner; /* last context to upload state */
79 int pf_enabled; /* is pageflipping allowed? */
81 int pf_current_page; /* which buffer is being displayed? */
82 int perf_boxes; /* performance boxes to be displayed */
83 int width, height; /* screen size in pixels */
85 drm_handle_t front_handle;
89 drm_handle_t back_handle;
93 drm_handle_t depth_handle;
97 drm_handle_t tex_handle;
100 int log_tex_granularity;
102 int rotation; /* 0, 90, 180 or 270 */
106 int virtualX, virtualY;
108 unsigned int front_tiled;
109 unsigned int back_tiled;
110 unsigned int depth_tiled;
111 unsigned int rotated_tiled;
112 unsigned int rotated2_tiled;
114 /* compat defines for the period of time when pipeA_* got renamed
115 * to planeA_*. They mean pipe, really.
117 #define planeA_x pipeA_x
118 #define planeA_y pipeA_y
119 #define planeA_w pipeA_w
120 #define planeA_h pipeA_h
121 #define planeB_x pipeB_x
122 #define planeB_y pipeB_y
123 #define planeB_w pipeB_w
124 #define planeB_h pipeB_h
134 /* Triple buffering */
135 drm_handle_t third_handle;
138 unsigned int third_tiled;
140 /* buffer object handles for the static buffers. May change
141 * over the lifetime of the client, though it doesn't in our current
144 unsigned int front_bo_handle;
145 unsigned int back_bo_handle;
146 unsigned int third_bo_handle;
147 unsigned int depth_bo_handle;
150 /* Driver specific fence types and classes.
153 /* The only fence class we support */
154 #define DRM_I915_FENCE_CLASS_ACCEL 0
155 /* Fence type that guarantees read-write flush */
156 #define DRM_I915_FENCE_TYPE_RW 2
157 /* MI_FLUSH programmed just before the fence */
158 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
160 /* Flags for perf_boxes
162 #define I915_BOX_RING_EMPTY 0x1
163 #define I915_BOX_FLIP 0x2
164 #define I915_BOX_WAIT 0x4
165 #define I915_BOX_TEXTURE_LOAD 0x8
166 #define I915_BOX_LOST_CONTEXT 0x10
168 /* I915 specific ioctls
169 * The device specific ioctl range is 0x40 to 0x79.
171 #define DRM_I915_INIT 0x00
172 #define DRM_I915_FLUSH 0x01
173 #define DRM_I915_FLIP 0x02
174 #define DRM_I915_BATCHBUFFER 0x03
175 #define DRM_I915_IRQ_EMIT 0x04
176 #define DRM_I915_IRQ_WAIT 0x05
177 #define DRM_I915_GETPARAM 0x06
178 #define DRM_I915_SETPARAM 0x07
179 #define DRM_I915_ALLOC 0x08
180 #define DRM_I915_FREE 0x09
181 #define DRM_I915_INIT_HEAP 0x0a
182 #define DRM_I915_CMDBUFFER 0x0b
183 #define DRM_I915_DESTROY_HEAP 0x0c
184 #define DRM_I915_SET_VBLANK_PIPE 0x0d
185 #define DRM_I915_GET_VBLANK_PIPE 0x0e
186 #define DRM_I915_VBLANK_SWAP 0x0f
187 #define DRM_I915_MMIO 0x10
188 #define DRM_I915_HWS_ADDR 0x11
189 #define DRM_I915_EXECBUFFER 0x12
190 #define DRM_I915_GEM_INIT 0x13
191 #define DRM_I915_GEM_EXECBUFFER 0x14
192 #define DRM_I915_GEM_PIN 0x15
193 #define DRM_I915_GEM_UNPIN 0x16
194 #define DRM_I915_GEM_BUSY 0x17
195 #define DRM_I915_GEM_THROTTLE 0x18
196 #define DRM_I915_GEM_ENTERVT 0x19
197 #define DRM_I915_GEM_LEAVEVT 0x1a
198 #define DRM_I915_GEM_CREATE 0x1b
199 #define DRM_I915_GEM_PREAD 0x1c
200 #define DRM_I915_GEM_PWRITE 0x1d
201 #define DRM_I915_GEM_MMAP 0x1e
202 #define DRM_I915_GEM_SET_DOMAIN 0x1f
203 #define DRM_I915_GEM_SW_FINISH 0x20
204 #define DRM_I915_GEM_SET_TILING 0x21
205 #define DRM_I915_GEM_GET_TILING 0x22
206 #define DRM_I915_GEM_GET_APERTURE 0x23
207 #define DRM_I915_GEM_MMAP_GTT 0x24
208 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
210 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
211 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
212 #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
213 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
214 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
215 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
216 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
217 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
218 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
219 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
220 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
221 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
222 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
223 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
224 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
225 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
226 #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
227 #define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
228 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
229 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
230 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
231 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
232 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
233 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
234 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
235 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
236 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
237 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
238 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
239 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
240 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
241 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
242 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
243 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
244 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
245 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
246 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
248 /* Asynchronous page flipping:
250 typedef struct drm_i915_flip {
252 * This is really talking about planes, and we could rename it
253 * except for the fact that some of the duplicated i915_drm.h files
254 * out there check for HAVE_I915_FLIP and so might pick up this
260 /* Allow drivers to submit batchbuffers directly to hardware, relying
261 * on the security mechanisms provided by hardware.
263 typedef struct drm_i915_batchbuffer {
264 int start; /* agp offset */
265 int used; /* nr bytes in use */
266 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
267 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
268 int num_cliprects; /* mulitpass with multiple cliprects? */
269 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
270 } drm_i915_batchbuffer_t;
272 /* As above, but pass a pointer to userspace buffer which can be
273 * validated by the kernel prior to sending to hardware.
275 typedef struct _drm_i915_cmdbuffer {
276 char __user *buf; /* pointer to userspace command buffer */
277 int sz; /* nr bytes in buf */
278 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
279 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
280 int num_cliprects; /* mulitpass with multiple cliprects? */
281 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
282 } drm_i915_cmdbuffer_t;
284 /* Userspace can request & wait on irq's:
286 typedef struct drm_i915_irq_emit {
288 } drm_i915_irq_emit_t;
290 typedef struct drm_i915_irq_wait {
292 } drm_i915_irq_wait_t;
294 /* Ioctl to query kernel params:
296 #define I915_PARAM_IRQ_ACTIVE 1
297 #define I915_PARAM_ALLOW_BATCHBUFFER 2
298 #define I915_PARAM_LAST_DISPATCH 3
299 #define I915_PARAM_CHIPSET_ID 4
300 #define I915_PARAM_HAS_GEM 5
301 #define I915_PARAM_NUM_FENCES_AVAIL 6
303 typedef struct drm_i915_getparam {
306 } drm_i915_getparam_t;
308 /* Ioctl to set kernel params:
310 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
311 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
312 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
313 #define I915_SETPARAM_NUM_USED_FENCES 4
315 typedef struct drm_i915_setparam {
318 } drm_i915_setparam_t;
320 /* A memory manager for regions of shared memory:
322 #define I915_MEM_REGION_AGP 1
324 typedef struct drm_i915_mem_alloc {
328 int __user *region_offset; /* offset from start of fb or agp */
329 } drm_i915_mem_alloc_t;
331 typedef struct drm_i915_mem_free {
334 } drm_i915_mem_free_t;
336 typedef struct drm_i915_mem_init_heap {
340 } drm_i915_mem_init_heap_t;
342 /* Allow memory manager to be torn down and re-initialized (eg on
345 typedef struct drm_i915_mem_destroy_heap {
347 } drm_i915_mem_destroy_heap_t;
349 /* Allow X server to configure which pipes to monitor for vblank signals
351 #define DRM_I915_VBLANK_PIPE_A 1
352 #define DRM_I915_VBLANK_PIPE_B 2
354 typedef struct drm_i915_vblank_pipe {
356 } drm_i915_vblank_pipe_t;
358 /* Schedule buffer swap at given vertical blank:
360 typedef struct drm_i915_vblank_swap {
361 drm_drawable_t drawable;
362 enum drm_vblank_seq_type seqtype;
363 unsigned int sequence;
364 } drm_i915_vblank_swap_t;
366 #define I915_MMIO_READ 0
367 #define I915_MMIO_WRITE 1
369 #define I915_MMIO_MAY_READ 0x1
370 #define I915_MMIO_MAY_WRITE 0x2
372 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0
373 #define MMIO_REGS_IA_VERTICES_COUNT 1
374 #define MMIO_REGS_VS_INVOCATION_COUNT 2
375 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3
376 #define MMIO_REGS_GS_INVOCATION_COUNT 4
377 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5
378 #define MMIO_REGS_CL_INVOCATION_COUNT 6
379 #define MMIO_REGS_PS_INVOCATION_COUNT 7
380 #define MMIO_REGS_PS_DEPTH_COUNT 8
382 typedef struct drm_i915_mmio_entry {
386 } drm_i915_mmio_entry_t;
388 typedef struct drm_i915_mmio {
389 unsigned int read_write:1;
394 typedef struct drm_i915_hws_addr {
396 } drm_i915_hws_addr_t;
399 * Relocation header is 4 uint32_ts
400 * 0 - 32 bit reloc count
401 * 1 - 32-bit relocation type
402 * 2-3 - 64-bit user buffer handle ptr for another list of relocs.
404 #define I915_RELOC_HEADER 4
407 * type 0 relocation has 4-uint32_t stride
408 * 0 - offset into buffer
409 * 1 - delta to add in
411 * 3 - reserved (for optimisations later).
414 * type 1 relocation has 4-uint32_t stride.
415 * Hangs off the first item in the op list.
416 * Performed after all valiations are done.
417 * Try to group relocs into the same relocatee together for
418 * performance reasons.
419 * 0 - offset into buffer
420 * 1 - delta to add in
421 * 2 - buffer index in op list.
422 * 3 - relocatee index in op list.
424 #define I915_RELOC_TYPE_0 0
425 #define I915_RELOC0_STRIDE 4
426 #define I915_RELOC_TYPE_1 1
427 #define I915_RELOC1_STRIDE 4
430 struct drm_i915_op_arg {
436 struct drm_bo_op_req req;
437 struct drm_bo_arg_rep rep;
442 struct drm_i915_execbuffer {
444 uint32_t num_buffers;
445 struct drm_i915_batchbuffer batch;
446 drm_context_t context; /* for lockless use in the future */
447 struct drm_fence_arg fence_arg;
450 struct drm_i915_gem_init {
452 * Beginning offset in the GTT to be managed by the DRM memory
457 * Ending offset in the GTT to be managed by the DRM memory
463 struct drm_i915_gem_create {
465 * Requested size for the object.
467 * The (page-aligned) allocated size for the object will be returned.
471 * Returned handle for the object.
473 * Object handles are nonzero.
479 struct drm_i915_gem_pread {
480 /** Handle for the object being read. */
483 /** Offset into the object to read from */
485 /** Length of data to read */
488 * Pointer to write the data into.
490 * This is a fixed-size type for 32/64 compatibility.
495 struct drm_i915_gem_pwrite {
496 /** Handle for the object being written to. */
499 /** Offset into the object to write to */
501 /** Length of data to write */
504 * Pointer to read the data from.
506 * This is a fixed-size type for 32/64 compatibility.
511 struct drm_i915_gem_mmap {
512 /** Handle for the object being mapped. */
515 /** Offset in the object to map. */
518 * Length of data to map.
520 * The value will be page-aligned.
524 * Returned pointer the data was mapped at.
526 * This is a fixed-size type for 32/64 compatibility.
531 struct drm_i915_gem_mmap_gtt {
532 /** Handle for the object being mapped. */
536 * Fake offset to use for subsequent mmap call
538 * This is a fixed-size type for 32/64 compatibility.
543 struct drm_i915_gem_set_domain {
544 /** Handle for the object */
547 /** New read domains */
548 uint32_t read_domains;
550 /** New write domain */
551 uint32_t write_domain;
554 struct drm_i915_gem_sw_finish {
555 /** Handle for the object */
559 struct drm_i915_gem_relocation_entry {
561 * Handle of the buffer being pointed to by this relocation entry.
563 * It's appealing to make this be an index into the mm_validate_entry
564 * list to refer to the buffer, but this allows the driver to create
565 * a relocation list for state buffers and not re-write it per
566 * exec using the buffer.
568 uint32_t target_handle;
571 * Value to be added to the offset of the target buffer to make up
572 * the relocation entry.
576 /** Offset in the buffer the relocation entry will be written into */
580 * Offset value of the target buffer that the relocation entry was last
583 * If the buffer has the same offset as last time, we can skip syncing
584 * and writing the relocation. This value is written back out by
585 * the execbuffer ioctl when the relocation is written.
587 uint64_t presumed_offset;
590 * Target memory domains read by this operation.
592 uint32_t read_domains;
595 * Target memory domains written by this operation.
597 * Note that only one domain may be written by the whole
598 * execbuffer operation, so that where there are conflicts,
599 * the application will get -EINVAL back.
601 uint32_t write_domain;
605 * Intel memory domains
607 * Most of these just align with the various caches in
608 * the system and are used to flush and invalidate as
609 * objects end up cached in different domains.
612 #define I915_GEM_DOMAIN_CPU 0x00000001
613 /** Render cache, used by 2D and 3D drawing */
614 #define I915_GEM_DOMAIN_RENDER 0x00000002
615 /** Sampler cache, used by texture engine */
616 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
617 /** Command queue, used to load batch buffers */
618 #define I915_GEM_DOMAIN_COMMAND 0x00000008
619 /** Instruction cache, used by shader programs */
620 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
621 /** Vertex address cache */
622 #define I915_GEM_DOMAIN_VERTEX 0x00000020
623 /** GTT domain - aperture and scanout */
624 #define I915_GEM_DOMAIN_GTT 0x00000040
627 struct drm_i915_gem_exec_object {
629 * User's handle for a buffer to be bound into the GTT for this
634 /** Number of relocations to be performed on this buffer */
635 uint32_t relocation_count;
637 * Pointer to array of struct drm_i915_gem_relocation_entry containing
638 * the relocations to be performed in this buffer.
642 /** Required alignment in graphics aperture */
646 * Returned value of the updated offset of the object, for future
647 * presumed_offset writes.
652 struct drm_i915_gem_execbuffer {
654 * List of buffers to be validated with their relocations to be
655 * performend on them.
657 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
659 * These buffers must be listed in an order such that all relocations
660 * a buffer is performing refer to buffers that have already appeared
661 * in the validate list.
663 uint64_t buffers_ptr;
664 uint32_t buffer_count;
666 /** Offset in the batchbuffer to start execution from. */
667 uint32_t batch_start_offset;
668 /** Bytes used in batchbuffer from batch_start_offset */
672 uint32_t num_cliprects;
673 /** This is a struct drm_clip_rect *cliprects */
674 uint64_t cliprects_ptr;
677 struct drm_i915_gem_pin {
678 /** Handle of the buffer to be pinned. */
682 /** alignment required within the aperture */
685 /** Returned GTT offset of the buffer. */
689 struct drm_i915_gem_unpin {
690 /** Handle of the buffer to be unpinned. */
695 struct drm_i915_gem_busy {
696 /** Handle of the buffer to check for busy */
699 /** Return busy status (1 if busy, 0 if idle) */
703 #define I915_TILING_NONE 0
704 #define I915_TILING_X 1
705 #define I915_TILING_Y 2
707 #define I915_BIT_6_SWIZZLE_NONE 0
708 #define I915_BIT_6_SWIZZLE_9 1
709 #define I915_BIT_6_SWIZZLE_9_10 2
710 #define I915_BIT_6_SWIZZLE_9_11 3
711 #define I915_BIT_6_SWIZZLE_9_10_11 4
712 /* Not seen by userland */
713 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
715 struct drm_i915_gem_set_tiling {
716 /** Handle of the buffer to have its tiling state updated */
720 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
723 * This value is to be set on request, and will be updated by the
724 * kernel on successful return with the actual chosen tiling layout.
726 * The tiling mode may be demoted to I915_TILING_NONE when the system
727 * has bit 6 swizzling that can't be managed correctly by GEM.
729 * Buffer contents become undefined when changing tiling_mode.
731 uint32_t tiling_mode;
734 * Stride in bytes for the object when in I915_TILING_X or
740 * Returned address bit 6 swizzling required for CPU access through
743 uint32_t swizzle_mode;
746 struct drm_i915_gem_get_tiling {
747 /** Handle of the buffer to get tiling state for. */
751 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
754 uint32_t tiling_mode;
757 * Returned address bit 6 swizzling required for CPU access through
760 uint32_t swizzle_mode;
763 struct drm_i915_gem_get_aperture {
764 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
768 * Available space in the aperture used by i915_gem_execbuffer, in
771 uint64_t aper_available_size;
774 struct drm_i915_get_pipe_from_crtc_id {
775 /** ID of CRTC being requested **/
778 /** pipe of requested CRTC **/
782 #endif /* _I915_DRM_H_ */