2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 /* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
36 /* Each region is a minimum of 16k, and there are at most 255 of them.
38 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40 #define I915_LOG_MIN_TEX_REGION_SIZE 14
42 typedef struct _drm_i915_init {
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03,
48 /* Since this struct isn't versioned, just used a new
49 * 'func' code to indicate the presence of dri2 sarea
53 unsigned int mmio_offset;
54 int sarea_priv_offset;
55 unsigned int ring_start;
56 unsigned int ring_end;
57 unsigned int ring_size;
58 unsigned int front_offset;
59 unsigned int back_offset;
60 unsigned int depth_offset;
64 unsigned int pitch_bits;
65 unsigned int back_pitch;
66 unsigned int depth_pitch;
69 unsigned int sarea_handle;
72 typedef struct drm_i915_sarea {
73 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
74 int last_upload; /* last time texture was uploaded */
75 int last_enqueue; /* last time a buffer was enqueued */
76 int last_dispatch; /* age of the most recently dispatched buffer */
77 int ctxOwner; /* last context to upload state */
79 int pf_enabled; /* is pageflipping allowed? */
81 int pf_current_page; /* which buffer is being displayed? */
82 int perf_boxes; /* performance boxes to be displayed */
83 int width, height; /* screen size in pixels */
85 drm_handle_t front_handle;
89 drm_handle_t back_handle;
93 drm_handle_t depth_handle;
97 drm_handle_t tex_handle;
100 int log_tex_granularity;
102 int rotation; /* 0, 90, 180 or 270 */
106 int virtualX, virtualY;
108 unsigned int front_tiled;
109 unsigned int back_tiled;
110 unsigned int depth_tiled;
111 unsigned int rotated_tiled;
112 unsigned int rotated2_tiled;
123 /* Triple buffering */
124 drm_handle_t third_handle;
127 unsigned int third_tiled;
129 /* buffer object handles for the static buffers. May change
130 * over the lifetime of the client, though it doesn't in our current
133 unsigned int front_bo_handle;
134 unsigned int back_bo_handle;
135 unsigned int third_bo_handle;
136 unsigned int depth_bo_handle;
139 /* Driver specific fence types and classes.
142 /* The only fence class we support */
143 #define DRM_I915_FENCE_CLASS_ACCEL 0
144 /* Fence type that guarantees read-write flush */
145 #define DRM_I915_FENCE_TYPE_RW 2
146 /* MI_FLUSH programmed just before the fence */
147 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
149 /* Flags for perf_boxes
151 #define I915_BOX_RING_EMPTY 0x1
152 #define I915_BOX_FLIP 0x2
153 #define I915_BOX_WAIT 0x4
154 #define I915_BOX_TEXTURE_LOAD 0x8
155 #define I915_BOX_LOST_CONTEXT 0x10
157 /* I915 specific ioctls
158 * The device specific ioctl range is 0x40 to 0x79.
160 #define DRM_I915_INIT 0x00
161 #define DRM_I915_FLUSH 0x01
162 #define DRM_I915_FLIP 0x02
163 #define DRM_I915_BATCHBUFFER 0x03
164 #define DRM_I915_IRQ_EMIT 0x04
165 #define DRM_I915_IRQ_WAIT 0x05
166 #define DRM_I915_GETPARAM 0x06
167 #define DRM_I915_SETPARAM 0x07
168 #define DRM_I915_ALLOC 0x08
169 #define DRM_I915_FREE 0x09
170 #define DRM_I915_INIT_HEAP 0x0a
171 #define DRM_I915_CMDBUFFER 0x0b
172 #define DRM_I915_DESTROY_HEAP 0x0c
173 #define DRM_I915_SET_VBLANK_PIPE 0x0d
174 #define DRM_I915_GET_VBLANK_PIPE 0x0e
175 #define DRM_I915_VBLANK_SWAP 0x0f
176 #define DRM_I915_MMIO 0x10
177 #define DRM_I915_HWS_ADDR 0x11
178 #define DRM_I915_EXECBUFFER 0x12
179 #define DRM_I915_GEM_INIT 0x13
180 #define DRM_I915_GEM_EXECBUFFER 0x14
181 #define DRM_I915_GEM_PIN 0x15
182 #define DRM_I915_GEM_UNPIN 0x16
183 #define DRM_I915_GEM_BUSY 0x17
184 #define DRM_I915_GEM_THROTTLE 0x18
185 #define DRM_I915_GEM_ENTERVT 0x19
186 #define DRM_I915_GEM_LEAVEVT 0x20
188 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
189 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
190 #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
191 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
192 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
193 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
194 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
195 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
196 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
197 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
198 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
199 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
200 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
201 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
202 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
203 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
204 #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
205 #define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
206 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
207 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
208 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
209 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
210 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
211 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
212 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
213 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
215 /* Asynchronous page flipping:
217 typedef struct drm_i915_flip {
219 * This is really talking about planes, and we could rename it
220 * except for the fact that some of the duplicated i915_drm.h files
221 * out there check for HAVE_I915_FLIP and so might pick up this
227 /* Allow drivers to submit batchbuffers directly to hardware, relying
228 * on the security mechanisms provided by hardware.
230 typedef struct drm_i915_batchbuffer {
231 int start; /* agp offset */
232 int used; /* nr bytes in use */
233 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
234 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
235 int num_cliprects; /* mulitpass with multiple cliprects? */
236 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
237 } drm_i915_batchbuffer_t;
239 /* As above, but pass a pointer to userspace buffer which can be
240 * validated by the kernel prior to sending to hardware.
242 typedef struct _drm_i915_cmdbuffer {
243 char __user *buf; /* pointer to userspace command buffer */
244 int sz; /* nr bytes in buf */
245 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
246 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
247 int num_cliprects; /* mulitpass with multiple cliprects? */
248 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
249 } drm_i915_cmdbuffer_t;
251 /* Userspace can request & wait on irq's:
253 typedef struct drm_i915_irq_emit {
255 } drm_i915_irq_emit_t;
257 typedef struct drm_i915_irq_wait {
259 } drm_i915_irq_wait_t;
261 /* Ioctl to query kernel params:
263 #define I915_PARAM_IRQ_ACTIVE 1
264 #define I915_PARAM_ALLOW_BATCHBUFFER 2
265 #define I915_PARAM_LAST_DISPATCH 3
266 #define I915_PARAM_CHIPSET_ID 4
268 typedef struct drm_i915_getparam {
271 } drm_i915_getparam_t;
273 /* Ioctl to set kernel params:
275 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
276 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
277 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
279 typedef struct drm_i915_setparam {
282 } drm_i915_setparam_t;
284 /* A memory manager for regions of shared memory:
286 #define I915_MEM_REGION_AGP 1
288 typedef struct drm_i915_mem_alloc {
292 int __user *region_offset; /* offset from start of fb or agp */
293 } drm_i915_mem_alloc_t;
295 typedef struct drm_i915_mem_free {
298 } drm_i915_mem_free_t;
300 typedef struct drm_i915_mem_init_heap {
304 } drm_i915_mem_init_heap_t;
306 /* Allow memory manager to be torn down and re-initialized (eg on
309 typedef struct drm_i915_mem_destroy_heap {
311 } drm_i915_mem_destroy_heap_t;
313 /* Allow X server to configure which pipes to monitor for vblank signals
315 #define DRM_I915_VBLANK_PIPE_A 1
316 #define DRM_I915_VBLANK_PIPE_B 2
318 typedef struct drm_i915_vblank_pipe {
320 } drm_i915_vblank_pipe_t;
322 /* Schedule buffer swap at given vertical blank:
324 typedef struct drm_i915_vblank_swap {
325 drm_drawable_t drawable;
326 enum drm_vblank_seq_type seqtype;
327 unsigned int sequence;
328 } drm_i915_vblank_swap_t;
330 #define I915_MMIO_READ 0
331 #define I915_MMIO_WRITE 1
333 #define I915_MMIO_MAY_READ 0x1
334 #define I915_MMIO_MAY_WRITE 0x2
336 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0
337 #define MMIO_REGS_IA_VERTICES_COUNT 1
338 #define MMIO_REGS_VS_INVOCATION_COUNT 2
339 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3
340 #define MMIO_REGS_GS_INVOCATION_COUNT 4
341 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5
342 #define MMIO_REGS_CL_INVOCATION_COUNT 6
343 #define MMIO_REGS_PS_INVOCATION_COUNT 7
344 #define MMIO_REGS_PS_DEPTH_COUNT 8
346 typedef struct drm_i915_mmio_entry {
350 } drm_i915_mmio_entry_t;
352 typedef struct drm_i915_mmio {
353 unsigned int read_write:1;
358 typedef struct drm_i915_hws_addr {
360 } drm_i915_hws_addr_t;
363 * Relocation header is 4 uint32_ts
364 * 0 - 32 bit reloc count
365 * 1 - 32-bit relocation type
366 * 2-3 - 64-bit user buffer handle ptr for another list of relocs.
368 #define I915_RELOC_HEADER 4
371 * type 0 relocation has 4-uint32_t stride
372 * 0 - offset into buffer
373 * 1 - delta to add in
375 * 3 - reserved (for optimisations later).
378 * type 1 relocation has 4-uint32_t stride.
379 * Hangs off the first item in the op list.
380 * Performed after all valiations are done.
381 * Try to group relocs into the same relocatee together for
382 * performance reasons.
383 * 0 - offset into buffer
384 * 1 - delta to add in
385 * 2 - buffer index in op list.
386 * 3 - relocatee index in op list.
388 #define I915_RELOC_TYPE_0 0
389 #define I915_RELOC0_STRIDE 4
390 #define I915_RELOC_TYPE_1 1
391 #define I915_RELOC1_STRIDE 4
394 struct drm_i915_op_arg {
400 struct drm_bo_op_req req;
401 struct drm_bo_arg_rep rep;
406 struct drm_i915_execbuffer {
408 uint32_t num_buffers;
409 struct drm_i915_batchbuffer batch;
410 drm_context_t context; /* for lockless use in the future */
411 struct drm_fence_arg fence_arg;
414 struct drm_i915_gem_init {
416 * Beginning offset in the GTT to be managed by the DRM memory
421 * Ending offset in the GTT to be managed by the DRM memory
427 struct drm_i915_gem_relocation_entry {
429 * Handle of the buffer being pointed to by this relocation entry.
431 * It's appealing to make this be an index into the mm_validate_entry
432 * list to refer to the buffer, but this allows the driver to create
433 * a relocation list for state buffers and not re-write it per
434 * exec using the buffer.
436 uint32_t target_handle;
439 * Value to be added to the offset of the target buffer to make up
440 * the relocation entry.
444 /** Offset in the buffer the relocation entry will be written into */
448 * Offset value of the target buffer that the relocation entry was last
451 * If the buffer has the same offset as last time, we can skip syncing
452 * and writing the relocation. This value is written back out by
453 * the execbuffer ioctl when the relocation is written.
455 uint64_t presumed_offset;
458 * Target memory domains read by this operation.
460 uint32_t read_domains;
463 * Target memory domains written by this operation.
465 * Note that only one domain may be written by the whole
466 * execbuffer operation, so that where there are conflicts,
467 * the application will get -EINVAL back.
469 uint32_t write_domain;
473 * Intel memory domains
475 * Most of these just align with the various caches in
476 * the system and are used to flush and invalidate as
477 * objects end up cached in different domains.
480 /* 0x00000001 is DRM_GEM_DOMAIN_CPU */
481 #define DRM_GEM_DOMAIN_I915_RENDER 0x00000002 /* Render cache, used by 2D and 3D drawing */
482 #define DRM_GEM_DOMAIN_I915_SAMPLER 0x00000004 /* Sampler cache, used by texture engine */
483 #define DRM_GEM_DOMAIN_I915_COMMAND 0x00000008 /* Command queue, used to load batch buffers */
484 #define DRM_GEM_DOMAIN_I915_INSTRUCTION 0x00000010 /* Instruction cache, used by shader programs */
485 #define DRM_GEM_DOMAIN_I915_VERTEX 0x00000020 /* Vertex address cache */
487 struct drm_i915_gem_exec_object {
489 * User's handle for a buffer to be bound into the GTT for this
494 /** List of relocations to be performed on this buffer */
495 uint32_t relocation_count;
496 uint64_t relocs_ptr; /* struct drm_i915_gem_relocation_entry *relocs */
498 /** Required alignment in graphics aperture */
502 * Returned value of the updated offset of the object, for future
503 * presumed_offset writes.
508 struct drm_i915_gem_execbuffer {
510 * List of buffers to be validated with their relocations to be
511 * performend on them.
513 * These buffers must be listed in an order such that all relocations
514 * a buffer is performing refer to buffers that have already appeared
515 * in the validate list.
517 uint64_t buffers_ptr; /* struct drm_i915_gem_validate_entry *buffers */
518 uint32_t buffer_count;
520 /** Offset in the batchbuffer to start execution from. */
521 uint32_t batch_start_offset;
522 /** Bytes used in batchbuffer from batch_start_offset */
526 uint32_t num_cliprects;
527 uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */
530 struct drm_i915_gem_pin {
531 /** Handle of the buffer to be pinned. */
535 /** alignment required within the aperture */
538 /** Returned GTT offset of the buffer. */
542 struct drm_i915_gem_unpin {
543 /** Handle of the buffer to be unpinned. */
548 struct drm_i915_gem_busy {
549 /** Handle of the buffer to check for busy */
552 /** Return busy status (1 if busy, 0 if idle) */
556 #endif /* _I915_DRM_H_ */