1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 /* General customization:
36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
38 #define DRIVER_NAME "i915"
39 #define DRIVER_DESC "Intel Graphics"
40 #define DRIVER_DATE "20070209"
42 #if defined(__linux__)
43 #define I915_HAVE_FENCE
44 #define I915_HAVE_BUFFER
50 * 1.2: Add Power Management
51 * 1.3: Add vblank support
52 * 1.4: Fix cmdbuffer path, add heap destroy
53 * 1.5: Add vblank pipe configuration
54 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
55 * - Support vertical blank on secondary display pipe
56 * 1.8: New ioctl for ARB_Occlusion_Query
57 * 1.9: Usable page flipping and triple buffering
58 * 1.10: Plane/pipe disentangling
59 * 1.11: TTM superioctl
60 * 1.12: TTM relocation optimization
62 #define DRIVER_MAJOR 1
63 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)
64 #define DRIVER_MINOR 12
66 #define DRIVER_MINOR 6
68 #define DRIVER_PATCHLEVEL 0
70 #ifdef I915_HAVE_BUFFER
71 #define I915_MAX_VALIDATE_BUFFERS 4096
74 typedef struct _drm_i915_ring_buffer {
84 } drm_i915_ring_buffer_t;
87 struct mem_block *next;
88 struct mem_block *prev;
91 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
94 typedef struct _drm_i915_vbl_swap {
95 struct list_head head;
96 drm_drawable_t drw_id;
98 unsigned int sequence;
100 } drm_i915_vbl_swap_t;
102 typedef struct drm_i915_private {
103 drm_local_map_t *sarea;
104 drm_local_map_t *mmio_map;
106 drm_i915_sarea_t *sarea_priv;
107 drm_i915_ring_buffer_t ring;
109 drm_dma_handle_t *status_page_dmah;
110 void *hw_status_page;
111 dma_addr_t dma_status_page;
113 unsigned int status_gfx_addr;
114 drm_local_map_t hws_map;
117 int use_mi_batchbuffer_start;
119 wait_queue_head_t irq_queue;
120 atomic_t irq_received;
121 atomic_t irq_emitted;
123 int tex_lru_log_granularity;
124 int allow_batchbuffer;
125 struct mem_block *agp_heap;
126 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
128 DRM_SPINTYPE user_irq_lock;
129 int user_irq_refcount;
131 uint32_t irq_enable_reg;
134 #ifdef I915_HAVE_FENCE
135 uint32_t flush_sequence;
136 uint32_t flush_flags;
137 uint32_t flush_pending;
138 uint32_t saved_flush_status;
140 #ifdef I915_HAVE_BUFFER
142 unsigned int max_validate_buffers;
143 struct mutex cmdbuf_mutex;
146 DRM_SPINTYPE swaps_lock;
147 drm_i915_vbl_swap_t vbl_swaps;
148 unsigned int swaps_pending;
175 u32 savePFIT_PGM_RATIOS;
177 u32 saveBLC_PWM_CTL2;
195 u32 saveVCLK_DIVISOR_VGA0;
196 u32 saveVCLK_DIVISOR_VGA1;
197 u32 saveVCLK_POST_DIV;
210 u32 savePFIT_CONTROL;
211 u32 save_palette_a[256];
212 u32 save_palette_b[256];
213 u32 saveFBC_CFB_BASE;
216 u32 saveFBC_CONTROL2;
226 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
228 } drm_i915_private_t;
230 enum intel_chip_family {
237 extern struct drm_ioctl_desc i915_ioctls[];
238 extern int i915_max_ioctl;
241 extern void i915_kernel_lost_context(struct drm_device * dev);
242 extern int i915_driver_load(struct drm_device *, unsigned long flags);
243 extern int i915_driver_unload(struct drm_device *);
244 extern void i915_driver_lastclose(struct drm_device * dev);
245 extern void i915_driver_preclose(struct drm_device *dev,
246 struct drm_file *file_priv);
247 extern int i915_driver_device_is_agp(struct drm_device * dev);
248 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
250 extern void i915_emit_breadcrumb(struct drm_device *dev);
251 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);
252 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);
253 extern int i915_driver_firstopen(struct drm_device *dev);
256 extern int i915_irq_emit(struct drm_device *dev, void *data,
257 struct drm_file *file_priv);
258 extern int i915_irq_wait(struct drm_device *dev, void *data,
259 struct drm_file *file_priv);
261 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
262 extern void i915_driver_irq_preinstall(struct drm_device * dev);
263 extern int i915_driver_irq_postinstall(struct drm_device * dev);
264 extern void i915_driver_irq_uninstall(struct drm_device * dev);
265 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
266 struct drm_file *file_priv);
267 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
268 struct drm_file *file_priv);
269 extern int i915_emit_irq(struct drm_device * dev);
270 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
271 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
272 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
273 extern int i915_vblank_swap(struct drm_device *dev, void *data,
274 struct drm_file *file_priv);
275 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
276 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
279 extern int i915_mem_alloc(struct drm_device *dev, void *data,
280 struct drm_file *file_priv);
281 extern int i915_mem_free(struct drm_device *dev, void *data,
282 struct drm_file *file_priv);
283 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
284 struct drm_file *file_priv);
285 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
286 struct drm_file *file_priv);
287 extern void i915_mem_takedown(struct mem_block **heap);
288 extern void i915_mem_release(struct drm_device * dev,
289 struct drm_file *file_priv,
290 struct mem_block *heap);
291 #ifdef I915_HAVE_FENCE
295 extern void i915_fence_handler(struct drm_device *dev);
296 extern int i915_fence_emit_sequence(struct drm_device *dev, uint32_t class,
299 uint32_t *native_type);
300 extern void i915_poke_flush(struct drm_device *dev, uint32_t class);
301 extern int i915_fence_has_irq(struct drm_device *dev, uint32_t class, uint32_t flags);
304 #ifdef I915_HAVE_BUFFER
306 extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);
307 extern int i915_fence_type(struct drm_buffer_object *bo, uint32_t *fclass,
309 extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
310 extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
311 struct drm_mem_type_manager *man);
312 extern uint64_t i915_evict_flags(struct drm_buffer_object *bo);
313 extern int i915_move(struct drm_buffer_object *bo, int evict,
314 int no_wait, struct drm_bo_mem_reg *new_mem);
315 void i915_flush_ttm(struct drm_ttm *ttm);
319 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
320 extern void intel_init_chipset_flush_compat(struct drm_device *dev);
321 extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
325 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
326 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
327 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
328 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
330 #define I915_VERBOSE 0
332 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
335 #define BEGIN_LP_RING(n) do { \
337 DRM_DEBUG("BEGIN_LP_RING(%d)\n", \
339 if (dev_priv->ring.space < (n)*4) \
340 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
342 outring = dev_priv->ring.tail; \
343 ringmask = dev_priv->ring.tail_mask; \
344 virt = dev_priv->ring.virtual_start; \
347 #define OUT_RING(n) do { \
348 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
349 *(volatile unsigned int *)(virt + outring) = (n); \
352 outring &= ringmask; \
355 #define ADVANCE_LP_RING() do { \
356 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
357 dev_priv->ring.tail = outring; \
358 dev_priv->ring.space -= outcount * 4; \
359 I915_WRITE(LP_RING + RING_TAIL, outring); \
362 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
364 /* Extended config space */
369 #define VGA_ST01_MDA 0x3ba
370 #define VGA_ST01_CGA 0x3da
372 #define VGA_MSR_WRITE 0x3c2
373 #define VGA_MSR_READ 0x3cc
374 #define VGA_MSR_MEM_EN (1<<1)
375 #define VGA_MSR_CGA_MODE (1<<0)
377 #define VGA_SR_INDEX 0x3c4
378 #define VGA_SR_DATA 0x3c5
380 #define VGA_AR_INDEX 0x3c0
381 #define VGA_AR_VID_EN (1<<5)
382 #define VGA_AR_DATA_WRITE 0x3c0
383 #define VGA_AR_DATA_READ 0x3c1
385 #define VGA_GR_INDEX 0x3ce
386 #define VGA_GR_DATA 0x3cf
388 #define VGA_GR_MEM_READ_MODE_SHIFT 3
389 #define VGA_GR_MEM_READ_MODE_PLANE 1
391 #define VGA_GR_MEM_MODE_MASK 0xc
392 #define VGA_GR_MEM_MODE_SHIFT 2
393 #define VGA_GR_MEM_A0000_AFFFF 0
394 #define VGA_GR_MEM_A0000_BFFFF 1
395 #define VGA_GR_MEM_B0000_B7FFF 2
396 #define VGA_GR_MEM_B0000_BFFFF 3
398 #define VGA_DACMASK 0x3c6
399 #define VGA_DACRX 0x3c7
400 #define VGA_DACWX 0x3c8
401 #define VGA_DACDATA 0x3c9
403 #define VGA_CR_INDEX_MDA 0x3b4
404 #define VGA_CR_DATA_MDA 0x3b5
405 #define VGA_CR_INDEX_CGA 0x3d4
406 #define VGA_CR_DATA_CGA 0x3d5
408 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
409 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
410 #define CMD_REPORT_HEAD (7<<23)
411 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
412 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
414 #define CMD_MI_FLUSH (0x04 << 23)
415 #define MI_NO_WRITE_FLUSH (1 << 2)
416 #define MI_READ_FLUSH (1 << 0)
417 #define MI_EXE_FLUSH (1 << 1)
418 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
419 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
421 /* Packet to load a register value from the ring/batch command stream:
423 #define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1)
425 #define BB1_START_ADDR_MASK (~0x7)
426 #define BB1_PROTECTED (1<<0)
427 #define BB1_UNPROTECTED (0<<0)
428 #define BB2_END_ADDR_MASK (~0x7)
430 /* Framebuffer compression */
431 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
432 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
433 #define FBC_CONTROL 0x03208
434 #define FBC_CTL_EN (1<<31)
435 #define FBC_CTL_PERIODIC (1<<30)
436 #define FBC_CTL_INTERVAL_SHIFT (16)
437 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
438 #define FBC_CTL_STRIDE_SHIFT (5)
439 #define FBC_CTL_FENCENO (1<<0)
440 #define FBC_COMMAND 0x0320c
441 #define FBC_CMD_COMPRESS (1<<0)
442 #define FBC_STATUS 0x03210
443 #define FBC_STAT_COMPRESSING (1<<31)
444 #define FBC_STAT_COMPRESSED (1<<30)
445 #define FBC_STAT_MODIFIED (1<<29)
446 #define FBC_STAT_CURRENT_LINE (1<<0)
447 #define FBC_CONTROL2 0x03214
448 #define FBC_CTL_FENCE_DBL (0<<4)
449 #define FBC_CTL_IDLE_IMM (0<<2)
450 #define FBC_CTL_IDLE_FULL (1<<2)
451 #define FBC_CTL_IDLE_LINE (2<<2)
452 #define FBC_CTL_IDLE_DEBUG (3<<2)
453 #define FBC_CTL_CPU_FENCE (1<<1)
454 #define FBC_CTL_PLANEA (0<<0)
455 #define FBC_CTL_PLANEB (1<<0)
456 #define FBC_FENCE_OFF 0x0321b
458 #define FBC_LL_SIZE (1536)
459 #define FBC_LL_PAD (32)
463 #define USER_INT_FLAG (1<<1)
464 #define VSYNC_PIPEB_FLAG (1<<5)
465 #define VSYNC_PIPEA_FLAG (1<<7)
466 #define HWB_OOM_FLAG (1<<13) /* binner out of memory */
468 #define I915REG_HWSTAM 0x02098
469 #define I915REG_INT_IDENTITY_R 0x020a4
470 #define I915REG_INT_MASK_R 0x020a8
471 #define I915REG_INT_ENABLE_R 0x020a0
472 #define I915REG_INSTPM 0x020c0
474 #define PIPEADSL 0x70000
475 #define PIPEBDSL 0x71000
477 #define I915REG_PIPEASTAT 0x70024
478 #define I915REG_PIPEBSTAT 0x71024
480 * The two pipe frame counter registers are not synchronized, so
481 * reading a stable value is somewhat tricky. The following code
485 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
486 * PIPE_FRAME_HIGH_SHIFT;
487 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
488 * PIPE_FRAME_LOW_SHIFT);
489 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
490 * PIPE_FRAME_HIGH_SHIFT);
491 * } while (high1 != high2);
492 * frame = (high1 << 8) | low1;
494 #define PIPEAFRAMEHIGH 0x70040
495 #define PIPEBFRAMEHIGH 0x71040
496 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
497 #define PIPE_FRAME_HIGH_SHIFT 0
498 #define PIPEAFRAMEPIXEL 0x70044
499 #define PIPEBFRAMEPIXEL 0x71044
501 #define PIPE_FRAME_LOW_MASK 0xff000000
502 #define PIPE_FRAME_LOW_SHIFT 24
504 * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
505 * and is 24 bits wide.
507 #define PIPE_PIXEL_MASK 0x00ffffff
508 #define PIPE_PIXEL_SHIFT 0
510 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
511 #define I915_VBLANK_CLEAR (1UL<<1)
513 #define SRX_INDEX 0x3c4
514 #define SRX_DATA 0x3c5
516 #define SR01_SCREEN_OFF (1<<5)
519 #define PPCR_ON (1<<0)
522 #define DVOB_ON (1<<31)
524 #define DVOC_ON (1<<31)
526 #define LVDS_ON (1<<31)
529 #define ADPA_DPMS_MASK (~(3<<10))
530 #define ADPA_DPMS_ON (0<<10)
531 #define ADPA_DPMS_SUSPEND (1<<10)
532 #define ADPA_DPMS_STANDBY (2<<10)
533 #define ADPA_DPMS_OFF (3<<10)
536 #define LP_RING 0x2030
537 #define HP_RING 0x2040
538 /* The binner has its own ring buffer:
540 #define HWB_RING 0x2400
542 #define RING_TAIL 0x00
543 #define TAIL_ADDR 0x001FFFF8
544 #define RING_HEAD 0x04
545 #define HEAD_WRAP_COUNT 0xFFE00000
546 #define HEAD_WRAP_ONE 0x00200000
547 #define HEAD_ADDR 0x001FFFFC
548 #define RING_START 0x08
549 #define START_ADDR 0x0xFFFFF000
550 #define RING_LEN 0x0C
551 #define RING_NR_PAGES 0x001FF000
552 #define RING_REPORT_MASK 0x00000006
553 #define RING_REPORT_64K 0x00000002
554 #define RING_REPORT_128K 0x00000004
555 #define RING_NO_REPORT 0x00000000
556 #define RING_VALID_MASK 0x00000001
557 #define RING_VALID 0x00000001
558 #define RING_INVALID 0x00000000
560 /* Instruction parser error reg:
564 /* Scratch pad debug 0 reg:
572 /* Secondary DMA fetch address debug reg:
574 #define DMA_FADD_S 0x20d4
577 * - Manipulating render cache behaviour is central
578 * to the concept of zone rendering, tuning this reg can help avoid
579 * unnecessary render cache reads and even writes (for z/stencil)
580 * at beginning and end of scene.
582 * - To change a bit, write to this reg with a mask bit set and the
583 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
585 #define Cache_Mode_0 0x2120
586 #define CM0_MASK_SHIFT 16
587 #define CM0_IZ_OPT_DISABLE (1<<6)
588 #define CM0_ZR_OPT_DISABLE (1<<5)
589 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
590 #define CM0_COLOR_EVICT_DISABLE (1<<3)
591 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
592 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
595 /* Graphics flush control. A CPU write flushes the GWB of all writes.
596 * The data is discarded.
598 #define GFX_FLSH_CNTL 0x2170
600 /* Binner control. Defines the location of the bin pointer list:
602 #define BINCTL 0x2420
603 #define BC_MASK (1 << 9)
605 /* Binned scene info.
607 #define BINSCENE 0x2428
608 #define BS_OP_LOAD (1 << 8)
609 #define BS_MASK (1 << 22)
611 /* Bin command parser debug reg:
615 /* Bin memory control debug reg:
619 /* Bin data cache debug reg:
623 /* Binner pointer cache debug reg:
627 /* Binner scratch pad debug reg:
629 #define BINSKPD 0x24f0
631 /* HWB scratch pad debug reg:
633 #define HWBSKPD 0x24f4
635 /* Binner memory pool reg:
637 #define BMP_BUFFER 0x2430
638 #define BMP_PAGE_SIZE_4K (0 << 10)
639 #define BMP_BUFFER_SIZE_SHIFT 1
640 #define BMP_ENABLE (1 << 0)
642 /* Get/put memory from the binner memory pool:
644 #define BMP_GET 0x2438
645 #define BMP_PUT 0x2440
646 #define BMP_OFFSET_SHIFT 5
650 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
652 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
653 #define SC_UPDATE_SCISSOR (0x1<<1)
654 #define SC_ENABLE_MASK (0x1<<0)
655 #define SC_ENABLE (0x1<<0)
657 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
659 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
660 #define SCI_YMIN_MASK (0xffff<<16)
661 #define SCI_XMIN_MASK (0xffff<<0)
662 #define SCI_YMAX_MASK (0xffff<<16)
663 #define SCI_XMAX_MASK (0xffff<<0)
665 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
666 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
667 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
668 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
669 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
670 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
671 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
673 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
675 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
676 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
677 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
678 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
680 #define MI_BATCH_BUFFER ((0x30<<23)|1)
681 #define MI_BATCH_BUFFER_START (0x31<<23)
682 #define MI_BATCH_BUFFER_END (0xA<<23)
683 #define MI_BATCH_NON_SECURE (1)
685 #define MI_BATCH_NON_SECURE_I965 (1<<8)
687 #define MI_WAIT_FOR_EVENT ((0x3<<23))
688 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
689 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
690 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
692 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
694 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
695 #define ASYNC_FLIP (1<<22)
696 #define DISPLAY_PLANE_A (0<<20)
697 #define DISPLAY_PLANE_B (1<<20)
700 #define DSPACNTR 0x70180
701 #define DSPBCNTR 0x71180
702 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
704 /* Define the region of interest for the binner:
706 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
708 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
710 #define BREADCRUMB_BITS 31
711 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
713 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
714 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
716 #define BLC_PWM_CTL 0x61254
717 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
719 #define BLC_PWM_CTL2 0x61250
721 * This is the most significant 15 bits of the number of backlight cycles in a
722 * complete cycle of the modulated backlight control.
724 * The actual value is this field multiplied by two.
726 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
727 #define BLM_LEGACY_MODE (1 << 16)
729 * This is the number of cycles out of the backlight modulation cycle for which
730 * the backlight is on.
732 * This field must be no greater than the number of cycles in the complete
733 * backlight modulation cycle.
735 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
736 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
738 #define I915_GCFGC 0xf0
739 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
740 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
741 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
742 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
744 #define I855_HPLLCC 0xc0
745 #define I855_CLOCK_CONTROL_MASK (3 << 0)
746 #define I855_CLOCK_133_200 (0 << 0)
747 #define I855_CLOCK_100_200 (1 << 0)
748 #define I855_CLOCK_100_133 (2 << 0)
749 #define I855_CLOCK_166_250 (3 << 0)
753 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
754 #define VCLK2_VCO_N 0x600a
755 #define VCLK2_VCO_DIV_SEL 0x6012
757 #define VCLK_DIVISOR_VGA0 0x6000
758 #define VCLK_DIVISOR_VGA1 0x6004
759 #define VCLK_POST_DIV 0x6010
760 /** Selects a post divisor of 4 instead of 2. */
761 # define VGA1_PD_P2_DIV_4 (1 << 15)
762 /** Overrides the p2 post divisor field */
763 # define VGA1_PD_P1_DIV_2 (1 << 13)
764 # define VGA1_PD_P1_SHIFT 8
765 /** P1 value is 2 greater than this field */
766 # define VGA1_PD_P1_MASK (0x1f << 8)
767 /** Selects a post divisor of 4 instead of 2. */
768 # define VGA0_PD_P2_DIV_4 (1 << 7)
769 /** Overrides the p2 post divisor field */
770 # define VGA0_PD_P1_DIV_2 (1 << 5)
771 # define VGA0_PD_P1_SHIFT 0
772 /** P1 value is 2 greater than this field */
773 # define VGA0_PD_P1_MASK (0x1f << 0)
775 /* I830 CRTC registers */
776 #define HTOTAL_A 0x60000
777 #define HBLANK_A 0x60004
778 #define HSYNC_A 0x60008
779 #define VTOTAL_A 0x6000c
780 #define VBLANK_A 0x60010
781 #define VSYNC_A 0x60014
782 #define PIPEASRC 0x6001c
783 #define BCLRPAT_A 0x60020
784 #define VSYNCSHIFT_A 0x60028
786 #define HTOTAL_B 0x61000
787 #define HBLANK_B 0x61004
788 #define HSYNC_B 0x61008
789 #define VTOTAL_B 0x6100c
790 #define VBLANK_B 0x61010
791 #define VSYNC_B 0x61014
792 #define PIPEBSRC 0x6101c
793 #define BCLRPAT_B 0x61020
794 #define VSYNCSHIFT_B 0x61028
796 #define HACTIVE_MASK 0x00000fff
797 #define VTOTAL_MASK 0x00001fff
798 #define VTOTAL_SHIFT 16
799 #define VACTIVE_MASK 0x00000fff
800 #define VBLANK_END_MASK 0x00001fff
801 #define VBLANK_END_SHIFT 16
802 #define VBLANK_START_MASK 0x00001fff
804 #define PP_STATUS 0x61200
805 # define PP_ON (1 << 31)
807 * Indicates that all dependencies of the panel are on:
811 * - LVDS/DVOB/DVOC on
813 # define PP_READY (1 << 30)
814 # define PP_SEQUENCE_NONE (0 << 28)
815 # define PP_SEQUENCE_ON (1 << 28)
816 # define PP_SEQUENCE_OFF (2 << 28)
817 # define PP_SEQUENCE_MASK 0x30000000
818 #define PP_CONTROL 0x61204
819 # define POWER_TARGET_ON (1 << 0)
821 #define LVDSPP_ON 0x61208
822 #define LVDSPP_OFF 0x6120c
823 #define PP_CYCLE 0x61210
825 #define PFIT_CONTROL 0x61230
826 # define PFIT_ENABLE (1 << 31)
827 # define PFIT_PIPE_MASK (3 << 29)
828 # define PFIT_PIPE_SHIFT 29
829 # define VERT_INTERP_DISABLE (0 << 10)
830 # define VERT_INTERP_BILINEAR (1 << 10)
831 # define VERT_INTERP_MASK (3 << 10)
832 # define VERT_AUTO_SCALE (1 << 9)
833 # define HORIZ_INTERP_DISABLE (0 << 6)
834 # define HORIZ_INTERP_BILINEAR (1 << 6)
835 # define HORIZ_INTERP_MASK (3 << 6)
836 # define HORIZ_AUTO_SCALE (1 << 5)
837 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
839 #define PFIT_PGM_RATIOS 0x61234
840 # define PFIT_VERT_SCALE_MASK 0xfff00000
841 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
843 #define PFIT_AUTO_RATIOS 0x61238
846 #define DPLL_A 0x06014
847 #define DPLL_B 0x06018
848 # define DPLL_VCO_ENABLE (1 << 31)
849 # define DPLL_DVO_HIGH_SPEED (1 << 30)
850 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
851 # define DPLL_VGA_MODE_DIS (1 << 28)
852 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
853 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
854 # define DPLL_MODE_MASK (3 << 26)
855 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
856 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
857 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
858 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
859 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
860 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
862 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
863 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
865 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
867 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
868 * this field (only one bit may be set).
870 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
871 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
872 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
873 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
874 # define PLL_REF_INPUT_DREFCLK (0 << 13)
875 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
876 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
877 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
878 # define PLL_REF_INPUT_MASK (3 << 13)
879 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
881 * Parallel to Serial Load Pulse phase selection.
882 * Selects the phase for the 10X DPLL clock for the PCIe
883 * digital display port. The range is 4 to 13; 10 or more
884 * is just a flip delay. The default is 6
886 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
887 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
890 * SDVO multiplier for 945G/GM. Not used on 965.
892 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
894 # define SDVO_MULTIPLIER_MASK 0x000000ff
895 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
896 # define SDVO_MULTIPLIER_SHIFT_VGA 0
898 /** @defgroup DPLL_MD
901 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
902 #define DPLL_A_MD 0x0601c
903 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
904 #define DPLL_B_MD 0x06020
906 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
908 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
910 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
911 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
912 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
913 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
914 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
916 * SDVO/UDI pixel multiplier.
918 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
919 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
920 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
921 * dummy bytes in the datastream at an increased clock rate, with both sides of
922 * the link knowing how many bytes are fill.
924 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
925 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
926 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
927 * through an SDVO command.
929 * This register field has values of multiplication factor minus 1, with
930 * a maximum multiplier of 5 for SDVO.
932 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
933 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
934 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
935 * This best be set to the default value (3) or the CRT won't work. No,
936 * I don't entirely understand what this does...
938 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
939 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
942 #define DPLL_TEST 0x606c
943 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
944 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
945 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
946 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
947 # define DPLLB_TEST_N_BYPASS (1 << 19)
948 # define DPLLB_TEST_M_BYPASS (1 << 18)
949 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
950 # define DPLLA_TEST_N_BYPASS (1 << 3)
951 # define DPLLA_TEST_M_BYPASS (1 << 2)
952 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
955 #define ADPA_DAC_ENABLE (1<<31)
956 #define ADPA_DAC_DISABLE 0
957 #define ADPA_PIPE_SELECT_MASK (1<<30)
958 #define ADPA_PIPE_A_SELECT 0
959 #define ADPA_PIPE_B_SELECT (1<<30)
960 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
961 #define ADPA_SETS_HVPOLARITY 0
962 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
963 #define ADPA_VSYNC_CNTL_ENABLE 0
964 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
965 #define ADPA_HSYNC_CNTL_ENABLE 0
966 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
967 #define ADPA_VSYNC_ACTIVE_LOW 0
968 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
969 #define ADPA_HSYNC_ACTIVE_LOW 0
975 # define FP_N_DIV_MASK 0x003f0000
976 # define FP_N_DIV_SHIFT 16
977 # define FP_M1_DIV_MASK 0x00003f00
978 # define FP_M1_DIV_SHIFT 8
979 # define FP_M2_DIV_MASK 0x0000003f
980 # define FP_M2_DIV_SHIFT 0
983 #define PORT_HOTPLUG_EN 0x61110
984 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
985 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
986 # define TV_HOTPLUG_INT_EN (1 << 18)
987 # define CRT_HOTPLUG_INT_EN (1 << 9)
988 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
990 #define PORT_HOTPLUG_STAT 0x61114
991 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
992 # define TV_HOTPLUG_INT_STATUS (1 << 10)
993 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
994 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
995 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
996 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
997 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
998 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1000 #define SDVOB 0x61140
1001 #define SDVOC 0x61160
1002 #define SDVO_ENABLE (1 << 31)
1003 #define SDVO_PIPE_B_SELECT (1 << 30)
1004 #define SDVO_STALL_SELECT (1 << 29)
1005 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1007 * 915G/GM SDVO pixel multiplier.
1009 * Programmed value is multiplier - 1, up to 5x.
1011 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1013 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1014 #define SDVO_PORT_MULTIPLY_SHIFT 23
1015 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1016 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1017 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1018 #define SDVOC_GANG_MODE (1 << 16)
1019 #define SDVO_BORDER_ENABLE (1 << 7)
1020 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1021 #define SDVO_DETECTED (1 << 2)
1022 /* Bits to be preserved when writing */
1023 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
1024 #define SDVOC_PRESERVE_MASK (1 << 17)
1030 * This register controls the LVDS output enable, pipe selection, and data
1033 * All of the clock/data pairs are force powered down by power sequencing.
1035 #define LVDS 0x61180
1037 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1038 * the DPLL semantics change when the LVDS is assigned to that pipe.
1040 # define LVDS_PORT_EN (1 << 31)
1041 /** Selects pipe B for LVDS data. Must be set on pre-965. */
1042 # define LVDS_PIPEB_SELECT (1 << 30)
1045 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1048 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1049 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1050 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1052 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1053 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1056 # define LVDS_A3_POWER_MASK (3 << 6)
1057 # define LVDS_A3_POWER_DOWN (0 << 6)
1058 # define LVDS_A3_POWER_UP (3 << 6)
1060 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1063 # define LVDS_CLKB_POWER_MASK (3 << 4)
1064 # define LVDS_CLKB_POWER_DOWN (0 << 4)
1065 # define LVDS_CLKB_POWER_UP (3 << 4)
1068 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1069 * setting for whether we are in dual-channel mode. The B3 pair will
1070 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1072 # define LVDS_B0B3_POWER_MASK (3 << 2)
1073 # define LVDS_B0B3_POWER_DOWN (0 << 2)
1074 # define LVDS_B0B3_POWER_UP (3 << 2)
1076 #define PIPEACONF 0x70008
1077 #define PIPEACONF_ENABLE (1<<31)
1078 #define PIPEACONF_DISABLE 0
1079 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1080 #define I965_PIPECONF_ACTIVE (1<<30)
1081 #define PIPEACONF_SINGLE_WIDE 0
1082 #define PIPEACONF_PIPE_UNLOCKED 0
1083 #define PIPEACONF_PIPE_LOCKED (1<<25)
1084 #define PIPEACONF_PALETTE 0
1085 #define PIPEACONF_GAMMA (1<<24)
1086 #define PIPECONF_FORCE_BORDER (1<<25)
1087 #define PIPECONF_PROGRESSIVE (0 << 21)
1088 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1089 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1091 #define PIPEBCONF 0x71008
1092 #define PIPEBCONF_ENABLE (1<<31)
1093 #define PIPEBCONF_DISABLE 0
1094 #define PIPEBCONF_DOUBLE_WIDE (1<<30)
1095 #define PIPEBCONF_DISABLE 0
1096 #define PIPEBCONF_GAMMA (1<<24)
1097 #define PIPEBCONF_PALETTE 0
1099 #define PIPEBGCMAXRED 0x71010
1100 #define PIPEBGCMAXGREEN 0x71014
1101 #define PIPEBGCMAXBLUE 0x71018
1102 #define PIPEBSTAT 0x71024
1103 #define PIPEBFRAMEHIGH 0x71040
1104 #define PIPEBFRAMEPIXEL 0x71044
1106 #define DSPACNTR 0x70180
1107 #define DSPBCNTR 0x71180
1108 #define DISPLAY_PLANE_ENABLE (1<<31)
1109 #define DISPLAY_PLANE_DISABLE 0
1110 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1111 #define DISPPLANE_GAMMA_DISABLE 0
1112 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1113 #define DISPPLANE_8BPP (0x2<<26)
1114 #define DISPPLANE_15_16BPP (0x4<<26)
1115 #define DISPPLANE_16BPP (0x5<<26)
1116 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1117 #define DISPPLANE_32BPP (0x7<<26)
1118 #define DISPPLANE_STEREO_ENABLE (1<<25)
1119 #define DISPPLANE_STEREO_DISABLE 0
1120 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1121 #define DISPPLANE_SEL_PIPE_A 0
1122 #define DISPPLANE_SEL_PIPE_B (1<<24)
1123 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1124 #define DISPPLANE_SRC_KEY_DISABLE 0
1125 #define DISPPLANE_LINE_DOUBLE (1<<20)
1126 #define DISPPLANE_NO_LINE_DOUBLE 0
1127 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1128 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1130 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1131 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1132 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1133 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1135 #define DSPABASE 0x70184
1136 #define DSPASTRIDE 0x70188
1138 #define DSPBBASE 0x71184
1139 #define DSPBADDR DSPBBASE
1140 #define DSPBSTRIDE 0x71188
1142 #define DSPAKEYVAL 0x70194
1143 #define DSPAKEYMASK 0x70198
1145 #define DSPAPOS 0x7018C /* reserved */
1146 #define DSPASIZE 0x70190
1147 #define DSPBPOS 0x7118C
1148 #define DSPBSIZE 0x71190
1150 #define DSPASURF 0x7019C
1151 #define DSPATILEOFF 0x701A4
1153 #define DSPBSURF 0x7119C
1154 #define DSPBTILEOFF 0x711A4
1156 #define VGACNTRL 0x71400
1157 # define VGA_DISP_DISABLE (1 << 31)
1158 # define VGA_2X_MODE (1 << 30)
1159 # define VGA_PIPE_B_SELECT (1 << 29)
1162 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1163 * of video memory available to the BIOS in SWF1.
1166 #define SWF0 0x71410
1169 * 855 scratch registers.
1171 #define SWF10 0x70410
1173 #define SWF30 0x72414
1176 * Overlay registers. These are overlay registers accessed via MMIO.
1177 * Those loaded via the overlay register page are defined in i830_video.c.
1179 #define OVADD 0x30000
1181 #define DOVSTA 0x30008
1182 #define OC_BUF (0x3<<20)
1184 #define OGAMC5 0x30010
1185 #define OGAMC4 0x30014
1186 #define OGAMC3 0x30018
1187 #define OGAMC2 0x3001c
1188 #define OGAMC1 0x30020
1189 #define OGAMC0 0x30024
1193 #define PALETTE_A 0x0a000
1194 #define PALETTE_B 0x0a800
1196 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1197 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1198 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1199 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
1200 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1202 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
1203 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1204 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1205 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2)
1207 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1208 (dev)->pci_device == 0x2982 || \
1209 (dev)->pci_device == 0x2992 || \
1210 (dev)->pci_device == 0x29A2 || \
1211 (dev)->pci_device == 0x2A02 || \
1212 (dev)->pci_device == 0x2A12 || \
1213 (dev)->pci_device == 0x2A42)
1215 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1217 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1219 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1220 (dev)->pci_device == 0x29B2 || \
1221 (dev)->pci_device == 0x29D2)
1223 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1224 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1226 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1227 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1229 #define PRIMARY_RINGBUFFER_SIZE (128*1024)