1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 /* General customization:
36 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
38 #define DRIVER_NAME "i915"
39 #define DRIVER_DESC "Intel Graphics"
40 #define DRIVER_DATE "20080312"
42 #if defined(__linux__)
43 #define I915_HAVE_FENCE
44 #define I915_HAVE_BUFFER
50 * 1.2: Add Power Management
51 * 1.3: Add vblank support
52 * 1.4: Fix cmdbuffer path, add heap destroy
53 * 1.5: Add vblank pipe configuration
54 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
55 * - Support vertical blank on secondary display pipe
56 * 1.8: New ioctl for ARB_Occlusion_Query
57 * 1.9: Usable page flipping and triple buffering
58 * 1.10: Plane/pipe disentangling
59 * 1.11: TTM superioctl
60 * 1.12: TTM relocation optimization
62 #define DRIVER_MAJOR 1
63 #if defined(I915_HAVE_FENCE) && defined(I915_HAVE_BUFFER)
64 #define DRIVER_MINOR 13
66 #define DRIVER_MINOR 6
68 #define DRIVER_PATCHLEVEL 0
70 #ifdef I915_HAVE_BUFFER
71 #define I915_MAX_VALIDATE_BUFFERS 4096
72 struct drm_i915_validate_buffer;
75 typedef struct _drm_i915_ring_buffer {
85 } drm_i915_ring_buffer_t;
88 struct mem_block *next;
89 struct mem_block *prev;
92 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
95 typedef struct _drm_i915_vbl_swap {
96 struct list_head head;
97 drm_drawable_t drw_id;
99 unsigned int sequence;
101 } drm_i915_vbl_swap_t;
103 typedef struct drm_i915_private {
104 drm_local_map_t *sarea;
105 drm_local_map_t *mmio_map;
107 drm_i915_sarea_t *sarea_priv;
108 drm_i915_ring_buffer_t ring;
110 drm_dma_handle_t *status_page_dmah;
111 void *hw_status_page;
112 dma_addr_t dma_status_page;
114 unsigned int status_gfx_addr;
115 drm_local_map_t hws_map;
118 int use_mi_batchbuffer_start;
120 wait_queue_head_t irq_queue;
121 atomic_t irq_received;
122 atomic_t irq_emitted;
124 int tex_lru_log_granularity;
125 int allow_batchbuffer;
126 struct mem_block *agp_heap;
127 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
129 DRM_SPINTYPE user_irq_lock;
130 int user_irq_refcount;
132 uint32_t irq_enable_reg;
135 #ifdef I915_HAVE_FENCE
136 uint32_t flush_sequence;
137 uint32_t flush_flags;
138 uint32_t flush_pending;
139 uint32_t saved_flush_status;
141 #ifdef I915_HAVE_BUFFER
143 unsigned int max_validate_buffers;
144 struct mutex cmdbuf_mutex;
145 struct drm_i915_validate_buffer *val_bufs;
148 DRM_SPINTYPE swaps_lock;
149 drm_i915_vbl_swap_t vbl_swaps;
150 unsigned int swaps_pending;
153 struct drm_buffer_object *sarea_bo;
154 struct drm_bo_kmap_obj sarea_kmap;
183 u32 savePFIT_PGM_RATIOS;
185 u32 saveBLC_PWM_CTL2;
204 u32 saveVCLK_DIVISOR_VGA0;
205 u32 saveVCLK_DIVISOR_VGA1;
206 u32 saveVCLK_POST_DIV;
219 u32 savePFIT_CONTROL;
220 u32 save_palette_a[256];
221 u32 save_palette_b[256];
222 u32 saveFBC_CFB_BASE;
225 u32 saveFBC_CONTROL2;
229 u32 saveCACHE_MODE_0;
231 u32 saveDSPCLK_GATE_D;
232 u32 saveMI_ARB_STATE;
242 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
246 struct drm_memrange gtt_space;
248 } drm_i915_private_t;
250 enum intel_chip_family {
257 /** driver private structure attached to each drm_gem_object */
258 struct drm_i915_gem_object {
259 /** Current space allocated to this object in the GTT, if any. */
260 struct drm_memrange_node *gtt_space;
262 /** AGP memory structure for our GTT binding. */
263 DRM_AGP_MEM *agp_mem;
265 struct page **page_list;
268 * Current offset of the object in GTT space.
270 * This is the same as gtt_space->start
274 /** Boolean whether this object has a valid gtt offset. */
277 /** How many users have pinned this object in GTT space */
281 extern struct drm_ioctl_desc i915_ioctls[];
282 extern int i915_max_ioctl;
285 extern void i915_kernel_lost_context(struct drm_device * dev);
286 extern int i915_driver_load(struct drm_device *, unsigned long flags);
287 extern int i915_driver_unload(struct drm_device *);
288 extern void i915_driver_lastclose(struct drm_device * dev);
289 extern void i915_driver_preclose(struct drm_device *dev,
290 struct drm_file *file_priv);
291 extern int i915_driver_device_is_agp(struct drm_device * dev);
292 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
294 extern void i915_emit_breadcrumb(struct drm_device *dev);
295 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync);
296 extern int i915_emit_mi_flush(struct drm_device *dev, uint32_t flush);
297 extern int i915_driver_firstopen(struct drm_device *dev);
298 extern int i915_dispatch_batchbuffer(struct drm_device * dev,
299 drm_i915_batchbuffer_t * batch);
300 extern int i915_quiescent(struct drm_device *dev);
303 extern int i915_irq_emit(struct drm_device *dev, void *data,
304 struct drm_file *file_priv);
305 extern int i915_irq_wait(struct drm_device *dev, void *data,
306 struct drm_file *file_priv);
308 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
309 extern void i915_driver_irq_preinstall(struct drm_device * dev);
310 extern int i915_driver_irq_postinstall(struct drm_device * dev);
311 extern void i915_driver_irq_uninstall(struct drm_device * dev);
312 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
313 struct drm_file *file_priv);
314 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
315 struct drm_file *file_priv);
316 extern int i915_emit_irq(struct drm_device * dev);
317 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
318 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
319 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
320 extern int i915_vblank_swap(struct drm_device *dev, void *data,
321 struct drm_file *file_priv);
322 extern void i915_user_irq_on(drm_i915_private_t *dev_priv);
323 extern void i915_user_irq_off(drm_i915_private_t *dev_priv);
326 extern int i915_mem_alloc(struct drm_device *dev, void *data,
327 struct drm_file *file_priv);
328 extern int i915_mem_free(struct drm_device *dev, void *data,
329 struct drm_file *file_priv);
330 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
331 struct drm_file *file_priv);
332 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
333 struct drm_file *file_priv);
334 extern void i915_mem_takedown(struct mem_block **heap);
335 extern void i915_mem_release(struct drm_device * dev,
336 struct drm_file *file_priv,
337 struct mem_block *heap);
338 #ifdef I915_HAVE_FENCE
340 extern void i915_fence_handler(struct drm_device *dev);
341 extern void i915_invalidate_reported_sequence(struct drm_device *dev);
345 #ifdef I915_HAVE_BUFFER
347 extern struct drm_ttm_backend *i915_create_ttm_backend_entry(struct drm_device *dev);
348 extern int i915_fence_type(struct drm_buffer_object *bo, uint32_t *fclass,
350 extern int i915_invalidate_caches(struct drm_device *dev, uint64_t buffer_flags);
351 extern int i915_init_mem_type(struct drm_device *dev, uint32_t type,
352 struct drm_mem_type_manager *man);
353 extern uint64_t i915_evict_flags(struct drm_buffer_object *bo);
354 extern int i915_move(struct drm_buffer_object *bo, int evict,
355 int no_wait, struct drm_bo_mem_reg *new_mem);
356 void i915_flush_ttm(struct drm_ttm *ttm);
358 int i915_execbuffer(struct drm_device *dev, void *data,
359 struct drm_file *file_priv);
361 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
362 struct drm_file *file_priv);
363 int i915_gem_execbuffer(struct drm_device *dev, void *data,
364 struct drm_file *file_priv);
365 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
366 struct drm_file *file_priv);
367 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
368 struct drm_file *file_priv);
369 int i915_gem_init_object(struct drm_device *dev, struct drm_gem_object *obj);
370 void i915_gem_free_object(struct drm_device *dev, struct drm_gem_object *obj);
375 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
376 extern void intel_init_chipset_flush_compat(struct drm_device *dev);
377 extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
381 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
382 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
383 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
384 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
386 #define I915_VERBOSE 0
388 #define RING_LOCALS unsigned int outring, ringmask, outcount; \
391 #define BEGIN_LP_RING(n) do { \
393 DRM_DEBUG("BEGIN_LP_RING(%d)\n", \
395 if (dev_priv->ring.space < (n)*4) \
396 i915_wait_ring(dev, (n)*4, __FUNCTION__); \
398 outring = dev_priv->ring.tail; \
399 ringmask = dev_priv->ring.tail_mask; \
400 virt = dev_priv->ring.virtual_start; \
403 #define OUT_RING(n) do { \
404 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
405 *(volatile unsigned int *)(virt + outring) = (n); \
408 outring &= ringmask; \
411 #define ADVANCE_LP_RING() do { \
412 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
413 dev_priv->ring.tail = outring; \
414 dev_priv->ring.space -= outcount * 4; \
415 I915_WRITE(LP_RING + RING_TAIL, outring); \
418 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
420 /* Extended config space */
425 #define VGA_ST01_MDA 0x3ba
426 #define VGA_ST01_CGA 0x3da
428 #define VGA_MSR_WRITE 0x3c2
429 #define VGA_MSR_READ 0x3cc
430 #define VGA_MSR_MEM_EN (1<<1)
431 #define VGA_MSR_CGA_MODE (1<<0)
433 #define VGA_SR_INDEX 0x3c4
434 #define VGA_SR_DATA 0x3c5
436 #define VGA_AR_INDEX 0x3c0
437 #define VGA_AR_VID_EN (1<<5)
438 #define VGA_AR_DATA_WRITE 0x3c0
439 #define VGA_AR_DATA_READ 0x3c1
441 #define VGA_GR_INDEX 0x3ce
442 #define VGA_GR_DATA 0x3cf
444 #define VGA_GR_MEM_READ_MODE_SHIFT 3
445 #define VGA_GR_MEM_READ_MODE_PLANE 1
447 #define VGA_GR_MEM_MODE_MASK 0xc
448 #define VGA_GR_MEM_MODE_SHIFT 2
449 #define VGA_GR_MEM_A0000_AFFFF 0
450 #define VGA_GR_MEM_A0000_BFFFF 1
451 #define VGA_GR_MEM_B0000_B7FFF 2
452 #define VGA_GR_MEM_B0000_BFFFF 3
454 #define VGA_DACMASK 0x3c6
455 #define VGA_DACRX 0x3c7
456 #define VGA_DACWX 0x3c8
457 #define VGA_DACDATA 0x3c9
459 #define VGA_CR_INDEX_MDA 0x3b4
460 #define VGA_CR_DATA_MDA 0x3b5
461 #define VGA_CR_INDEX_CGA 0x3d4
462 #define VGA_CR_DATA_CGA 0x3d5
464 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
465 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
466 #define CMD_REPORT_HEAD (7<<23)
467 #define CMD_STORE_DWORD_IMM ((0x20<<23) | (0x1 << 22) | 0x1)
468 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
469 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
471 #define CMD_MI_FLUSH (0x04 << 23)
472 #define MI_NO_WRITE_FLUSH (1 << 2)
473 #define MI_READ_FLUSH (1 << 0)
474 #define MI_EXE_FLUSH (1 << 1)
475 #define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
476 #define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
478 /* Packet to load a register value from the ring/batch command stream:
480 #define CMD_MI_LOAD_REGISTER_IMM ((0x22 << 23)|0x1)
482 #define BB1_START_ADDR_MASK (~0x7)
483 #define BB1_PROTECTED (1<<0)
484 #define BB1_UNPROTECTED (0<<0)
485 #define BB2_END_ADDR_MASK (~0x7)
487 /* Framebuffer compression */
488 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */
489 #define FBC_LL_BASE 0x03204 /* 4k page aligned */
490 #define FBC_CONTROL 0x03208
491 #define FBC_CTL_EN (1<<31)
492 #define FBC_CTL_PERIODIC (1<<30)
493 #define FBC_CTL_INTERVAL_SHIFT (16)
494 #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
495 #define FBC_CTL_STRIDE_SHIFT (5)
496 #define FBC_CTL_FENCENO (1<<0)
497 #define FBC_COMMAND 0x0320c
498 #define FBC_CMD_COMPRESS (1<<0)
499 #define FBC_STATUS 0x03210
500 #define FBC_STAT_COMPRESSING (1<<31)
501 #define FBC_STAT_COMPRESSED (1<<30)
502 #define FBC_STAT_MODIFIED (1<<29)
503 #define FBC_STAT_CURRENT_LINE (1<<0)
504 #define FBC_CONTROL2 0x03214
505 #define FBC_CTL_FENCE_DBL (0<<4)
506 #define FBC_CTL_IDLE_IMM (0<<2)
507 #define FBC_CTL_IDLE_FULL (1<<2)
508 #define FBC_CTL_IDLE_LINE (2<<2)
509 #define FBC_CTL_IDLE_DEBUG (3<<2)
510 #define FBC_CTL_CPU_FENCE (1<<1)
511 #define FBC_CTL_PLANEA (0<<0)
512 #define FBC_CTL_PLANEB (1<<0)
513 #define FBC_FENCE_OFF 0x0321b
515 #define FBC_LL_SIZE (1536)
516 #define FBC_LL_PAD (32)
520 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
521 #define I915_DISPLAY_PORT_INTERRUPT (1<<17)
522 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
523 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14)
524 #define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */
525 #define I915_SYNC_STATUS_INTERRUPT (1<<12)
526 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
527 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
528 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
529 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
530 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
531 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
532 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
533 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
534 #define I915_DEBUG_INTERRUPT (1<<2)
535 #define I915_USER_INTERRUPT (1<<1)
538 #define I915REG_HWSTAM 0x02098
539 #define I915REG_INT_IDENTITY_R 0x020a4
540 #define I915REG_INT_MASK_R 0x020a8
541 #define I915REG_INT_ENABLE_R 0x020a0
542 #define I915REG_INSTPM 0x020c0
544 #define PIPEADSL 0x70000
545 #define PIPEBDSL 0x71000
547 #define I915REG_PIPEASTAT 0x70024
548 #define I915REG_PIPEBSTAT 0x71024
550 * The two pipe frame counter registers are not synchronized, so
551 * reading a stable value is somewhat tricky. The following code
555 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
556 * PIPE_FRAME_HIGH_SHIFT;
557 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
558 * PIPE_FRAME_LOW_SHIFT);
559 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
560 * PIPE_FRAME_HIGH_SHIFT);
561 * } while (high1 != high2);
562 * frame = (high1 << 8) | low1;
564 #define PIPEAFRAMEHIGH 0x70040
565 #define PIPEBFRAMEHIGH 0x71040
566 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
567 #define PIPE_FRAME_HIGH_SHIFT 0
568 #define PIPEAFRAMEPIXEL 0x70044
569 #define PIPEBFRAMEPIXEL 0x71044
571 #define PIPE_FRAME_LOW_MASK 0xff000000
572 #define PIPE_FRAME_LOW_SHIFT 24
574 * Pixel within the current frame is counted in the PIPEAFRAMEPIXEL register
575 * and is 24 bits wide.
577 #define PIPE_PIXEL_MASK 0x00ffffff
578 #define PIPE_PIXEL_SHIFT 0
580 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31)
581 #define I915_CRC_ERROR_ENABLE (1UL<<29)
582 #define I915_CRC_DONE_ENABLE (1UL<<28)
583 #define I915_GMBUS_EVENT_ENABLE (1UL<<27)
584 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25)
585 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
586 #define I915_DPST_EVENT_ENABLE (1UL<<23)
587 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
588 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
589 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
590 #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
591 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17)
592 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16)
593 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
594 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
595 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11)
596 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9)
597 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
598 #define I915_DPST_EVENT_STATUS (1UL<<7)
599 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6)
600 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
601 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
602 #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
603 #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1)
604 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0)
606 #define SRX_INDEX 0x3c4
607 #define SRX_DATA 0x3c5
609 #define SR01_SCREEN_OFF (1<<5)
612 #define PPCR_ON (1<<0)
615 #define DVOB_ON (1<<31)
617 #define DVOC_ON (1<<31)
619 #define LVDS_ON (1<<31)
622 #define ADPA_DPMS_MASK (~(3<<10))
623 #define ADPA_DPMS_ON (0<<10)
624 #define ADPA_DPMS_SUSPEND (1<<10)
625 #define ADPA_DPMS_STANDBY (2<<10)
626 #define ADPA_DPMS_OFF (3<<10)
629 #define LP_RING 0x2030
630 #define HP_RING 0x2040
631 /* The binner has its own ring buffer:
633 #define HWB_RING 0x2400
635 #define RING_TAIL 0x00
636 #define TAIL_ADDR 0x001FFFF8
637 #define RING_HEAD 0x04
638 #define HEAD_WRAP_COUNT 0xFFE00000
639 #define HEAD_WRAP_ONE 0x00200000
640 #define HEAD_ADDR 0x001FFFFC
641 #define RING_START 0x08
642 #define START_ADDR 0x0xFFFFF000
643 #define RING_LEN 0x0C
644 #define RING_NR_PAGES 0x001FF000
645 #define RING_REPORT_MASK 0x00000006
646 #define RING_REPORT_64K 0x00000002
647 #define RING_REPORT_128K 0x00000004
648 #define RING_NO_REPORT 0x00000000
649 #define RING_VALID_MASK 0x00000001
650 #define RING_VALID 0x00000001
651 #define RING_INVALID 0x00000000
653 /* Instruction parser error reg:
657 /* Scratch pad debug 0 reg:
665 /* Secondary DMA fetch address debug reg:
667 #define DMA_FADD_S 0x20d4
669 /* Memory Interface Arbitration State
671 #define MI_ARB_STATE 0x20e4
674 * - Manipulating render cache behaviour is central
675 * to the concept of zone rendering, tuning this reg can help avoid
676 * unnecessary render cache reads and even writes (for z/stencil)
677 * at beginning and end of scene.
679 * - To change a bit, write to this reg with a mask bit set and the
680 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set.
682 #define Cache_Mode_0 0x2120
683 #define CACHE_MODE_0 0x2120
684 #define CM0_MASK_SHIFT 16
685 #define CM0_IZ_OPT_DISABLE (1<<6)
686 #define CM0_ZR_OPT_DISABLE (1<<5)
687 #define CM0_DEPTH_EVICT_DISABLE (1<<4)
688 #define CM0_COLOR_EVICT_DISABLE (1<<3)
689 #define CM0_DEPTH_WRITE_DISABLE (1<<1)
690 #define CM0_RC_OP_FLUSH_DISABLE (1<<0)
693 /* Graphics flush control. A CPU write flushes the GWB of all writes.
694 * The data is discarded.
696 #define GFX_FLSH_CNTL 0x2170
698 /* Binner control. Defines the location of the bin pointer list:
700 #define BINCTL 0x2420
701 #define BC_MASK (1 << 9)
703 /* Binned scene info.
705 #define BINSCENE 0x2428
706 #define BS_OP_LOAD (1 << 8)
707 #define BS_MASK (1 << 22)
709 /* Bin command parser debug reg:
713 /* Bin memory control debug reg:
717 /* Bin data cache debug reg:
721 /* Binner pointer cache debug reg:
725 /* Binner scratch pad debug reg:
727 #define BINSKPD 0x24f0
729 /* HWB scratch pad debug reg:
731 #define HWBSKPD 0x24f4
733 /* Binner memory pool reg:
735 #define BMP_BUFFER 0x2430
736 #define BMP_PAGE_SIZE_4K (0 << 10)
737 #define BMP_BUFFER_SIZE_SHIFT 1
738 #define BMP_ENABLE (1 << 0)
740 /* Get/put memory from the binner memory pool:
742 #define BMP_GET 0x2438
743 #define BMP_PUT 0x2440
744 #define BMP_OFFSET_SHIFT 5
748 #define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
750 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
751 #define SC_UPDATE_SCISSOR (0x1<<1)
752 #define SC_ENABLE_MASK (0x1<<0)
753 #define SC_ENABLE (0x1<<0)
755 #define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
757 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
758 #define SCI_YMIN_MASK (0xffff<<16)
759 #define SCI_XMIN_MASK (0xffff<<0)
760 #define SCI_YMAX_MASK (0xffff<<16)
761 #define SCI_XMAX_MASK (0xffff<<0)
763 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
764 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
765 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
766 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
767 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
768 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
769 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
771 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
773 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
774 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
775 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
776 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
777 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
778 #define XY_SRC_COPY_BLT_DST_TILED (1<<11)
781 #define MI_BATCH_BUFFER ((0x30<<23)|1)
782 #define MI_BATCH_BUFFER_START (0x31<<23)
783 #define MI_BATCH_BUFFER_END (0xA<<23)
784 #define MI_BATCH_NON_SECURE (1)
786 #define MI_BATCH_NON_SECURE_I965 (1<<8)
788 #define MI_WAIT_FOR_EVENT ((0x3<<23))
789 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
790 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
791 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
793 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23))
795 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
796 #define ASYNC_FLIP (1<<22)
797 #define DISPLAY_PLANE_A (0<<20)
798 #define DISPLAY_PLANE_B (1<<20)
801 #define DSPACNTR 0x70180
802 #define DSPBCNTR 0x71180
803 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
805 /* Define the region of interest for the binner:
807 #define CMD_OP_BIN_CONTROL ((0x3<<29)|(0x1d<<24)|(0x84<<16)|4)
809 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
811 #define BREADCRUMB_BITS 31
812 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
814 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5])
815 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
817 #define BLC_PWM_CTL 0x61254
818 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
820 #define BLC_PWM_CTL2 0x61250
822 * This is the most significant 15 bits of the number of backlight cycles in a
823 * complete cycle of the modulated backlight control.
825 * The actual value is this field multiplied by two.
827 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
828 #define BLM_LEGACY_MODE (1 << 16)
830 * This is the number of cycles out of the backlight modulation cycle for which
831 * the backlight is on.
833 * This field must be no greater than the number of cycles in the complete
834 * backlight modulation cycle.
836 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
837 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
839 #define I915_GCFGC 0xf0
840 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
841 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
842 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
843 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
845 #define I855_HPLLCC 0xc0
846 #define I855_CLOCK_CONTROL_MASK (3 << 0)
847 #define I855_CLOCK_133_200 (0 << 0)
848 #define I855_CLOCK_100_200 (1 << 0)
849 #define I855_CLOCK_100_133 (2 << 0)
850 #define I855_CLOCK_166_250 (3 << 0)
854 #define VCLK2_VCO_M 0x6008 /* treat as 16 bit? (includes msbs) */
855 #define VCLK2_VCO_N 0x600a
856 #define VCLK2_VCO_DIV_SEL 0x6012
858 #define VCLK_DIVISOR_VGA0 0x6000
859 #define VCLK_DIVISOR_VGA1 0x6004
860 #define VCLK_POST_DIV 0x6010
861 /** Selects a post divisor of 4 instead of 2. */
862 # define VGA1_PD_P2_DIV_4 (1 << 15)
863 /** Overrides the p2 post divisor field */
864 # define VGA1_PD_P1_DIV_2 (1 << 13)
865 # define VGA1_PD_P1_SHIFT 8
866 /** P1 value is 2 greater than this field */
867 # define VGA1_PD_P1_MASK (0x1f << 8)
868 /** Selects a post divisor of 4 instead of 2. */
869 # define VGA0_PD_P2_DIV_4 (1 << 7)
870 /** Overrides the p2 post divisor field */
871 # define VGA0_PD_P1_DIV_2 (1 << 5)
872 # define VGA0_PD_P1_SHIFT 0
873 /** P1 value is 2 greater than this field */
874 # define VGA0_PD_P1_MASK (0x1f << 0)
876 /* PCI D state control register */
877 #define D_STATE 0x6104
878 #define DSPCLK_GATE_D 0x6200
880 /* I830 CRTC registers */
881 #define HTOTAL_A 0x60000
882 #define HBLANK_A 0x60004
883 #define HSYNC_A 0x60008
884 #define VTOTAL_A 0x6000c
885 #define VBLANK_A 0x60010
886 #define VSYNC_A 0x60014
887 #define PIPEASRC 0x6001c
888 #define BCLRPAT_A 0x60020
889 #define VSYNCSHIFT_A 0x60028
891 #define HTOTAL_B 0x61000
892 #define HBLANK_B 0x61004
893 #define HSYNC_B 0x61008
894 #define VTOTAL_B 0x6100c
895 #define VBLANK_B 0x61010
896 #define VSYNC_B 0x61014
897 #define PIPEBSRC 0x6101c
898 #define BCLRPAT_B 0x61020
899 #define VSYNCSHIFT_B 0x61028
901 #define HACTIVE_MASK 0x00000fff
902 #define VTOTAL_MASK 0x00001fff
903 #define VTOTAL_SHIFT 16
904 #define VACTIVE_MASK 0x00000fff
905 #define VBLANK_END_MASK 0x00001fff
906 #define VBLANK_END_SHIFT 16
907 #define VBLANK_START_MASK 0x00001fff
909 #define PP_STATUS 0x61200
910 # define PP_ON (1 << 31)
912 * Indicates that all dependencies of the panel are on:
916 * - LVDS/DVOB/DVOC on
918 # define PP_READY (1 << 30)
919 # define PP_SEQUENCE_NONE (0 << 28)
920 # define PP_SEQUENCE_ON (1 << 28)
921 # define PP_SEQUENCE_OFF (2 << 28)
922 # define PP_SEQUENCE_MASK 0x30000000
923 #define PP_CONTROL 0x61204
924 # define POWER_TARGET_ON (1 << 0)
926 #define LVDSPP_ON 0x61208
927 #define LVDSPP_OFF 0x6120c
928 #define PP_CYCLE 0x61210
930 #define PFIT_CONTROL 0x61230
931 # define PFIT_ENABLE (1 << 31)
932 # define PFIT_PIPE_MASK (3 << 29)
933 # define PFIT_PIPE_SHIFT 29
934 # define VERT_INTERP_DISABLE (0 << 10)
935 # define VERT_INTERP_BILINEAR (1 << 10)
936 # define VERT_INTERP_MASK (3 << 10)
937 # define VERT_AUTO_SCALE (1 << 9)
938 # define HORIZ_INTERP_DISABLE (0 << 6)
939 # define HORIZ_INTERP_BILINEAR (1 << 6)
940 # define HORIZ_INTERP_MASK (3 << 6)
941 # define HORIZ_AUTO_SCALE (1 << 5)
942 # define PANEL_8TO6_DITHER_ENABLE (1 << 3)
944 #define PFIT_PGM_RATIOS 0x61234
945 # define PFIT_VERT_SCALE_MASK 0xfff00000
946 # define PFIT_HORIZ_SCALE_MASK 0x0000fff0
948 #define PFIT_AUTO_RATIOS 0x61238
951 #define DPLL_A 0x06014
952 #define DPLL_B 0x06018
953 # define DPLL_VCO_ENABLE (1 << 31)
954 # define DPLL_DVO_HIGH_SPEED (1 << 30)
955 # define DPLL_SYNCLOCK_ENABLE (1 << 29)
956 # define DPLL_VGA_MODE_DIS (1 << 28)
957 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
958 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */
959 # define DPLL_MODE_MASK (3 << 26)
960 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
961 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
962 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
963 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
964 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
965 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
967 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
968 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
970 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
972 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
973 * this field (only one bit may be set).
975 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
976 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16
977 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
978 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
979 # define PLL_REF_INPUT_DREFCLK (0 << 13)
980 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
981 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
982 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
983 # define PLL_REF_INPUT_MASK (3 << 13)
984 # define PLL_LOAD_PULSE_PHASE_SHIFT 9
986 * Parallel to Serial Load Pulse phase selection.
987 * Selects the phase for the 10X DPLL clock for the PCIe
988 * digital display port. The range is 4 to 13; 10 or more
989 * is just a flip delay. The default is 6
991 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
992 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
995 * SDVO multiplier for 945G/GM. Not used on 965.
997 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
999 # define SDVO_MULTIPLIER_MASK 0x000000ff
1000 # define SDVO_MULTIPLIER_SHIFT_HIRES 4
1001 # define SDVO_MULTIPLIER_SHIFT_VGA 0
1003 /** @defgroup DPLL_MD
1006 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */
1007 #define DPLL_A_MD 0x0601c
1008 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */
1009 #define DPLL_B_MD 0x06020
1011 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1013 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1015 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1016 # define DPLL_MD_UDI_DIVIDER_SHIFT 24
1017 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1018 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1019 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1021 * SDVO/UDI pixel multiplier.
1023 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1024 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1025 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1026 * dummy bytes in the datastream at an increased clock rate, with both sides of
1027 * the link knowing how many bytes are fill.
1029 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1030 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1031 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1032 * through an SDVO command.
1034 * This register field has values of multiplication factor minus 1, with
1035 * a maximum multiplier of 5 for SDVO.
1037 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1038 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1039 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1040 * This best be set to the default value (3) or the CRT won't work. No,
1041 * I don't entirely understand what this does...
1043 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1044 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1047 #define DPLL_TEST 0x606c
1048 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1049 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1050 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1051 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1052 # define DPLLB_TEST_N_BYPASS (1 << 19)
1053 # define DPLLB_TEST_M_BYPASS (1 << 18)
1054 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1055 # define DPLLA_TEST_N_BYPASS (1 << 3)
1056 # define DPLLA_TEST_M_BYPASS (1 << 2)
1057 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1059 #define ADPA 0x61100
1060 #define ADPA_DAC_ENABLE (1<<31)
1061 #define ADPA_DAC_DISABLE 0
1062 #define ADPA_PIPE_SELECT_MASK (1<<30)
1063 #define ADPA_PIPE_A_SELECT 0
1064 #define ADPA_PIPE_B_SELECT (1<<30)
1065 #define ADPA_USE_VGA_HVPOLARITY (1<<15)
1066 #define ADPA_SETS_HVPOLARITY 0
1067 #define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1068 #define ADPA_VSYNC_CNTL_ENABLE 0
1069 #define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1070 #define ADPA_HSYNC_CNTL_ENABLE 0
1071 #define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1072 #define ADPA_VSYNC_ACTIVE_LOW 0
1073 #define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1074 #define ADPA_HSYNC_ACTIVE_LOW 0
1076 #define FPA0 0x06040
1077 #define FPA1 0x06044
1078 #define FPB0 0x06048
1079 #define FPB1 0x0604c
1080 # define FP_N_DIV_MASK 0x003f0000
1081 # define FP_N_DIV_SHIFT 16
1082 # define FP_M1_DIV_MASK 0x00003f00
1083 # define FP_M1_DIV_SHIFT 8
1084 # define FP_M2_DIV_MASK 0x0000003f
1085 # define FP_M2_DIV_SHIFT 0
1088 #define PORT_HOTPLUG_EN 0x61110
1089 # define SDVOB_HOTPLUG_INT_EN (1 << 26)
1090 # define SDVOC_HOTPLUG_INT_EN (1 << 25)
1091 # define TV_HOTPLUG_INT_EN (1 << 18)
1092 # define CRT_HOTPLUG_INT_EN (1 << 9)
1093 # define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1095 #define PORT_HOTPLUG_STAT 0x61114
1096 # define CRT_HOTPLUG_INT_STATUS (1 << 11)
1097 # define TV_HOTPLUG_INT_STATUS (1 << 10)
1098 # define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1099 # define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1100 # define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1101 # define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1102 # define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1103 # define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1105 #define SDVOB 0x61140
1106 #define SDVOC 0x61160
1107 #define SDVO_ENABLE (1 << 31)
1108 #define SDVO_PIPE_B_SELECT (1 << 30)
1109 #define SDVO_STALL_SELECT (1 << 29)
1110 #define SDVO_INTERRUPT_ENABLE (1 << 26)
1112 * 915G/GM SDVO pixel multiplier.
1114 * Programmed value is multiplier - 1, up to 5x.
1116 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1118 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1119 #define SDVO_PORT_MULTIPLY_SHIFT 23
1120 #define SDVO_PHASE_SELECT_MASK (15 << 19)
1121 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1122 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1123 #define SDVOC_GANG_MODE (1 << 16)
1124 #define SDVO_BORDER_ENABLE (1 << 7)
1125 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
1126 #define SDVO_DETECTED (1 << 2)
1127 /* Bits to be preserved when writing */
1128 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
1129 #define SDVOC_PRESERVE_MASK (1 << 17)
1135 * This register controls the LVDS output enable, pipe selection, and data
1138 * All of the clock/data pairs are force powered down by power sequencing.
1140 #define LVDS 0x61180
1142 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1143 * the DPLL semantics change when the LVDS is assigned to that pipe.
1145 # define LVDS_PORT_EN (1 << 31)
1146 /** Selects pipe B for LVDS data. Must be set on pre-965. */
1147 # define LVDS_PIPEB_SELECT (1 << 30)
1150 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1153 # define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1154 # define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1155 # define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1157 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1158 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1161 # define LVDS_A3_POWER_MASK (3 << 6)
1162 # define LVDS_A3_POWER_DOWN (0 << 6)
1163 # define LVDS_A3_POWER_UP (3 << 6)
1165 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1168 # define LVDS_CLKB_POWER_MASK (3 << 4)
1169 # define LVDS_CLKB_POWER_DOWN (0 << 4)
1170 # define LVDS_CLKB_POWER_UP (3 << 4)
1173 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1174 * setting for whether we are in dual-channel mode. The B3 pair will
1175 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1177 # define LVDS_B0B3_POWER_MASK (3 << 2)
1178 # define LVDS_B0B3_POWER_DOWN (0 << 2)
1179 # define LVDS_B0B3_POWER_UP (3 << 2)
1181 #define PIPEACONF 0x70008
1182 #define PIPEACONF_ENABLE (1<<31)
1183 #define PIPEACONF_DISABLE 0
1184 #define PIPEACONF_DOUBLE_WIDE (1<<30)
1185 #define I965_PIPECONF_ACTIVE (1<<30)
1186 #define PIPEACONF_SINGLE_WIDE 0
1187 #define PIPEACONF_PIPE_UNLOCKED 0
1188 #define PIPEACONF_PIPE_LOCKED (1<<25)
1189 #define PIPEACONF_PALETTE 0
1190 #define PIPEACONF_GAMMA (1<<24)
1191 #define PIPECONF_FORCE_BORDER (1<<25)
1192 #define PIPECONF_PROGRESSIVE (0 << 21)
1193 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
1194 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
1196 #define DSPARB 0x70030
1197 #define DSPARB_CSTART_MASK (0x7f << 7)
1198 #define DSPARB_CSTART_SHIFT 7
1199 #define DSPARB_BSTART_MASK (0x7f)
1200 #define DSPARB_BSTART_SHIFT 0
1202 #define PIPEBCONF 0x71008
1203 #define PIPEBCONF_ENABLE (1<<31)
1204 #define PIPEBCONF_DISABLE 0
1205 #define PIPEBCONF_DOUBLE_WIDE (1<<30)
1206 #define PIPEBCONF_DISABLE 0
1207 #define PIPEBCONF_GAMMA (1<<24)
1208 #define PIPEBCONF_PALETTE 0
1210 #define PIPEBGCMAXRED 0x71010
1211 #define PIPEBGCMAXGREEN 0x71014
1212 #define PIPEBGCMAXBLUE 0x71018
1213 #define PIPEBSTAT 0x71024
1214 #define PIPEBFRAMEHIGH 0x71040
1215 #define PIPEBFRAMEPIXEL 0x71044
1217 #define DSPACNTR 0x70180
1218 #define DSPBCNTR 0x71180
1219 #define DISPLAY_PLANE_ENABLE (1<<31)
1220 #define DISPLAY_PLANE_DISABLE 0
1221 #define DISPPLANE_GAMMA_ENABLE (1<<30)
1222 #define DISPPLANE_GAMMA_DISABLE 0
1223 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
1224 #define DISPPLANE_8BPP (0x2<<26)
1225 #define DISPPLANE_15_16BPP (0x4<<26)
1226 #define DISPPLANE_16BPP (0x5<<26)
1227 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
1228 #define DISPPLANE_32BPP (0x7<<26)
1229 #define DISPPLANE_STEREO_ENABLE (1<<25)
1230 #define DISPPLANE_STEREO_DISABLE 0
1231 #define DISPPLANE_SEL_PIPE_MASK (1<<24)
1232 #define DISPPLANE_SEL_PIPE_A 0
1233 #define DISPPLANE_SEL_PIPE_B (1<<24)
1234 #define DISPPLANE_SRC_KEY_ENABLE (1<<22)
1235 #define DISPPLANE_SRC_KEY_DISABLE 0
1236 #define DISPPLANE_LINE_DOUBLE (1<<20)
1237 #define DISPPLANE_NO_LINE_DOUBLE 0
1238 #define DISPPLANE_STEREO_POLARITY_FIRST 0
1239 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
1241 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
1242 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
1243 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
1244 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
1246 #define DSPABASE 0x70184
1247 #define DSPASTRIDE 0x70188
1249 #define DSPBBASE 0x71184
1250 #define DSPBADDR DSPBBASE
1251 #define DSPBSTRIDE 0x71188
1253 #define DSPAKEYVAL 0x70194
1254 #define DSPAKEYMASK 0x70198
1256 #define DSPAPOS 0x7018C /* reserved */
1257 #define DSPASIZE 0x70190
1258 #define DSPBPOS 0x7118C
1259 #define DSPBSIZE 0x71190
1261 #define DSPASURF 0x7019C
1262 #define DSPATILEOFF 0x701A4
1264 #define DSPBSURF 0x7119C
1265 #define DSPBTILEOFF 0x711A4
1267 #define VGACNTRL 0x71400
1268 # define VGA_DISP_DISABLE (1 << 31)
1269 # define VGA_2X_MODE (1 << 30)
1270 # define VGA_PIPE_B_SELECT (1 << 29)
1273 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
1274 * of video memory available to the BIOS in SWF1.
1277 #define SWF0 0x71410
1280 * 855 scratch registers.
1282 #define SWF10 0x70410
1284 #define SWF30 0x72414
1287 * Overlay registers. These are overlay registers accessed via MMIO.
1288 * Those loaded via the overlay register page are defined in i830_video.c.
1290 #define OVADD 0x30000
1292 #define DOVSTA 0x30008
1293 #define OC_BUF (0x3<<20)
1295 #define OGAMC5 0x30010
1296 #define OGAMC4 0x30014
1297 #define OGAMC3 0x30018
1298 #define OGAMC2 0x3001c
1299 #define OGAMC1 0x30020
1300 #define OGAMC0 0x30024
1304 #define PALETTE_A 0x0a000
1305 #define PALETTE_B 0x0a800
1307 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1308 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1309 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
1310 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
1311 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1313 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
1314 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1315 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1316 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
1317 (dev)->pci_device == 0x27AE)
1318 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
1319 (dev)->pci_device == 0x2982 || \
1320 (dev)->pci_device == 0x2992 || \
1321 (dev)->pci_device == 0x29A2 || \
1322 (dev)->pci_device == 0x2A02 || \
1323 (dev)->pci_device == 0x2A12 || \
1324 (dev)->pci_device == 0x2A42)
1326 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
1328 #define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
1330 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1331 (dev)->pci_device == 0x29B2 || \
1332 (dev)->pci_device == 0x29D2)
1334 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1335 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
1337 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1338 IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
1340 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev))
1342 #define PRIMARY_RINGBUFFER_SIZE (128*1024)