shared-core/i915_init.c

   1 /*
   2  * Copyright (c) 2007 Intel Corporation
   3  *   Jesse Barnes <jesse.barnes@intel.com>
   4  *
   5  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   6  *                   2004 Sylvain Meyer
   7  *
   8  * GPL/BSD dual license
   9  */
  10 #include "drmP.h"
  11 #include "drm.h"
  12 #include "drm_sarea.h"
  13 #include "i915_drm.h"
  14 #include "i915_drv.h"
  15
  16 /**
  17  * i915_probe_agp - get AGP bootup configuration
  18  * @pdev: PCI device
  19  * @aperture_size: returns AGP aperture configured size
  20  * @preallocated_size: returns size of BIOS preallocated AGP space
  21  *
  22  * Since Intel integrated graphics are UMA, the BIOS has to set aside
  23  * some RAM for the framebuffer at early boot.  This code figures out
  24  * how much was set aside so we can use it for our own purposes.
  25  */
  26 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
  27                    unsigned long *preallocated_size)
  28 {
  29         struct pci_dev *bridge_dev;
  30         u16 tmp = 0;
  31         unsigned long overhead;
  32
  33         bridge_dev = pci_find_slot(0, PCI_DEVFN(0,0));
  34         if (!bridge_dev) {
  35                 DRM_ERROR("bridge device not found\n");
  36                 return -1;
  37         }
  38
  39         /* Get the fb aperture size and "stolen" memory amount. */
  40         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
  41         pci_dev_put(bridge_dev);
  42
  43         *aperture_size = 1024 * 1024;
  44         *preallocated_size = 1024 * 1024;
  45
  46         switch (pdev->device) {
  47         case PCI_DEVICE_ID_INTEL_82830_CGC:
  48         case PCI_DEVICE_ID_INTEL_82845G_IG:
  49         case PCI_DEVICE_ID_INTEL_82855GM_IG:
  50         case PCI_DEVICE_ID_INTEL_82865_IG:
  51                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  52                         *aperture_size *= 64;
  53                 else
  54                         *aperture_size *= 128;
  55                 break;
  56         default:
  57                 /* 9xx supports large sizes, just look at the length */
  58                 *aperture_size = pci_resource_len(pdev, 2);
  59                 break;
  60         }
  61
  62         /*
  63          * Some of the preallocated space is taken by the GTT
  64          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
  65          */
  66         overhead = (*aperture_size / 1024) + 4096;
  67         switch (tmp & INTEL_855_GMCH_GMS_MASK) {
  68         case INTEL_855_GMCH_GMS_STOLEN_1M:
  69                 break; /* 1M already */
  70         case INTEL_855_GMCH_GMS_STOLEN_4M:
  71                 *preallocated_size *= 4;
  72                 break;
  73         case INTEL_855_GMCH_GMS_STOLEN_8M:
  74                 *preallocated_size *= 8;
  75                 break;
  76         case INTEL_855_GMCH_GMS_STOLEN_16M:
  77                 *preallocated_size *= 16;
  78                 break;
  79         case INTEL_855_GMCH_GMS_STOLEN_32M:
  80                 *preallocated_size *= 32;
  81                 break;
  82         case INTEL_915G_GMCH_GMS_STOLEN_48M:
  83                 *preallocated_size *= 48;
  84                 break;
  85         case INTEL_915G_GMCH_GMS_STOLEN_64M:
  86                 *preallocated_size *= 64;
  87                 break;
  88         case INTEL_855_GMCH_GMS_DISABLED:
  89                 DRM_ERROR("video memory is disabled\n");
  90                 return -1;
  91         default:
  92                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  93                         tmp & INTEL_855_GMCH_GMS_MASK);
  94                 return -1;
  95         }
  96         *preallocated_size -= overhead;
  97
  98         return 0;
  99 }
 100
 101 /**
 102  * i915_driver_load - setup chip and create an initial config
 103  * @dev: DRM device
 104  * @flags: startup flags
 105  *
 106  * The driver load routine has to do several things:
 107  *   - drive output discovery via intel_modeset_init()
 108  *   - initialize the memory manager
 109  *   - allocate initial config memory
 110  *   - setup the DRM framebuffer with the allocated memory
 111  */
 112 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 113 {
 114         struct drm_i915_private *dev_priv;
 115         unsigned long agp_size, prealloc_size;
 116         unsigned long sareapage;
 117         int size, ret;
 118
 119         dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
 120         if (dev_priv == NULL)
 121                 return -ENOMEM;
 122
 123         memset(dev_priv, 0, sizeof(struct drm_i915_private));
 124         dev->dev_private = (void *)dev_priv;
 125 //      dev_priv->flags = flags;
 126
 127         /* i915 has 4 more counters */
 128         dev->counters += 4;
 129         dev->types[6] = _DRM_STAT_IRQ;
 130         dev->types[7] = _DRM_STAT_PRIMARY;
 131         dev->types[8] = _DRM_STAT_SECONDARY;
 132         dev->types[9] = _DRM_STAT_DMA;
 133
 134         if (IS_I9XX(dev)) {
 135                 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
 136                 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
 137                 dev->mode_config.fb_base =
 138                         drm_get_resource_start(dev, 2) & 0xff000000;
 139         } else if (drm_get_resource_start(dev, 1)) {
 140                 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
 141                 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
 142                 dev->mode_config.fb_base =
 143                         drm_get_resource_start(dev, 0) & 0xff000000;
 144         } else {
 145                 DRM_ERROR("Unable to find MMIO registers\n");
 146                 return -ENODEV;
 147         }
 148
 149         DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
 150
 151         ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
 152                          _DRM_REGISTERS, _DRM_READ_ONLY|_DRM_DRIVER, &dev_priv->mmio_map);
 153         if (ret != 0) {
 154                 DRM_ERROR("Cannot add mapping for MMIO registers\n");
 155                 return ret;
 156         }
 157
 158         /* prebuild the SAREA */
 159         sareapage = max(SAREA_MAX, PAGE_SIZE);
 160         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
 161                          &dev_priv->sarea);
 162         if (ret) {
 163                 DRM_ERROR("SAREA setup failed\n");
 164                 return ret;
 165         }
 166
 167         init_waitqueue_head(&dev->lock.lock_queue);
 168
 169         /* FIXME: assume sarea_priv is right after SAREA */
 170         dev_priv->sarea_priv = dev_priv->sarea->handle + sizeof(struct drm_sarea);
 171
 172         /*
 173          * Initialize the memory manager for local and AGP space
 174          */
 175         drm_bo_driver_init(dev);
 176
 177         i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
 178         printk("setting up %ld bytes of VRAM space\n", prealloc_size);
 179         printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
 180         drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT);
 181         drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT, (agp_size - prealloc_size) >> PAGE_SHIFT);
 182
 183         I915_WRITE(LP_RING + RING_LEN, 0);
 184         I915_WRITE(LP_RING + RING_HEAD, 0);
 185         I915_WRITE(LP_RING + RING_TAIL, 0);
 186
 187         size = PRIMARY_RINGBUFFER_SIZE;
 188         ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
 189                                        DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
 190                                        DRM_BO_FLAG_MEM_VRAM |
 191                                        DRM_BO_FLAG_NO_EVICT |
 192                                        DRM_BO_HINT_DONT_FENCE, 0, 0x1, 0,
 193                                        &dev_priv->ring_buffer);
 194         if (ret < 0) {
 195                 DRM_ERROR("Unable to allocate or pin ring buffer\n");
 196                 return -EINVAL;
 197         }
 198
 199         /* remap the buffer object properly */
 200         dev_priv->ring.Start = dev_priv->ring_buffer->offset;
 201         dev_priv->ring.End = dev_priv->ring.Start + size;
 202         dev_priv->ring.Size = size;
 203         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 204
 205         /* FIXME: need wrapper with PCI mem checks */
 206         ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
 207                                   (void **) &dev_priv->ring.virtual_start);
 208         if (ret)
 209                 DRM_ERROR("error mapping ring buffer: %d\n", ret);
 210
 211         DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
 212                   dev_priv->ring.virtual_start, dev_priv->ring.Size);
 213
 214         dev_priv->sarea_priv->pf_current_page = 0;
 215
 216         memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
 217
 218         I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
 219         I915_WRITE(LP_RING + RING_LEN,
 220                    ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
 221                    (RING_NO_REPORT | RING_VALID));
 222
 223         /* We are using separate values as placeholders for mechanisms for
 224          * private backbuffer/depthbuffer usage.
 225          */
 226         dev_priv->use_mi_batchbuffer_start = 0;
 227
 228         /* Allow hardware batchbuffers unless told otherwise.
 229          */
 230         dev_priv->allow_batchbuffer = 1;
 231
 232         /* Program Hardware Status Page */
 233         if (!IS_G33(dev)) {
 234                 dev_priv->status_page_dmah =
 235                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 236
 237                 if (!dev_priv->status_page_dmah) {
 238                         dev->dev_private = (void *)dev_priv;
 239                         i915_dma_cleanup(dev);
 240                         DRM_ERROR("Can not allocate hardware status page\n");
 241                         return -ENOMEM;
 242                 }
 243                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 244                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 245
 246                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 247
 248                 I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
 249         }
 250         DRM_DEBUG("Enabled hardware status page\n");
 251
 252         dev_priv->wq = create_singlethread_workqueue("i915");
 253         if (dev_priv == 0) {
 254                 DRM_DEBUG("Error\n");
 255         }
 256
 257
 258         intel_modeset_init(dev);
 259         drm_initial_config(dev, false);
 260
 261         drm_mm_print(&dev->bm.man[DRM_BO_MEM_VRAM].manager, "VRAM");
 262         drm_mm_print(&dev->bm.man[DRM_BO_MEM_TT].manager, "TT");
 263
 264         drm_irq_install(dev);
 265
 266         return 0;
 267 }
 268
 269 int i915_driver_unload(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272
 273         I915_WRITE(LP_RING + RING_LEN, 0);
 274
 275         intel_modeset_cleanup(dev);
 276
 277 #if 0
 278         if (dev_priv->ring.virtual_start) {
 279                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 280         }
 281 #endif
 282
 283         if (dev_priv->status_page_dmah) {
 284                 drm_pci_free(dev, dev_priv->status_page_dmah);
 285                 dev_priv->status_page_dmah = NULL;
 286                 dev_priv->hw_status_page = NULL;
 287                 dev_priv->dma_status_page = 0;
 288                 /* Need to rewrite hardware status page */
 289                 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
 290         }
 291
 292         if (dev_priv->status_gfx_addr) {
 293                 dev_priv->status_gfx_addr = 0;
 294                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 295                 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
 296         }
 297
 298         drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
 299                             dev_priv->ring.virtual_start);
 300
 301         DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
 302         mutex_lock(&dev->struct_mutex);
 303         drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
 304
 305         if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT)) {
 306                 DRM_ERROR("Memory manager type 3 not clean. "
 307                           "Delaying takedown\n");
 308         }
 309         if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM)) {
 310                 DRM_ERROR("Memory manager type 3 not clean. "
 311                           "Delaying takedown\n");
 312         }
 313         mutex_unlock(&dev->struct_mutex);
 314
 315         drm_bo_driver_finish(dev);
 316
 317         DRM_DEBUG("%p, %p\n", dev_priv->mmio_map, dev_priv->sarea);
 318         drm_rmmap(dev, dev_priv->mmio_map);
 319         drm_rmmap(dev, dev_priv->sarea);
 320
 321         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 322
 323         dev->dev_private = NULL;
 324         return 0;
 325 }