shared-core/i915_init.c

   1 /*
   2  * Copyright (c) 2007 Intel Corporation
   3  *   Jesse Barnes <jesse.barnes@intel.com>
   4  *
   5  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   6  *                   2004 Sylvain Meyer
   7  *
   8  * GPL/BSD dual license
   9  */
  10 #include "drmP.h"
  11 #include "drm.h"
  12 #include "drm_sarea.h"
  13 #include "i915_drm.h"
  14 #include "i915_drv.h"
  15 #include "intel_bios.h"
  16
  17 /**
  18  * i915_probe_agp - get AGP bootup configuration
  19  * @pdev: PCI device
  20  * @aperture_size: returns AGP aperture configured size
  21  * @preallocated_size: returns size of BIOS preallocated AGP space
  22  *
  23  * Since Intel integrated graphics are UMA, the BIOS has to set aside
  24  * some RAM for the framebuffer at early boot.  This code figures out
  25  * how much was set aside so we can use it for our own purposes.
  26  */
  27 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
  28                    unsigned long *preallocated_size)
  29 {
  30         struct pci_dev *bridge_dev;
  31         u16 tmp = 0;
  32         unsigned long overhead;
  33
  34         bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
  35         if (!bridge_dev) {
  36                 DRM_ERROR("bridge device not found\n");
  37                 return -1;
  38         }
  39
  40         /* Get the fb aperture size and "stolen" memory amount. */
  41         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
  42         pci_dev_put(bridge_dev);
  43
  44         *aperture_size = 1024 * 1024;
  45         *preallocated_size = 1024 * 1024;
  46
  47         switch (pdev->device) {
  48         case PCI_DEVICE_ID_INTEL_82830_CGC:
  49         case PCI_DEVICE_ID_INTEL_82845G_IG:
  50         case PCI_DEVICE_ID_INTEL_82855GM_IG:
  51         case PCI_DEVICE_ID_INTEL_82865_IG:
  52                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  53                         *aperture_size *= 64;
  54                 else
  55                         *aperture_size *= 128;
  56                 break;
  57         default:
  58                 /* 9xx supports large sizes, just look at the length */
  59                 *aperture_size = pci_resource_len(pdev, 2);
  60                 break;
  61         }
  62
  63         /*
  64          * Some of the preallocated space is taken by the GTT
  65          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
  66          */
  67         overhead = (*aperture_size / 1024) + 4096;
  68         switch (tmp & INTEL_855_GMCH_GMS_MASK) {
  69         case INTEL_855_GMCH_GMS_STOLEN_1M:
  70                 break; /* 1M already */
  71         case INTEL_855_GMCH_GMS_STOLEN_4M:
  72                 *preallocated_size *= 4;
  73                 break;
  74         case INTEL_855_GMCH_GMS_STOLEN_8M:
  75                 *preallocated_size *= 8;
  76                 break;
  77         case INTEL_855_GMCH_GMS_STOLEN_16M:
  78                 *preallocated_size *= 16;
  79                 break;
  80         case INTEL_855_GMCH_GMS_STOLEN_32M:
  81                 *preallocated_size *= 32;
  82                 break;
  83         case INTEL_915G_GMCH_GMS_STOLEN_48M:
  84                 *preallocated_size *= 48;
  85                 break;
  86         case INTEL_915G_GMCH_GMS_STOLEN_64M:
  87                 *preallocated_size *= 64;
  88                 break;
  89         case INTEL_855_GMCH_GMS_DISABLED:
  90                 DRM_ERROR("video memory is disabled\n");
  91                 return -1;
  92         default:
  93                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  94                         tmp & INTEL_855_GMCH_GMS_MASK);
  95                 return -1;
  96         }
  97         *preallocated_size -= overhead;
  98
  99         return 0;
 100 }
 101
 102 /**
 103  * i915_driver_load - setup chip and create an initial config
 104  * @dev: DRM device
 105  * @flags: startup flags
 106  *
 107  * The driver load routine has to do several things:
 108  *   - drive output discovery via intel_modeset_init()
 109  *   - initialize the memory manager
 110  *   - allocate initial config memory
 111  *   - setup the DRM framebuffer with the allocated memory
 112  */
 113 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 114 {
 115         struct drm_i915_private *dev_priv;
 116         unsigned long agp_size, prealloc_size;
 117         int size, ret;
 118
 119         dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
 120         if (dev_priv == NULL)
 121                 return -ENOMEM;
 122
 123         memset(dev_priv, 0, sizeof(struct drm_i915_private));
 124         dev->dev_private = (void *)dev_priv;
 125 //      dev_priv->flags = flags;
 126
 127         /* i915 has 4 more counters */
 128         dev->counters += 4;
 129         dev->types[6] = _DRM_STAT_IRQ;
 130         dev->types[7] = _DRM_STAT_PRIMARY;
 131         dev->types[8] = _DRM_STAT_SECONDARY;
 132         dev->types[9] = _DRM_STAT_DMA;
 133
 134         if (IS_MOBILE(dev) || IS_I9XX(dev))
 135                 dev_priv->cursor_needs_physical = true;
 136         else
 137                 dev_priv->cursor_needs_physical = false;
 138
 139         if (IS_I965G(dev) || IS_G33(dev))
 140                 dev_priv->cursor_needs_physical = false;
 141
 142         if (IS_I9XX(dev)) {
 143                 pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
 144                 DRM_DEBUG("stolen base %p\n", (void*)dev_priv->stolen_base);
 145         }
 146
 147         if (IS_I9XX(dev)) {
 148                 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
 149                 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
 150                 dev->mode_config.fb_base =
 151                         drm_get_resource_start(dev, 2) & 0xff000000;
 152         } else if (drm_get_resource_start(dev, 1)) {
 153                 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
 154                 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
 155                 dev->mode_config.fb_base =
 156                         drm_get_resource_start(dev, 0) & 0xff000000;
 157         } else {
 158                 DRM_ERROR("Unable to find MMIO registers\n");
 159                 return -ENODEV;
 160         }
 161
 162         DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
 163
 164         ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
 165                          _DRM_REGISTERS, _DRM_KERNEL|_DRM_READ_ONLY|_DRM_DRIVER, &dev_priv->mmio_map);
 166         if (ret != 0) {
 167                 DRM_ERROR("Cannot add mapping for MMIO registers\n");
 168                 return ret;
 169         }
 170
 171 #ifdef __linux__
 172 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
 173         intel_init_chipset_flush_compat(dev);
 174 #endif
 175 #endif
 176
 177         /*
 178          * Initialize the memory manager for local and AGP space
 179          */
 180         drm_bo_driver_init(dev);
 181
 182         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 183                 i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
 184                 printk("setting up %ld bytes of VRAM space\n", prealloc_size);
 185                 printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
 186                 drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT, 1);
 187                 drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT, (agp_size - prealloc_size) >> PAGE_SHIFT, 1);
 188
 189                 I915_WRITE(LP_RING + RING_LEN, 0);
 190                 I915_WRITE(LP_RING + RING_HEAD, 0);
 191                 I915_WRITE(LP_RING + RING_TAIL, 0);
 192
 193                 size = PRIMARY_RINGBUFFER_SIZE;
 194                 ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
 195                                                DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
 196                                                DRM_BO_FLAG_MEM_VRAM |
 197                                                DRM_BO_FLAG_NO_EVICT,
 198                                                DRM_BO_HINT_DONT_FENCE, 0x1, 0,
 199                                                &dev_priv->ring_buffer);
 200                 if (ret < 0) {
 201                         DRM_ERROR("Unable to allocate or pin ring buffer\n");
 202                         return -EINVAL;
 203                 }
 204
 205                 /* remap the buffer object properly */
 206                 dev_priv->ring.Start = dev_priv->ring_buffer->offset;
 207                 dev_priv->ring.End = dev_priv->ring.Start + size;
 208                 dev_priv->ring.Size = size;
 209                 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 210
 211                 /* FIXME: need wrapper with PCI mem checks */
 212                 ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
 213                                           (void **) &dev_priv->ring.virtual_start);
 214                 if (ret)
 215                         DRM_ERROR("error mapping ring buffer: %d\n", ret);
 216
 217                 DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
 218                           dev_priv->ring.virtual_start, dev_priv->ring.Size);
 219
 220         //
 221
 222                 memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
 223
 224                 I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
 225                 I915_WRITE(LP_RING + RING_LEN,
 226                            ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
 227                            (RING_NO_REPORT | RING_VALID));
 228
 229                 /* We are using separate values as placeholders for mechanisms for
 230                  * private backbuffer/depthbuffer usage.
 231                  */
 232                 dev_priv->use_mi_batchbuffer_start = 0;
 233
 234                 /* Allow hardware batchbuffers unless told otherwise.
 235                  */
 236                 dev_priv->allow_batchbuffer = 1;
 237
 238                 /* Program Hardware Status Page */
 239                 if (!IS_G33(dev)) {
 240                         dev_priv->status_page_dmah =
 241                                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 242
 243                         if (!dev_priv->status_page_dmah) {
 244                                 dev->dev_private = (void *)dev_priv;
 245                                 i915_dma_cleanup(dev);
 246                                 DRM_ERROR("Can not allocate hardware status page\n");
 247                                 return -ENOMEM;
 248                         }
 249                         dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 250                         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 251
 252                         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 253
 254                         I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
 255                 }
 256                 DRM_DEBUG("Enabled hardware status page\n");
 257
 258                 dev_priv->wq = create_singlethread_workqueue("i915");
 259                 if (dev_priv->wq == 0) {
 260                   DRM_DEBUG("Error\n");
 261                 }
 262
 263                 ret = intel_find_bios(dev);
 264                 if (ret) {
 265                         DRM_ERROR("failed to find VBT\n");
 266                         return -ENODEV;
 267                 }
 268
 269                 intel_modeset_init(dev);
 270                 drm_initial_config(dev, false);
 271
 272                 drm_mm_print(&dev->bm.man[DRM_BO_MEM_VRAM].manager, "VRAM");
 273                 drm_mm_print(&dev->bm.man[DRM_BO_MEM_TT].manager, "TT");
 274
 275                 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
 276                 if (!dev->devname)
 277                         return -ENOMEM;
 278
 279                 drm_irq_install(dev);
 280         }
 281
 282         return 0;
 283 }
 284
 285 int i915_driver_unload(struct drm_device *dev)
 286 {
 287         struct drm_i915_private *dev_priv = dev->dev_private;
 288
 289         I915_WRITE(LP_RING + RING_LEN, 0);
 290
 291         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 292                 drm_irq_uninstall(dev);
 293                 intel_modeset_cleanup(dev);
 294                 destroy_workqueue(dev_priv->wq);
 295         }
 296
 297 #if 0
 298         if (dev_priv->ring.virtual_start) {
 299                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 300         }
 301 #endif
 302         if (dev_priv->sarea_kmap.virtual) {
 303                 drm_bo_kunmap(&dev_priv->sarea_kmap);
 304                 dev_priv->sarea_kmap.virtual = NULL;
 305                 dev->sigdata.lock = NULL;
 306         }
 307
 308         if (dev_priv->sarea_bo) {
 309                 mutex_lock(&dev->struct_mutex);
 310                 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
 311                 mutex_unlock(&dev->struct_mutex);
 312                 dev_priv->sarea_bo = NULL;
 313         }
 314
 315         if (dev_priv->status_page_dmah) {
 316                 drm_pci_free(dev, dev_priv->status_page_dmah);
 317                 dev_priv->status_page_dmah = NULL;
 318                 dev_priv->hw_status_page = NULL;
 319                 dev_priv->dma_status_page = 0;
 320                 /* Need to rewrite hardware status page */
 321                 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
 322         }
 323
 324         if (dev_priv->status_gfx_addr) {
 325                 dev_priv->status_gfx_addr = 0;
 326                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 327                 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
 328         }
 329
 330         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 331                 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
 332                                     dev_priv->ring.virtual_start);
 333
 334                 DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
 335                 mutex_lock(&dev->struct_mutex);
 336                 drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
 337
 338                 if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1)) {
 339                         DRM_ERROR("Memory manager type 3 not clean. "
 340                                   "Delaying takedown\n");
 341                 }
 342                 if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
 343                         DRM_ERROR("Memory manager type 3 not clean. "
 344                                   "Delaying takedown\n");
 345                 }
 346                 mutex_unlock(&dev->struct_mutex);
 347         }
 348
 349         drm_bo_driver_finish(dev);
 350
 351 #ifdef __linux__
 352 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
 353         intel_init_chipset_flush_compat(dev);
 354 #endif
 355 #endif
 356
 357         DRM_DEBUG("%p\n", dev_priv->mmio_map);
 358         drm_rmmap(dev, dev_priv->mmio_map);
 359
 360         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 361
 362         dev->dev_private = NULL;
 363         return 0;
 364 }
 365
 366 int i915_master_create(struct drm_device *dev, struct drm_master *master)
 367 {
 368         struct drm_i915_master_private *master_priv;
 369         unsigned long sareapage;
 370         int ret;
 371
 372         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
 373         if (!master_priv)
 374                 return -ENOMEM;
 375
 376         /* prebuild the SAREA */
 377         sareapage = max(SAREA_MAX, PAGE_SIZE);
 378         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
 379                          &master_priv->sarea);
 380         if (ret) {
 381                 DRM_ERROR("SAREA setup failed\n");
 382                 return ret;
 383         }
 384         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
 385         master_priv->sarea_priv->pf_current_page = 0;
 386
 387         master->driver_priv = master_priv;
 388         return 0;
 389 }
 390
 391 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
 392 {
 393         struct drm_i915_master_private *master_priv = master->driver_priv;
 394
 395         if (!master_priv)
 396                 return;
 397
 398         if (master_priv->sarea)
 399                 drm_rmmap(dev, master_priv->sarea);
 400
 401         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
 402
 403         master->driver_priv = NULL;
 404 }
 405
 406 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 407 {
 408         struct drm_i915_private *dev_priv = dev->dev_private;
 409         if (drm_core_check_feature(dev, DRIVER_MODESET))
 410                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 411 }
 412
 413 void i915_driver_lastclose(struct drm_device * dev)
 414 {
 415         struct drm_i915_private *dev_priv = dev->dev_private;
 416
 417         if (drm_core_check_feature(dev, DRIVER_MODESET))
 418                 return;
 419
 420         if (dev_priv->agp_heap)
 421                 i915_mem_takedown(&(dev_priv->agp_heap));
 422
 423         i915_dma_cleanup(dev);
 424 }
 425
 426 int i915_driver_firstopen(struct drm_device *dev)
 427 {
 428         if (drm_core_check_feature(dev, DRIVER_MODESET))
 429                 return 0;
 430
 431         drm_bo_driver_init(dev);
 432         return 0;
 433 }