2 * Copyright (c) 2007 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
12 #include "drm_sarea.h"
17 * i915_probe_agp - get AGP bootup configuration
19 * @aperture_size: returns AGP aperture configured size
20 * @preallocated_size: returns size of BIOS preallocated AGP space
22 * Since Intel integrated graphics are UMA, the BIOS has to set aside
23 * some RAM for the framebuffer at early boot. This code figures out
24 * how much was set aside so we can use it for our own purposes.
26 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
27 unsigned long *preallocated_size)
29 struct pci_dev *bridge_dev;
31 unsigned long overhead;
33 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
35 DRM_ERROR("bridge device not found\n");
39 /* Get the fb aperture size and "stolen" memory amount. */
40 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
41 pci_dev_put(bridge_dev);
43 *aperture_size = 1024 * 1024;
44 *preallocated_size = 1024 * 1024;
46 switch (pdev->device) {
47 case PCI_DEVICE_ID_INTEL_82830_CGC:
48 case PCI_DEVICE_ID_INTEL_82845G_IG:
49 case PCI_DEVICE_ID_INTEL_82855GM_IG:
50 case PCI_DEVICE_ID_INTEL_82865_IG:
51 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
54 *aperture_size *= 128;
57 /* 9xx supports large sizes, just look at the length */
58 *aperture_size = pci_resource_len(pdev, 2);
63 * Some of the preallocated space is taken by the GTT
64 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
66 overhead = (*aperture_size / 1024) + 4096;
67 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
68 case INTEL_855_GMCH_GMS_STOLEN_1M:
69 break; /* 1M already */
70 case INTEL_855_GMCH_GMS_STOLEN_4M:
71 *preallocated_size *= 4;
73 case INTEL_855_GMCH_GMS_STOLEN_8M:
74 *preallocated_size *= 8;
76 case INTEL_855_GMCH_GMS_STOLEN_16M:
77 *preallocated_size *= 16;
79 case INTEL_855_GMCH_GMS_STOLEN_32M:
80 *preallocated_size *= 32;
82 case INTEL_915G_GMCH_GMS_STOLEN_48M:
83 *preallocated_size *= 48;
85 case INTEL_915G_GMCH_GMS_STOLEN_64M:
86 *preallocated_size *= 64;
88 case INTEL_855_GMCH_GMS_DISABLED:
89 DRM_ERROR("video memory is disabled\n");
92 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
93 tmp & INTEL_855_GMCH_GMS_MASK);
96 *preallocated_size -= overhead;
102 * i915_driver_load - setup chip and create an initial config
104 * @flags: startup flags
106 * The driver load routine has to do several things:
107 * - drive output discovery via intel_modeset_init()
108 * - initialize the memory manager
109 * - allocate initial config memory
110 * - setup the DRM framebuffer with the allocated memory
112 int i915_driver_load(drm_device_t *dev, unsigned long flags)
114 drm_i915_private_t *dev_priv;
115 unsigned long agp_size, prealloc_size;
116 unsigned long sareapage;
119 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
120 if (dev_priv == NULL)
121 return DRM_ERR(ENOMEM);
123 memset(dev_priv, 0, sizeof(drm_i915_private_t));
124 dev->dev_private = (void *)dev_priv;
125 // dev_priv->flags = flags;
127 /* i915 has 4 more counters */
129 dev->types[6] = _DRM_STAT_IRQ;
130 dev->types[7] = _DRM_STAT_PRIMARY;
131 dev->types[8] = _DRM_STAT_SECONDARY;
132 dev->types[9] = _DRM_STAT_DMA;
135 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
136 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
137 dev->mode_config.fb_base =
138 drm_get_resource_start(dev, 2) & 0xff000000;
139 } else if (drm_get_resource_start(dev, 1)) {
140 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
141 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
142 dev->mode_config.fb_base =
143 drm_get_resource_start(dev, 0) & 0xff000000;
145 DRM_ERROR("Unable to find MMIO registers\n");
149 DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
151 ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
152 _DRM_REGISTERS, _DRM_READ_ONLY|_DRM_DRIVER, &dev_priv->mmio_map);
154 DRM_ERROR("Cannot add mapping for MMIO registers\n");
158 /* prebuild the SAREA */
159 sareapage = max(SAREA_MAX, PAGE_SIZE);
160 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
163 DRM_ERROR("SAREA setup failed\n");
167 init_waitqueue_head(&dev->lock.lock_queue);
169 /* FIXME: assume sarea_priv is right after SAREA */
170 dev_priv->sarea_priv = dev_priv->sarea->handle + sizeof(drm_sarea_t);
173 * Initialize the memory manager for local and AGP space
175 drm_bo_driver_init(dev);
177 i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
178 DRM_DEBUG("setting up %ld bytes of VRAM space\n", prealloc_size);
179 drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT);
181 I915_WRITE(LP_RING + RING_LEN, 0);
182 I915_WRITE(LP_RING + RING_HEAD, 0);
183 I915_WRITE(LP_RING + RING_TAIL, 0);
185 size = PRIMARY_RINGBUFFER_SIZE;
186 ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
187 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
188 DRM_BO_FLAG_MEM_VRAM |
189 DRM_BO_FLAG_NO_EVICT,
190 DRM_BO_HINT_DONT_FENCE, 0x1, 0,
191 &dev_priv->ring_buffer);
193 DRM_ERROR("Unable to allocate ring buffer\n");
197 /* remap the buffer object properly */
198 dev_priv->ring.Start = dev_priv->ring_buffer->offset;
199 dev_priv->ring.End = dev_priv->ring.Start + size;
200 dev_priv->ring.Size = size;
201 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
203 /* FIXME: need wrapper with PCI mem checks */
204 ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
205 (void **) &dev_priv->ring.virtual_start);
207 DRM_ERROR("error mapping ring buffer: %d\n", ret);
209 DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
210 dev_priv->ring.virtual_start, dev_priv->ring.Size);
212 dev_priv->sarea_priv->pf_current_page = 0;
214 memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
216 I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
217 I915_WRITE(LP_RING + RING_LEN,
218 ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
219 (RING_NO_REPORT | RING_VALID));
221 /* We are using separate values as placeholders for mechanisms for
222 * private backbuffer/depthbuffer usage.
224 dev_priv->use_mi_batchbuffer_start = 0;
226 /* Allow hardware batchbuffers unless told otherwise.
228 dev_priv->allow_batchbuffer = 1;
230 /* Program Hardware Status Page */
232 dev_priv->status_page_dmah =
233 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
235 if (!dev_priv->status_page_dmah) {
236 dev->dev_private = (void *)dev_priv;
237 i915_dma_cleanup(dev);
238 DRM_ERROR("Can not allocate hardware status page\n");
239 return DRM_ERR(ENOMEM);
241 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
242 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
244 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
246 I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
248 DRM_DEBUG("Enabled hardware status page\n");
250 intel_modeset_init(dev);
251 drm_initial_config(dev, false);
256 int i915_driver_unload(drm_device_t *dev)
258 drm_i915_private_t *dev_priv = dev->dev_private;
260 if (dev_priv->ring.virtual_start) {
261 drm_core_ioremapfree(&dev_priv->ring.map, dev);
264 if (dev_priv->status_page_dmah) {
265 drm_pci_free(dev, dev_priv->status_page_dmah);
266 dev_priv->status_page_dmah = NULL;
267 dev_priv->hw_status_page = NULL;
268 dev_priv->dma_status_page = 0;
269 /* Need to rewrite hardware status page */
270 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
273 if (dev_priv->status_gfx_addr) {
274 dev_priv->status_gfx_addr = 0;
275 drm_core_ioremapfree(&dev_priv->hws_map, dev);
276 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
279 I915_WRITE(LP_RING + RING_LEN, 0);
281 intel_modeset_cleanup(dev);
283 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
284 dev_priv->ring.virtual_start);
286 DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
287 mutex_lock(&dev->struct_mutex);
288 drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
289 mutex_unlock(&dev->struct_mutex);
291 if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM)) {
292 DRM_ERROR("Memory manager type 3 not clean. "
293 "Delaying takedown\n");
296 drm_bo_driver_finish(dev);
298 DRM_DEBUG("%p, %p\n", dev_priv->mmio_map, dev_priv->sarea);
299 drm_rmmap(dev, dev_priv->mmio_map);
300 drm_rmmap(dev, dev_priv->sarea);
302 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
304 dev->dev_private = NULL;
308 void i915_driver_lastclose(drm_device_t * dev)
310 drm_i915_private_t *dev_priv = dev->dev_private;
312 i915_mem_takedown(&(dev_priv->agp_heap));
314 i915_dma_cleanup(dev);
317 void i915_driver_preclose(drm_device_t * dev, DRMFILE filp)
319 drm_i915_private_t *dev_priv = dev->dev_private;
320 i915_mem_release(dev, filp, dev_priv->agp_heap);