shared-core/i915_init.c

   1 /*
   2  * Copyright (c) 2007 Intel Corporation
   3  *   Jesse Barnes <jesse.barnes@intel.com>
   4  *
   5  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   6  *                   2004 Sylvain Meyer
   7  *
   8  * GPL/BSD dual license
   9  */
  10 #include "drmP.h"
  11 #include "drm.h"
  12 #include "drm_sarea.h"
  13 #include "i915_drm.h"
  14 #include "i915_drv.h"
  15 #include "intel_bios.h"
  16
  17 /**
  18  * i915_probe_agp - get AGP bootup configuration
  19  * @pdev: PCI device
  20  * @aperture_size: returns AGP aperture configured size
  21  * @preallocated_size: returns size of BIOS preallocated AGP space
  22  *
  23  * Since Intel integrated graphics are UMA, the BIOS has to set aside
  24  * some RAM for the framebuffer at early boot.  This code figures out
  25  * how much was set aside so we can use it for our own purposes.
  26  */
  27 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
  28                    unsigned long *preallocated_size)
  29 {
  30         struct pci_dev *bridge_dev;
  31         u16 tmp = 0;
  32         unsigned long overhead;
  33
  34         bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
  35         if (!bridge_dev) {
  36                 DRM_ERROR("bridge device not found\n");
  37                 return -1;
  38         }
  39
  40         /* Get the fb aperture size and "stolen" memory amount. */
  41         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
  42         pci_dev_put(bridge_dev);
  43
  44         *aperture_size = 1024 * 1024;
  45         *preallocated_size = 1024 * 1024;
  46
  47         switch (pdev->device) {
  48         case PCI_DEVICE_ID_INTEL_82830_CGC:
  49         case PCI_DEVICE_ID_INTEL_82845G_IG:
  50         case PCI_DEVICE_ID_INTEL_82855GM_IG:
  51         case PCI_DEVICE_ID_INTEL_82865_IG:
  52                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
  53                         *aperture_size *= 64;
  54                 else
  55                         *aperture_size *= 128;
  56                 break;
  57         default:
  58                 /* 9xx supports large sizes, just look at the length */
  59                 *aperture_size = pci_resource_len(pdev, 2);
  60                 break;
  61         }
  62
  63         /*
  64          * Some of the preallocated space is taken by the GTT
  65          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
  66          */
  67         overhead = (*aperture_size / 1024) + 4096;
  68         switch (tmp & INTEL_855_GMCH_GMS_MASK) {
  69         case INTEL_855_GMCH_GMS_STOLEN_1M:
  70                 break; /* 1M already */
  71         case INTEL_855_GMCH_GMS_STOLEN_4M:
  72                 *preallocated_size *= 4;
  73                 break;
  74         case INTEL_855_GMCH_GMS_STOLEN_8M:
  75                 *preallocated_size *= 8;
  76                 break;
  77         case INTEL_855_GMCH_GMS_STOLEN_16M:
  78                 *preallocated_size *= 16;
  79                 break;
  80         case INTEL_855_GMCH_GMS_STOLEN_32M:
  81                 *preallocated_size *= 32;
  82                 break;
  83         case INTEL_915G_GMCH_GMS_STOLEN_48M:
  84                 *preallocated_size *= 48;
  85                 break;
  86         case INTEL_915G_GMCH_GMS_STOLEN_64M:
  87                 *preallocated_size *= 64;
  88                 break;
  89         case INTEL_855_GMCH_GMS_DISABLED:
  90                 DRM_ERROR("video memory is disabled\n");
  91                 return -1;
  92         default:
  93                 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
  94                         tmp & INTEL_855_GMCH_GMS_MASK);
  95                 return -1;
  96         }
  97         *preallocated_size -= overhead;
  98
  99         return 0;
 100 }
 101
 102 int i915_load_modeset_init(struct drm_device *dev)
 103 {
 104         struct drm_i915_private *dev_priv = dev->dev_private;
 105         unsigned long agp_size, prealloc_size;
 106         int size, ret = 0;
 107
 108         i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
 109         printk("setting up %ld bytes of VRAM space\n", prealloc_size);
 110         printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
 111
 112         drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT, 1);
 113         drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT,
 114                        (agp_size - prealloc_size) >> PAGE_SHIFT, 1);
 115         I915_WRITE(PRB0_CTL, 0);
 116         I915_WRITE(PRB0_HEAD, 0);
 117         I915_WRITE(PRB0_TAIL, 0);
 118
 119         size = PRIMARY_RINGBUFFER_SIZE;
 120         ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
 121                         DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
 122                         DRM_BO_FLAG_MEM_VRAM |
 123                         DRM_BO_FLAG_NO_EVICT,
 124                         DRM_BO_HINT_DONT_FENCE, 0x1, 0,
 125                         &dev_priv->ring_buffer);
 126         if (ret < 0) {
 127                 DRM_ERROR("Unable to allocate or pin ring buffer\n");
 128                 goto clean_mm;
 129         }
 130
 131         /* remap the buffer object properly */
 132         dev_priv->ring.Start = dev_priv->ring_buffer->offset;
 133         dev_priv->ring.End = dev_priv->ring.Start + size;
 134         dev_priv->ring.Size = size;
 135         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
 136
 137         /* FIXME: need wrapper with PCI mem checks */
 138         ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
 139                                   (void **) &dev_priv->ring.virtual_start);
 140         if (ret) {
 141                 DRM_ERROR("error mapping ring buffer: %d\n", ret);
 142                 goto destroy_ringbuffer;
 143         }
 144
 145         DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
 146                         dev_priv->ring.virtual_start, dev_priv->ring.Size);
 147
 148         memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
 149         I915_WRITE(PRB0_START, dev_priv->ring.Start);
 150         I915_WRITE(PRB0_CTL, ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
 151                    (RING_NO_REPORT | RING_VALID));
 152
 153         /* We are using separate values as placeholders for mechanisms for
 154          * private backbuffer/depthbuffer usage.
 155          */
 156         dev_priv->use_mi_batchbuffer_start = 0;
 157         if (IS_I965G(dev)) /* 965 doesn't support older method */
 158                 dev_priv->use_mi_batchbuffer_start = 1;
 159
 160         /* Allow hardware batchbuffers unless told otherwise.
 161          */
 162         dev_priv->allow_batchbuffer = 1;
 163         dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
 164         mutex_init(&dev_priv->cmdbuf_mutex);
 165
 166         /* Program Hardware Status Page */
 167         if (!IS_G33(dev)) {
 168                 dev_priv->status_page_dmah =
 169                         drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 170
 171                 if (!dev_priv->status_page_dmah) {
 172                         DRM_ERROR("Can not allocate hardware status page\n");
 173                         ret = -ENOMEM;
 174                         goto destroy_ringbuffer;
 175                 }
 176                 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
 177                 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 178
 179                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 180
 181                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 182         } else {
 183                 size = 4 * 1024;
 184                 ret = drm_buffer_object_create(dev, size,
 185                                 drm_bo_type_kernel,
 186                                 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
 187                                 DRM_BO_FLAG_MEM_VRAM |
 188                                 DRM_BO_FLAG_NO_EVICT,
 189                                 DRM_BO_HINT_DONT_FENCE, 0x1, 0,
 190                                 &dev_priv->hws_bo);
 191                 if (ret < 0) {
 192                         DRM_ERROR("Unable to allocate or pin hw status page\n");
 193                         ret = -EINVAL;
 194                         goto destroy_ringbuffer;
 195                 }
 196
 197                 dev_priv->status_gfx_addr =
 198                         dev_priv->hws_bo->offset & (0x1ffff << 12);
 199                 dev_priv->hws_map.offset = dev->agp->base +
 200                         dev_priv->hws_bo->offset;
 201                 dev_priv->hws_map.size = size;
 202                 dev_priv->hws_map.type= 0;
 203                 dev_priv->hws_map.flags= 0;
 204                 dev_priv->hws_map.mtrr = 0;
 205
 206                 drm_core_ioremap(&dev_priv->hws_map, dev);
 207                 if (dev_priv->hws_map.handle == NULL) {
 208                         dev_priv->status_gfx_addr = 0;
 209                         DRM_ERROR("can not ioremap virtual addr for"
 210                                         "G33 hw status page\n");
 211                         ret = -ENOMEM;
 212                         goto destroy_hws;
 213                 }
 214                 dev_priv->hw_status_page = dev_priv->hws_map.handle;
 215                 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 216                 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
 217         }
 218         DRM_DEBUG("Enabled hardware status page\n");
 219
 220         dev_priv->wq = create_singlethread_workqueue("i915");
 221         if (dev_priv->wq == 0) {
 222                 DRM_DEBUG("Error\n");
 223                 ret = -EINVAL;
 224                 goto destroy_hws;
 225         }
 226
 227         ret = intel_init_bios(dev);
 228         if (ret) {
 229                 DRM_ERROR("failed to find VBIOS tables\n");
 230                 ret = -ENODEV;
 231                 goto destroy_wq;
 232         }
 233
 234         intel_modeset_init(dev);
 235         drm_initial_config(dev, false);
 236
 237         drm_mm_print(&dev->bm.man[DRM_BO_MEM_VRAM].manager, "VRAM");
 238         drm_mm_print(&dev->bm.man[DRM_BO_MEM_TT].manager, "TT");
 239
 240         dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
 241         if (!dev->devname) {
 242                 ret = -ENOMEM;
 243                 goto modeset_cleanup;
 244         }
 245
 246         ret = drm_irq_install(dev);
 247         if (ret) {
 248                 kfree(dev->devname);
 249                 goto modeset_cleanup;
 250         }
 251         return 0;
 252
 253 modeset_cleanup:
 254         intel_modeset_cleanup(dev);
 255 destroy_wq:
 256         destroy_workqueue(dev_priv->wq);
 257 destroy_hws:
 258         if (!IS_G33(dev)) {
 259                 if (dev_priv->status_page_dmah)
 260                         drm_pci_free(dev, dev_priv->status_page_dmah);
 261         } else {
 262                 if (dev_priv->hws_map.handle)
 263                         drm_core_ioremapfree(&dev_priv->hws_map, dev);
 264                 if (dev_priv->hws_bo)
 265                         drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
 266         }
 267         I915_WRITE(HWS_PGA, 0x1ffff000);
 268 destroy_ringbuffer:
 269         if (dev_priv->ring.virtual_start)
 270                 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
 271                                     dev_priv->ring.virtual_start);
 272         if (dev_priv->ring_buffer)
 273                 drm_bo_usage_deref_unlocked(&dev_priv->ring_buffer);
 274 clean_mm:
 275         drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1);
 276         drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1);
 277         return ret;
 278 }
 279
 280 /**
 281  * i915_driver_load - setup chip and create an initial config
 282  * @dev: DRM device
 283  * @flags: startup flags
 284  *
 285  * The driver load routine has to do several things:
 286  *   - drive output discovery via intel_modeset_init()
 287  *   - initialize the memory manager
 288  *   - allocate initial config memory
 289  *   - setup the DRM framebuffer with the allocated memory
 290  */
 291 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 292 {
 293         struct drm_i915_private *dev_priv;
 294         int ret = 0;
 295
 296         dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
 297         if (dev_priv == NULL)
 298                 return -ENOMEM;
 299
 300         memset(dev_priv, 0, sizeof(struct drm_i915_private));
 301         dev->dev_private = (void *)dev_priv;
 302 //      dev_priv->flags = flags;
 303
 304         /* i915 has 4 more counters */
 305         dev->counters += 4;
 306         dev->types[6] = _DRM_STAT_IRQ;
 307         dev->types[7] = _DRM_STAT_PRIMARY;
 308         dev->types[8] = _DRM_STAT_SECONDARY;
 309         dev->types[9] = _DRM_STAT_DMA;
 310
 311         if (IS_MOBILE(dev) || IS_I9XX(dev))
 312                 dev_priv->cursor_needs_physical = true;
 313         else
 314                 dev_priv->cursor_needs_physical = false;
 315
 316         if (IS_I965G(dev) || IS_G33(dev))
 317                 dev_priv->cursor_needs_physical = false;
 318
 319         if (IS_I9XX(dev)) {
 320                 pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
 321                 DRM_DEBUG("stolen base %p\n", (void*)dev_priv->stolen_base);
 322         }
 323
 324         if (IS_I9XX(dev)) {
 325                 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
 326                 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
 327                 dev->mode_config.fb_base =
 328                         drm_get_resource_start(dev, 2) & 0xff000000;
 329         } else if (drm_get_resource_start(dev, 1)) {
 330                 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
 331                 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
 332                 dev->mode_config.fb_base =
 333                         drm_get_resource_start(dev, 0) & 0xff000000;
 334         } else {
 335                 DRM_ERROR("Unable to find MMIO registers\n");
 336                 ret = -ENODEV;
 337                 goto free_priv;
 338         }
 339
 340         DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
 341
 342         ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
 343                          _DRM_REGISTERS, _DRM_KERNEL|_DRM_READ_ONLY|_DRM_DRIVER,
 344                          &dev_priv->mmio_map);
 345         if (ret != 0) {
 346                 DRM_ERROR("Cannot add mapping for MMIO registers\n");
 347                 goto free_priv;
 348         }
 349
 350 #ifdef __linux__
 351 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
 352         intel_init_chipset_flush_compat(dev);
 353 #endif
 354 #endif
 355
 356         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 357                 /*
 358                  * Initialize the memory manager for local and AGP space
 359                  */
 360                 ret = drm_bo_driver_init(dev);
 361                 if (ret) {
 362                         DRM_ERROR("fail to init memory manager for "
 363                                   "local & AGP space\n");
 364                         goto out_rmmap;
 365                 }
 366
 367                 ret = i915_load_modeset_init(dev);
 368                 if (ret < 0) {
 369                         DRM_ERROR("failed to init modeset\n");
 370                         goto driver_fini;
 371                 }
 372         }
 373         return 0;
 374
 375 driver_fini:
 376         drm_bo_driver_finish(dev);
 377 out_rmmap:
 378         drm_rmmap(dev, dev_priv->mmio_map);
 379 free_priv:
 380         drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
 381         return ret;
 382 }
 383
 384 int i915_driver_unload(struct drm_device *dev)
 385 {
 386         struct drm_i915_private *dev_priv = dev->dev_private;
 387
 388         I915_WRITE(PRB0_CTL, 0);
 389
 390         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 391                 drm_irq_uninstall(dev);
 392                 intel_modeset_cleanup(dev);
 393                 destroy_workqueue(dev_priv->wq);
 394         }
 395
 396 #if 0
 397         if (dev_priv->ring.virtual_start) {
 398                 drm_core_ioremapfree(&dev_priv->ring.map, dev);
 399         }
 400 #endif
 401         if (dev_priv->sarea_kmap.virtual) {
 402                 drm_bo_kunmap(&dev_priv->sarea_kmap);
 403                 dev_priv->sarea_kmap.virtual = NULL;
 404                 dev->sigdata.lock = NULL;
 405         }
 406
 407         if (dev_priv->sarea_bo) {
 408                 mutex_lock(&dev->struct_mutex);
 409                 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
 410                 mutex_unlock(&dev->struct_mutex);
 411                 dev_priv->sarea_bo = NULL;
 412         }
 413
 414         if (dev_priv->status_page_dmah) {
 415                 drm_pci_free(dev, dev_priv->status_page_dmah);
 416                 dev_priv->status_page_dmah = NULL;
 417                 dev_priv->hw_status_page = NULL;
 418                 dev_priv->dma_status_page = 0;
 419                 /* Need to rewrite hardware status page */
 420                 I915_WRITE(HWS_PGA, 0x1ffff000);
 421         }
 422
 423         if (dev_priv->status_gfx_addr) {
 424                 dev_priv->status_gfx_addr = 0;
 425                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 426                 drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
 427                 I915_WRITE(HWS_PGA, 0x1ffff000);
 428         }
 429
 430         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 431                 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
 432                                     dev_priv->ring.virtual_start);
 433
 434                 DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
 435                 mutex_lock(&dev->struct_mutex);
 436                 drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
 437
 438                 if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1)) {
 439                         DRM_ERROR("Memory manager type 3 not clean. "
 440                                   "Delaying takedown\n");
 441                 }
 442                 if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
 443                         DRM_ERROR("Memory manager type 3 not clean. "
 444                                   "Delaying takedown\n");
 445                 }
 446                 mutex_unlock(&dev->struct_mutex);
 447         }
 448
 449         drm_bo_driver_finish(dev);
 450
 451 #ifdef __linux__
 452 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
 453         intel_init_chipset_flush_compat(dev);
 454 #endif
 455 #endif
 456
 457         DRM_DEBUG("%p\n", dev_priv->mmio_map);
 458         drm_rmmap(dev, dev_priv->mmio_map);
 459
 460         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
 461
 462         dev->dev_private = NULL;
 463         return 0;
 464 }
 465
 466 int i915_master_create(struct drm_device *dev, struct drm_master *master)
 467 {
 468         struct drm_i915_master_private *master_priv;
 469         unsigned long sareapage;
 470         int ret;
 471
 472         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
 473         if (!master_priv)
 474                 return -ENOMEM;
 475
 476         /* prebuild the SAREA */
 477         sareapage = max(SAREA_MAX, PAGE_SIZE);
 478         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
 479                          &master_priv->sarea);
 480         if (ret) {
 481                 DRM_ERROR("SAREA setup failed\n");
 482                 return ret;
 483         }
 484         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
 485         master_priv->sarea_priv->pf_current_page = 0;
 486
 487         master->driver_priv = master_priv;
 488         return 0;
 489 }
 490
 491 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
 492 {
 493         struct drm_i915_master_private *master_priv = master->driver_priv;
 494
 495         if (!master_priv)
 496                 return;
 497
 498         if (master_priv->sarea)
 499                 drm_rmmap(dev, master_priv->sarea);
 500
 501         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
 502
 503         master->driver_priv = NULL;
 504 }
 505
 506 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
 507 {
 508         struct drm_i915_private *dev_priv = dev->dev_private;
 509         if (drm_core_check_feature(dev, DRIVER_MODESET))
 510                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
 511 }
 512
 513 void i915_driver_lastclose(struct drm_device * dev)
 514 {
 515         struct drm_i915_private *dev_priv = dev->dev_private;
 516
 517         if (drm_core_check_feature(dev, DRIVER_MODESET))
 518                 return;
 519
 520         if (dev_priv->agp_heap)
 521                 i915_mem_takedown(&(dev_priv->agp_heap));
 522
 523         i915_dma_cleanup(dev);
 524 }
 525
 526 int i915_driver_firstopen(struct drm_device *dev)
 527 {
 528         if (drm_core_check_feature(dev, DRIVER_MODESET))
 529                 return 0;
 530
 531         drm_bo_driver_init(dev);
 532         return 0;
 533 }