2 * Copyright (c) 2007 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
12 #include "drm_sarea.h"
15 #include "intel_bios.h"
18 * i915_probe_agp - get AGP bootup configuration
20 * @aperture_size: returns AGP aperture configured size
21 * @preallocated_size: returns size of BIOS preallocated AGP space
23 * Since Intel integrated graphics are UMA, the BIOS has to set aside
24 * some RAM for the framebuffer at early boot. This code figures out
25 * how much was set aside so we can use it for our own purposes.
27 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
28 unsigned long *preallocated_size)
30 struct pci_dev *bridge_dev;
32 unsigned long overhead;
34 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
36 DRM_ERROR("bridge device not found\n");
40 /* Get the fb aperture size and "stolen" memory amount. */
41 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
42 pci_dev_put(bridge_dev);
44 *aperture_size = 1024 * 1024;
45 *preallocated_size = 1024 * 1024;
47 switch (pdev->device) {
48 case PCI_DEVICE_ID_INTEL_82830_CGC:
49 case PCI_DEVICE_ID_INTEL_82845G_IG:
50 case PCI_DEVICE_ID_INTEL_82855GM_IG:
51 case PCI_DEVICE_ID_INTEL_82865_IG:
52 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
55 *aperture_size *= 128;
58 /* 9xx supports large sizes, just look at the length */
59 *aperture_size = pci_resource_len(pdev, 2);
64 * Some of the preallocated space is taken by the GTT
65 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
67 overhead = (*aperture_size / 1024) + 4096;
68 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
69 case INTEL_855_GMCH_GMS_STOLEN_1M:
70 break; /* 1M already */
71 case INTEL_855_GMCH_GMS_STOLEN_4M:
72 *preallocated_size *= 4;
74 case INTEL_855_GMCH_GMS_STOLEN_8M:
75 *preallocated_size *= 8;
77 case INTEL_855_GMCH_GMS_STOLEN_16M:
78 *preallocated_size *= 16;
80 case INTEL_855_GMCH_GMS_STOLEN_32M:
81 *preallocated_size *= 32;
83 case INTEL_915G_GMCH_GMS_STOLEN_48M:
84 *preallocated_size *= 48;
86 case INTEL_915G_GMCH_GMS_STOLEN_64M:
87 *preallocated_size *= 64;
89 case INTEL_855_GMCH_GMS_DISABLED:
90 DRM_ERROR("video memory is disabled\n");
93 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
94 tmp & INTEL_855_GMCH_GMS_MASK);
97 *preallocated_size -= overhead;
102 int i915_load_modeset_init(struct drm_device *dev)
104 struct drm_i915_private *dev_priv = dev->dev_private;
105 unsigned long agp_size, prealloc_size;
108 i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
109 printk("setting up %ld bytes of VRAM space\n", prealloc_size);
110 printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
112 drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT, 1);
113 drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT,
114 (agp_size - prealloc_size) >> PAGE_SHIFT, 1);
115 I915_WRITE(PRB0_CTL, 0);
116 I915_WRITE(PRB0_HEAD, 0);
117 I915_WRITE(PRB0_TAIL, 0);
119 size = PRIMARY_RINGBUFFER_SIZE;
120 ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
121 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
122 DRM_BO_FLAG_MEM_VRAM |
123 DRM_BO_FLAG_NO_EVICT,
124 DRM_BO_HINT_DONT_FENCE, 0x1, 0,
125 &dev_priv->ring_buffer);
127 DRM_ERROR("Unable to allocate or pin ring buffer\n");
131 /* remap the buffer object properly */
132 dev_priv->ring.Start = dev_priv->ring_buffer->offset;
133 dev_priv->ring.End = dev_priv->ring.Start + size;
134 dev_priv->ring.Size = size;
135 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
137 /* FIXME: need wrapper with PCI mem checks */
138 ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
139 (void **) &dev_priv->ring.virtual_start);
141 DRM_ERROR("error mapping ring buffer: %d\n", ret);
142 goto destroy_ringbuffer;
145 DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
146 dev_priv->ring.virtual_start, dev_priv->ring.Size);
148 memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
149 I915_WRITE(PRB0_START, dev_priv->ring.Start);
150 I915_WRITE(PRB0_CTL, ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
151 (RING_NO_REPORT | RING_VALID));
153 /* We are using separate values as placeholders for mechanisms for
154 * private backbuffer/depthbuffer usage.
156 dev_priv->use_mi_batchbuffer_start = 0;
157 if (IS_I965G(dev)) /* 965 doesn't support older method */
158 dev_priv->use_mi_batchbuffer_start = 1;
160 /* Allow hardware batchbuffers unless told otherwise.
162 dev_priv->allow_batchbuffer = 1;
163 dev_priv->max_validate_buffers = I915_MAX_VALIDATE_BUFFERS;
164 mutex_init(&dev_priv->cmdbuf_mutex);
166 /* Program Hardware Status Page */
168 dev_priv->status_page_dmah =
169 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
171 if (!dev_priv->status_page_dmah) {
172 DRM_ERROR("Can not allocate hardware status page\n");
174 goto destroy_ringbuffer;
176 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
177 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
179 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
181 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
184 ret = drm_buffer_object_create(dev, size,
186 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
187 DRM_BO_FLAG_MEM_VRAM |
188 DRM_BO_FLAG_NO_EVICT,
189 DRM_BO_HINT_DONT_FENCE, 0x1, 0,
192 DRM_ERROR("Unable to allocate or pin hw status page\n");
194 goto destroy_ringbuffer;
197 dev_priv->status_gfx_addr =
198 dev_priv->hws_bo->offset & (0x1ffff << 12);
199 dev_priv->hws_map.offset = dev->agp->base +
200 dev_priv->hws_bo->offset;
201 dev_priv->hws_map.size = size;
202 dev_priv->hws_map.type= 0;
203 dev_priv->hws_map.flags= 0;
204 dev_priv->hws_map.mtrr = 0;
206 drm_core_ioremap(&dev_priv->hws_map, dev);
207 if (dev_priv->hws_map.handle == NULL) {
208 dev_priv->status_gfx_addr = 0;
209 DRM_ERROR("can not ioremap virtual addr for"
210 "G33 hw status page\n");
214 dev_priv->hw_status_page = dev_priv->hws_map.handle;
215 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
216 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
218 DRM_DEBUG("Enabled hardware status page\n");
220 dev_priv->wq = create_singlethread_workqueue("i915");
221 if (dev_priv->wq == 0) {
222 DRM_DEBUG("Error\n");
227 ret = intel_find_bios(dev);
229 DRM_ERROR("failed to find VBT\n");
234 intel_modeset_init(dev);
235 drm_initial_config(dev, false);
237 drm_mm_print(&dev->bm.man[DRM_BO_MEM_VRAM].manager, "VRAM");
238 drm_mm_print(&dev->bm.man[DRM_BO_MEM_TT].manager, "TT");
240 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
243 goto modeset_cleanup;
246 ret = drm_irq_install(dev);
249 goto modeset_cleanup;
254 intel_modeset_cleanup(dev);
256 destroy_workqueue(dev_priv->wq);
259 if (dev_priv->status_page_dmah)
260 drm_pci_free(dev, dev_priv->status_page_dmah);
262 if (dev_priv->hws_map.handle)
263 drm_core_ioremapfree(&dev_priv->hws_map, dev);
264 if (dev_priv->hws_bo)
265 drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
267 I915_WRITE(HWS_PGA, 0x1ffff000);
269 if (dev_priv->ring.virtual_start)
270 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
271 dev_priv->ring.virtual_start);
272 if (dev_priv->ring_buffer)
273 drm_bo_usage_deref_unlocked(&dev_priv->ring_buffer);
275 drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1);
276 drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1);
281 * i915_driver_load - setup chip and create an initial config
283 * @flags: startup flags
285 * The driver load routine has to do several things:
286 * - drive output discovery via intel_modeset_init()
287 * - initialize the memory manager
288 * - allocate initial config memory
289 * - setup the DRM framebuffer with the allocated memory
291 int i915_driver_load(struct drm_device *dev, unsigned long flags)
293 struct drm_i915_private *dev_priv;
296 dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
297 if (dev_priv == NULL)
300 memset(dev_priv, 0, sizeof(struct drm_i915_private));
301 dev->dev_private = (void *)dev_priv;
302 // dev_priv->flags = flags;
304 /* i915 has 4 more counters */
306 dev->types[6] = _DRM_STAT_IRQ;
307 dev->types[7] = _DRM_STAT_PRIMARY;
308 dev->types[8] = _DRM_STAT_SECONDARY;
309 dev->types[9] = _DRM_STAT_DMA;
311 if (IS_MOBILE(dev) || IS_I9XX(dev))
312 dev_priv->cursor_needs_physical = true;
314 dev_priv->cursor_needs_physical = false;
316 if (IS_I965G(dev) || IS_G33(dev))
317 dev_priv->cursor_needs_physical = false;
320 pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
321 DRM_DEBUG("stolen base %p\n", (void*)dev_priv->stolen_base);
325 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
326 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
327 dev->mode_config.fb_base =
328 drm_get_resource_start(dev, 2) & 0xff000000;
329 } else if (drm_get_resource_start(dev, 1)) {
330 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
331 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
332 dev->mode_config.fb_base =
333 drm_get_resource_start(dev, 0) & 0xff000000;
335 DRM_ERROR("Unable to find MMIO registers\n");
340 DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
342 ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
343 _DRM_REGISTERS, _DRM_KERNEL|_DRM_READ_ONLY|_DRM_DRIVER,
344 &dev_priv->mmio_map);
346 DRM_ERROR("Cannot add mapping for MMIO registers\n");
351 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
352 intel_init_chipset_flush_compat(dev);
357 * Initialize the memory manager for local and AGP space
359 ret = drm_bo_driver_init(dev);
361 DRM_ERROR("fail to init memory manager for local & AGP space\n");
365 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
366 ret = i915_load_modeset_init(dev);
368 DRM_ERROR("failed to init modeset\n");
375 drm_bo_driver_finish(dev);
377 drm_rmmap(dev, dev_priv->mmio_map);
379 drm_free(dev_priv, sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
383 int i915_driver_unload(struct drm_device *dev)
385 struct drm_i915_private *dev_priv = dev->dev_private;
387 I915_WRITE(PRB0_CTL, 0);
389 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
390 drm_irq_uninstall(dev);
391 intel_modeset_cleanup(dev);
392 destroy_workqueue(dev_priv->wq);
396 if (dev_priv->ring.virtual_start) {
397 drm_core_ioremapfree(&dev_priv->ring.map, dev);
400 if (dev_priv->sarea_kmap.virtual) {
401 drm_bo_kunmap(&dev_priv->sarea_kmap);
402 dev_priv->sarea_kmap.virtual = NULL;
403 dev->sigdata.lock = NULL;
406 if (dev_priv->sarea_bo) {
407 mutex_lock(&dev->struct_mutex);
408 drm_bo_usage_deref_locked(&dev_priv->sarea_bo);
409 mutex_unlock(&dev->struct_mutex);
410 dev_priv->sarea_bo = NULL;
413 if (dev_priv->status_page_dmah) {
414 drm_pci_free(dev, dev_priv->status_page_dmah);
415 dev_priv->status_page_dmah = NULL;
416 dev_priv->hw_status_page = NULL;
417 dev_priv->dma_status_page = 0;
418 /* Need to rewrite hardware status page */
419 I915_WRITE(HWS_PGA, 0x1ffff000);
422 if (dev_priv->status_gfx_addr) {
423 dev_priv->status_gfx_addr = 0;
424 drm_core_ioremapfree(&dev_priv->hws_map, dev);
425 drm_bo_usage_deref_unlocked(&dev_priv->hws_bo);
426 I915_WRITE(HWS_PGA, 0x1ffff000);
429 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
430 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
431 dev_priv->ring.virtual_start);
433 DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
434 mutex_lock(&dev->struct_mutex);
435 drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
437 if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT, 1)) {
438 DRM_ERROR("Memory manager type 3 not clean. "
439 "Delaying takedown\n");
441 if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM, 1)) {
442 DRM_ERROR("Memory manager type 3 not clean. "
443 "Delaying takedown\n");
445 mutex_unlock(&dev->struct_mutex);
448 drm_bo_driver_finish(dev);
451 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,25)
452 intel_init_chipset_flush_compat(dev);
456 DRM_DEBUG("%p\n", dev_priv->mmio_map);
457 drm_rmmap(dev, dev_priv->mmio_map);
459 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
461 dev->dev_private = NULL;
465 int i915_master_create(struct drm_device *dev, struct drm_master *master)
467 struct drm_i915_master_private *master_priv;
468 unsigned long sareapage;
471 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
475 /* prebuild the SAREA */
476 sareapage = max(SAREA_MAX, PAGE_SIZE);
477 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
478 &master_priv->sarea);
480 DRM_ERROR("SAREA setup failed\n");
483 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
484 master_priv->sarea_priv->pf_current_page = 0;
486 master->driver_priv = master_priv;
490 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
492 struct drm_i915_master_private *master_priv = master->driver_priv;
497 if (master_priv->sarea)
498 drm_rmmap(dev, master_priv->sarea);
500 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
502 master->driver_priv = NULL;
505 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
507 struct drm_i915_private *dev_priv = dev->dev_private;
508 if (drm_core_check_feature(dev, DRIVER_MODESET))
509 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
512 void i915_driver_lastclose(struct drm_device * dev)
514 struct drm_i915_private *dev_priv = dev->dev_private;
516 if (drm_core_check_feature(dev, DRIVER_MODESET))
519 if (dev_priv->agp_heap)
520 i915_mem_takedown(&(dev_priv->agp_heap));
522 i915_dma_cleanup(dev);
525 int i915_driver_firstopen(struct drm_device *dev)
527 if (drm_core_check_feature(dev, DRIVER_MODESET))
530 drm_bo_driver_init(dev);