2 * Copyright (c) 2007 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
12 #include "drm_sarea.h"
17 * i915_probe_agp - get AGP bootup configuration
19 * @aperture_size: returns AGP aperture configured size
20 * @preallocated_size: returns size of BIOS preallocated AGP space
22 * Since Intel integrated graphics are UMA, the BIOS has to set aside
23 * some RAM for the framebuffer at early boot. This code figures out
24 * how much was set aside so we can use it for our own purposes.
26 int i915_probe_agp(struct pci_dev *pdev, unsigned long *aperture_size,
27 unsigned long *preallocated_size)
29 struct pci_dev *bridge_dev;
31 unsigned long overhead;
33 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
35 DRM_ERROR("bridge device not found\n");
39 /* Get the fb aperture size and "stolen" memory amount. */
40 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
41 pci_dev_put(bridge_dev);
43 *aperture_size = 1024 * 1024;
44 *preallocated_size = 1024 * 1024;
46 switch (pdev->device) {
47 case PCI_DEVICE_ID_INTEL_82830_CGC:
48 case PCI_DEVICE_ID_INTEL_82845G_IG:
49 case PCI_DEVICE_ID_INTEL_82855GM_IG:
50 case PCI_DEVICE_ID_INTEL_82865_IG:
51 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
54 *aperture_size *= 128;
57 /* 9xx supports large sizes, just look at the length */
58 *aperture_size = pci_resource_len(pdev, 2);
63 * Some of the preallocated space is taken by the GTT
64 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
66 overhead = (*aperture_size / 1024) + 4096;
67 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
68 case INTEL_855_GMCH_GMS_STOLEN_1M:
69 break; /* 1M already */
70 case INTEL_855_GMCH_GMS_STOLEN_4M:
71 *preallocated_size *= 4;
73 case INTEL_855_GMCH_GMS_STOLEN_8M:
74 *preallocated_size *= 8;
76 case INTEL_855_GMCH_GMS_STOLEN_16M:
77 *preallocated_size *= 16;
79 case INTEL_855_GMCH_GMS_STOLEN_32M:
80 *preallocated_size *= 32;
82 case INTEL_915G_GMCH_GMS_STOLEN_48M:
83 *preallocated_size *= 48;
85 case INTEL_915G_GMCH_GMS_STOLEN_64M:
86 *preallocated_size *= 64;
88 case INTEL_855_GMCH_GMS_DISABLED:
89 DRM_ERROR("video memory is disabled\n");
92 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
93 tmp & INTEL_855_GMCH_GMS_MASK);
96 *preallocated_size -= overhead;
102 * i915_driver_load - setup chip and create an initial config
104 * @flags: startup flags
106 * The driver load routine has to do several things:
107 * - drive output discovery via intel_modeset_init()
108 * - initialize the memory manager
109 * - allocate initial config memory
110 * - setup the DRM framebuffer with the allocated memory
112 int i915_driver_load(struct drm_device *dev, unsigned long flags)
114 struct drm_i915_private *dev_priv;
115 unsigned long agp_size, prealloc_size;
118 dev_priv = drm_alloc(sizeof(struct drm_i915_private), DRM_MEM_DRIVER);
119 if (dev_priv == NULL)
122 memset(dev_priv, 0, sizeof(struct drm_i915_private));
123 dev->dev_private = (void *)dev_priv;
124 // dev_priv->flags = flags;
126 /* i915 has 4 more counters */
128 dev->types[6] = _DRM_STAT_IRQ;
129 dev->types[7] = _DRM_STAT_PRIMARY;
130 dev->types[8] = _DRM_STAT_SECONDARY;
131 dev->types[9] = _DRM_STAT_DMA;
134 pci_read_config_dword(dev->pdev, 0x5C, &dev_priv->stolen_base);
135 DRM_DEBUG("stolen base %p\n", (void*)dev_priv->stolen_base);
139 dev_priv->mmiobase = drm_get_resource_start(dev, 0);
140 dev_priv->mmiolen = drm_get_resource_len(dev, 0);
141 dev->mode_config.fb_base =
142 drm_get_resource_start(dev, 2) & 0xff000000;
143 } else if (drm_get_resource_start(dev, 1)) {
144 dev_priv->mmiobase = drm_get_resource_start(dev, 1);
145 dev_priv->mmiolen = drm_get_resource_len(dev, 1);
146 dev->mode_config.fb_base =
147 drm_get_resource_start(dev, 0) & 0xff000000;
149 DRM_ERROR("Unable to find MMIO registers\n");
153 DRM_DEBUG("fb_base: 0x%08lx\n", dev->mode_config.fb_base);
155 ret = drm_addmap(dev, dev_priv->mmiobase, dev_priv->mmiolen,
156 _DRM_REGISTERS, _DRM_READ_ONLY|_DRM_DRIVER, &dev_priv->mmio_map);
158 DRM_ERROR("Cannot add mapping for MMIO registers\n");
163 * Initialize the memory manager for local and AGP space
165 drm_bo_driver_init(dev);
167 i915_probe_agp(dev->pdev, &agp_size, &prealloc_size);
168 printk("setting up %ld bytes of VRAM space\n", prealloc_size);
169 printk("setting up %ld bytes of TT space\n", (agp_size - prealloc_size));
170 drm_bo_init_mm(dev, DRM_BO_MEM_VRAM, 0, prealloc_size >> PAGE_SHIFT);
171 drm_bo_init_mm(dev, DRM_BO_MEM_TT, prealloc_size >> PAGE_SHIFT, (agp_size - prealloc_size) >> PAGE_SHIFT);
173 I915_WRITE(LP_RING + RING_LEN, 0);
174 I915_WRITE(LP_RING + RING_HEAD, 0);
175 I915_WRITE(LP_RING + RING_TAIL, 0);
177 size = PRIMARY_RINGBUFFER_SIZE;
178 ret = drm_buffer_object_create(dev, size, drm_bo_type_kernel,
179 DRM_BO_FLAG_READ | DRM_BO_FLAG_WRITE |
180 DRM_BO_FLAG_MEM_VRAM |
181 DRM_BO_FLAG_NO_EVICT,
182 DRM_BO_HINT_DONT_FENCE, 0x1, 0,
183 &dev_priv->ring_buffer);
185 DRM_ERROR("Unable to allocate or pin ring buffer\n");
189 /* remap the buffer object properly */
190 dev_priv->ring.Start = dev_priv->ring_buffer->offset;
191 dev_priv->ring.End = dev_priv->ring.Start + size;
192 dev_priv->ring.Size = size;
193 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
195 /* FIXME: need wrapper with PCI mem checks */
196 ret = drm_mem_reg_ioremap(dev, &dev_priv->ring_buffer->mem,
197 (void **) &dev_priv->ring.virtual_start);
199 DRM_ERROR("error mapping ring buffer: %d\n", ret);
201 DRM_DEBUG("ring start %08lX, %p, %08lX\n", dev_priv->ring.Start,
202 dev_priv->ring.virtual_start, dev_priv->ring.Size);
206 memset((void *)(dev_priv->ring.virtual_start), 0, dev_priv->ring.Size);
208 I915_WRITE(LP_RING + RING_START, dev_priv->ring.Start);
209 I915_WRITE(LP_RING + RING_LEN,
210 ((dev_priv->ring.Size - 4096) & RING_NR_PAGES) |
211 (RING_NO_REPORT | RING_VALID));
213 /* We are using separate values as placeholders for mechanisms for
214 * private backbuffer/depthbuffer usage.
216 dev_priv->use_mi_batchbuffer_start = 0;
218 /* Allow hardware batchbuffers unless told otherwise.
220 dev_priv->allow_batchbuffer = 1;
222 /* Program Hardware Status Page */
224 dev_priv->status_page_dmah =
225 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
227 if (!dev_priv->status_page_dmah) {
228 dev->dev_private = (void *)dev_priv;
229 i915_dma_cleanup(dev);
230 DRM_ERROR("Can not allocate hardware status page\n");
233 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
234 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
236 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
238 I915_WRITE(I915REG_HWS_PGA, dev_priv->dma_status_page);
240 DRM_DEBUG("Enabled hardware status page\n");
242 dev_priv->wq = create_singlethread_workqueue("i915");
244 DRM_DEBUG("Error\n");
248 intel_modeset_init(dev);
249 drm_initial_config(dev, false);
251 drm_mm_print(&dev->bm.man[DRM_BO_MEM_VRAM].manager, "VRAM");
252 drm_mm_print(&dev->bm.man[DRM_BO_MEM_TT].manager, "TT");
254 drm_irq_install(dev);
259 int i915_driver_unload(struct drm_device *dev)
261 struct drm_i915_private *dev_priv = dev->dev_private;
263 I915_WRITE(LP_RING + RING_LEN, 0);
265 intel_modeset_cleanup(dev);
268 if (dev_priv->ring.virtual_start) {
269 drm_core_ioremapfree(&dev_priv->ring.map, dev);
273 if (dev_priv->status_page_dmah) {
274 drm_pci_free(dev, dev_priv->status_page_dmah);
275 dev_priv->status_page_dmah = NULL;
276 dev_priv->hw_status_page = NULL;
277 dev_priv->dma_status_page = 0;
278 /* Need to rewrite hardware status page */
279 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
282 if (dev_priv->status_gfx_addr) {
283 dev_priv->status_gfx_addr = 0;
284 drm_core_ioremapfree(&dev_priv->hws_map, dev);
285 I915_WRITE(I915REG_HWS_PGA, 0x1ffff000);
288 drm_mem_reg_iounmap(dev, &dev_priv->ring_buffer->mem,
289 dev_priv->ring.virtual_start);
291 DRM_DEBUG("usage is %d\n", atomic_read(&dev_priv->ring_buffer->usage));
292 mutex_lock(&dev->struct_mutex);
293 drm_bo_usage_deref_locked(&dev_priv->ring_buffer);
295 if (drm_bo_clean_mm(dev, DRM_BO_MEM_TT)) {
296 DRM_ERROR("Memory manager type 3 not clean. "
297 "Delaying takedown\n");
299 if (drm_bo_clean_mm(dev, DRM_BO_MEM_VRAM)) {
300 DRM_ERROR("Memory manager type 3 not clean. "
301 "Delaying takedown\n");
303 mutex_unlock(&dev->struct_mutex);
305 drm_bo_driver_finish(dev);
307 DRM_DEBUG("%p\n", dev_priv->mmio_map);
308 drm_rmmap(dev, dev_priv->mmio_map);
310 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
312 dev->dev_private = NULL;
316 int i915_master_create(struct drm_device *dev, struct drm_master *master)
318 struct drm_i915_master_private *master_priv;
319 unsigned long sareapage;
322 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
326 /* prebuild the SAREA */
327 sareapage = max(SAREA_MAX, PAGE_SIZE);
328 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
329 &master_priv->sarea);
331 DRM_ERROR("SAREA setup failed\n");
334 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
335 master_priv->sarea_priv->pf_current_page = 0;
337 master->driver_priv = master_priv;
341 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
343 struct drm_i915_master_private *master_priv = master->driver_priv;
348 drm_rmmap(dev, master_priv->sarea);
349 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
351 master->driver_priv = NULL;