1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define MAX_NOPID ((u32)~0)
37 * i915_get_pipe - return the the pipe associated with a given plane
39 * @plane: plane to look for
41 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
42 * rather than a pipe number, since they may not always be equal. This routine
43 * maps the given @plane back to a pipe number.
46 i915_get_pipe(struct drm_device *dev, int plane)
48 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
51 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
53 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
57 * i915_get_plane - return the the plane associated with a given pipe
59 * @pipe: pipe to look for
61 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
62 * rather than a plane number, since they may not always be equal. This routine
63 * maps the given @pipe back to a plane number.
66 i915_get_plane(struct drm_device *dev, int pipe)
68 if (i915_get_pipe(dev, 0) == pipe)
74 * i915_pipe_enabled - check if a pipe is enabled
76 * @pipe: pipe to check
78 * Reading certain registers when the pipe is disabled can hang the chip.
79 * Use this routine to make sure the PLL is running and the pipe is active
80 * before reading such registers if unsure.
83 i915_pipe_enabled(struct drm_device *dev, int pipe)
85 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
86 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
88 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
95 * Emit a synchronous flip.
97 * This function must be called with the drawable spinlock held.
100 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
103 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
104 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
106 int pf_planes = 1 << plane;
108 DRM_SPINLOCK_ASSERT(&dev->drw_lock);
110 /* If the window is visible on the other plane, we have to flip on that
114 x1 = sarea_priv->planeA_x;
115 y1 = sarea_priv->planeA_y;
116 x2 = x1 + sarea_priv->planeA_w;
117 y2 = y1 + sarea_priv->planeA_h;
119 x1 = sarea_priv->planeB_x;
120 y1 = sarea_priv->planeB_y;
121 x2 = x1 + sarea_priv->planeB_w;
122 y2 = y1 + sarea_priv->planeB_h;
125 if (x2 > 0 && y2 > 0) {
126 int i, num_rects = drw->num_rects;
127 struct drm_clip_rect *rect = drw->rects;
129 for (i = 0; i < num_rects; i++)
130 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
131 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
138 i915_dispatch_flip(dev, pf_planes, 1);
142 * Emit blits for scheduled buffer swaps.
144 * This function will be called with the HW lock held.
146 static void i915_vblank_tasklet(struct drm_device *dev)
148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
149 struct list_head *list, *tmp, hits, *hit;
150 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
152 struct drm_drawable_info *drw;
153 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
154 u32 cpp = dev_priv->cpp, offsets[3];
155 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
156 XY_SRC_COPY_BLT_WRITE_ALPHA |
157 XY_SRC_COPY_BLT_WRITE_RGB)
158 : XY_SRC_COPY_BLT_CMD;
159 u32 src_pitch = sarea_priv->pitch * cpp;
160 u32 dst_pitch = sarea_priv->pitch * cpp;
161 /* COPY rop (0xcc), map cpp to magic color depth constants */
162 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
165 if (sarea_priv->front_tiled) {
166 cmd |= XY_SRC_COPY_BLT_DST_TILED;
169 if (sarea_priv->back_tiled) {
170 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
174 counter[0] = drm_vblank_count(dev, 0);
175 counter[1] = drm_vblank_count(dev, 1);
179 INIT_LIST_HEAD(&hits);
183 /* No irqsave/restore necessary. This tasklet may be run in an
184 * interrupt context or normal context, but we don't have to worry
185 * about getting interrupted by something acquiring the lock, because
186 * we are the interrupt context thing that acquires the lock.
188 DRM_SPINLOCK(&dev_priv->swaps_lock);
190 /* Find buffer swaps scheduled for this vertical blank */
191 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
192 drm_i915_vbl_swap_t *vbl_swap =
193 list_entry(list, drm_i915_vbl_swap_t, head);
194 int pipe = i915_get_pipe(dev, vbl_swap->plane);
196 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
200 dev_priv->swaps_pending--;
201 drm_vblank_put(dev, pipe);
203 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
204 DRM_SPINLOCK(&dev->drw_lock);
206 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
209 DRM_SPINUNLOCK(&dev->drw_lock);
210 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
211 DRM_SPINLOCK(&dev_priv->swaps_lock);
215 list_for_each(hit, &hits) {
216 drm_i915_vbl_swap_t *swap_cmp =
217 list_entry(hit, drm_i915_vbl_swap_t, head);
218 struct drm_drawable_info *drw_cmp =
219 drm_get_drawable_info(dev, swap_cmp->drw_id);
222 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
223 list_add_tail(list, hit);
228 DRM_SPINUNLOCK(&dev->drw_lock);
230 /* List of hits was empty, or we reached the end of it */
232 list_add_tail(list, hits.prev);
236 DRM_SPINLOCK(&dev_priv->swaps_lock);
239 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
245 i915_kernel_lost_context(dev);
247 upper[0] = upper[1] = 0;
248 slice[0] = max(sarea_priv->planeA_h / nhits, 1);
249 slice[1] = max(sarea_priv->planeB_h / nhits, 1);
250 lower[0] = sarea_priv->planeA_y + slice[0];
251 lower[1] = sarea_priv->planeB_y + slice[0];
253 offsets[0] = sarea_priv->front_offset;
254 offsets[1] = sarea_priv->back_offset;
255 offsets[2] = sarea_priv->third_offset;
256 num_pages = sarea_priv->third_handle ? 3 : 2;
258 DRM_SPINLOCK(&dev->drw_lock);
260 /* Emit blits for buffer swaps, partitioning both outputs into as many
261 * slices as there are buffer swaps scheduled in order to avoid tearing
262 * (based on the assumption that a single buffer swap would always
263 * complete before scanout starts).
265 for (i = 0; i++ < nhits;
266 upper[0] = lower[0], lower[0] += slice[0],
267 upper[1] = lower[1], lower[1] += slice[1]) {
268 int init_drawrect = 1;
271 lower[0] = lower[1] = sarea_priv->height;
273 list_for_each(hit, &hits) {
274 drm_i915_vbl_swap_t *swap_hit =
275 list_entry(hit, drm_i915_vbl_swap_t, head);
276 struct drm_clip_rect *rect;
277 int num_rects, plane, front, back;
278 unsigned short top, bottom;
280 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
285 plane = swap_hit->plane;
287 if (swap_hit->flip) {
288 i915_dispatch_vsync_flip(dev, drw, plane);
293 int width = sarea_priv->width;
294 int height = sarea_priv->height;
298 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
300 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
307 OUT_RING(GFX_OP_DRAWRECT_INFO);
310 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
317 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
324 bottom = lower[plane];
326 front = (dev_priv->sarea_priv->pf_current_page >>
328 back = (front + 1) % num_pages;
330 for (num_rects = drw->num_rects; num_rects--; rect++) {
331 int y1 = max(rect->y1, top);
332 int y2 = min(rect->y2, bottom);
340 OUT_RING(ropcpp | dst_pitch);
341 OUT_RING((y1 << 16) | rect->x1);
342 OUT_RING((y2 << 16) | rect->x2);
343 OUT_RING(offsets[front]);
344 OUT_RING((y1 << 16) | rect->x1);
346 OUT_RING(offsets[back]);
353 DRM_SPINUNLOCK(&dev->drw_lock);
355 list_for_each_safe(hit, tmp, &hits) {
356 drm_i915_vbl_swap_t *swap_hit =
357 list_entry(hit, drm_i915_vbl_swap_t, head);
361 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
365 static int i915_in_vblank(struct drm_device *dev, int pipe)
367 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
368 unsigned long pipedsl, vblank, vtotal;
369 unsigned long vbl_start, vbl_end, cur_line;
371 pipedsl = pipe ? PIPEBDSL : PIPEADSL;
372 vblank = pipe ? VBLANK_B : VBLANK_A;
373 vtotal = pipe ? VTOTAL_B : VTOTAL_A;
375 vbl_start = I915_READ(vblank) & VBLANK_START_MASK;
376 vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;
378 cur_line = I915_READ(pipedsl);
380 if (cur_line >= vbl_start)
386 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
388 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
389 unsigned long high_frame;
390 unsigned long low_frame;
391 u32 high1, high2, low, count;
394 pipe = i915_get_pipe(dev, plane);
395 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
396 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
398 if (!i915_pipe_enabled(dev, pipe)) {
399 printk(KERN_ERR "trying to get vblank count for disabled "
405 * High & low register fields aren't synchronized, so make sure
406 * we get a low value that's stable across two reads of the high
410 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
411 PIPE_FRAME_HIGH_SHIFT);
412 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
413 PIPE_FRAME_LOW_SHIFT);
414 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
415 PIPE_FRAME_HIGH_SHIFT);
416 } while (high1 != high2);
418 count = (high1 << 8) | low;
421 * If we're in the middle of the vblank period, the
422 * above regs won't have been updated yet, so return
423 * an incremented count to stay accurate
426 if (i915_in_vblank(dev, pipe))
429 /* count may be reset by other driver(e.g. 2D driver),
430 we have no way to know if it is wrapped or resetted
431 when count is zero. do a rough guess.
433 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
434 dev->last_vblank[pipe] = 0;
439 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
441 struct drm_device *dev = (struct drm_device *) arg;
442 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
444 u32 pipea_stats, pipeb_stats;
447 iir = I915_READ(I915REG_INT_IDENTITY_R);
449 DRM_DEBUG("flag=%08x\n", iir);
452 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
454 I915_READ(I915REG_INT_MASK_R),
455 I915_READ(I915REG_INT_ENABLE_R),
456 I915_READ(I915REG_PIPEASTAT),
457 I915_READ(I915REG_PIPEBSTAT));
462 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
463 * we may get extra interrupts.
465 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
466 pipea_stats = I915_READ(I915REG_PIPEASTAT);
467 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
468 I915_VBLANK_INTERRUPT_STATUS))
471 drm_handle_vblank(dev, i915_get_plane(dev, 0));
473 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
475 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
476 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
477 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
478 I915_VBLANK_INTERRUPT_STATUS))
481 drm_handle_vblank(dev, i915_get_plane(dev, 1));
483 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
486 if (dev_priv->sarea_priv)
487 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
489 I915_WRITE(I915REG_INT_IDENTITY_R, iir);
490 (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
492 if (iir & I915_USER_INTERRUPT) {
493 DRM_WAKEUP(&dev_priv->irq_queue);
494 #ifdef I915_HAVE_FENCE
495 i915_fence_handler(dev);
500 if (dev_priv->swaps_pending > 0)
501 drm_locked_tasklet(dev, i915_vblank_tasklet);
507 int i915_emit_irq(struct drm_device *dev)
509 drm_i915_private_t *dev_priv = dev->dev_private;
512 i915_kernel_lost_context(dev);
516 i915_emit_breadcrumb(dev);
520 OUT_RING(GFX_OP_USER_INTERRUPT);
523 return dev_priv->counter;
526 void i915_user_irq_on(drm_i915_private_t *dev_priv)
528 DRM_SPINLOCK(&dev_priv->user_irq_lock);
529 if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
530 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
531 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
533 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
537 void i915_user_irq_off(drm_i915_private_t *dev_priv)
539 DRM_SPINLOCK(&dev_priv->user_irq_lock);
540 if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
541 // dev_priv->irq_enable_reg &= ~USER_INT_FLAG;
542 // I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
544 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
548 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
550 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
553 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
554 READ_BREADCRUMB(dev_priv));
556 if (READ_BREADCRUMB(dev_priv) >= irq_nr)
559 i915_user_irq_on(dev_priv);
560 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
561 READ_BREADCRUMB(dev_priv) >= irq_nr);
562 i915_user_irq_off(dev_priv);
565 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
566 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
569 if (dev_priv->sarea_priv)
570 dev_priv->sarea_priv->last_dispatch =
571 READ_BREADCRUMB(dev_priv);
575 /* Needs the lock as it touches the ring.
577 int i915_irq_emit(struct drm_device *dev, void *data,
578 struct drm_file *file_priv)
580 drm_i915_private_t *dev_priv = dev->dev_private;
581 drm_i915_irq_emit_t *emit = data;
584 LOCK_TEST_WITH_RETURN(dev, file_priv);
587 DRM_ERROR("called with no initialization\n");
591 result = i915_emit_irq(dev);
593 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
594 DRM_ERROR("copy_to_user\n");
601 /* Doesn't need the hardware lock.
603 int i915_irq_wait(struct drm_device *dev, void *data,
604 struct drm_file *file_priv)
606 drm_i915_private_t *dev_priv = dev->dev_private;
607 drm_i915_irq_wait_t *irqwait = data;
610 DRM_ERROR("called with no initialization\n");
614 return i915_wait_irq(dev, irqwait->irq_seq);
617 int i915_enable_vblank(struct drm_device *dev, int plane)
619 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
620 int pipe = i915_get_pipe(dev, plane);
621 u32 pipestat_reg = 0;
626 pipestat_reg = I915REG_PIPEASTAT;
627 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
630 pipestat_reg = I915REG_PIPEBSTAT;
631 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
634 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
641 pipestat = I915_READ (pipestat_reg);
643 * Older chips didn't have the start vblank interrupt,
647 pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
649 pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
651 * Clear any pending status
653 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
654 I915_VBLANK_INTERRUPT_STATUS);
655 I915_WRITE(pipestat_reg, pipestat);
657 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
662 void i915_disable_vblank(struct drm_device *dev, int plane)
664 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
665 int pipe = i915_get_pipe(dev, plane);
666 u32 pipestat_reg = 0;
671 pipestat_reg = I915REG_PIPEASTAT;
672 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
675 pipestat_reg = I915REG_PIPEBSTAT;
676 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
679 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
684 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
687 pipestat = I915_READ (pipestat_reg);
688 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
689 I915_VBLANK_INTERRUPT_ENABLE);
691 * Clear any pending status
693 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
694 I915_VBLANK_INTERRUPT_STATUS);
695 I915_WRITE(pipestat_reg, pipestat);
699 static void i915_enable_interrupt (struct drm_device *dev)
701 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
703 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
705 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
706 dev_priv->irq_enabled = 1;
709 /* Set the vblank monitor pipe
711 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
712 struct drm_file *file_priv)
714 drm_i915_private_t *dev_priv = dev->dev_private;
715 drm_i915_vblank_pipe_t *pipe = data;
718 DRM_ERROR("called with no initialization\n");
722 if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
723 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
727 dev_priv->vblank_pipe = pipe->pipe;
732 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
733 struct drm_file *file_priv)
735 drm_i915_private_t *dev_priv = dev->dev_private;
736 drm_i915_vblank_pipe_t *pipe = data;
740 DRM_ERROR("called with no initialization\n");
744 flag = I915_READ(I915REG_INT_ENABLE_R);
746 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
747 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
748 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
749 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
755 * Schedule buffer swap at given vertical blank.
757 int i915_vblank_swap(struct drm_device *dev, void *data,
758 struct drm_file *file_priv)
760 drm_i915_private_t *dev_priv = dev->dev_private;
761 drm_i915_vblank_swap_t *swap = data;
762 drm_i915_vbl_swap_t *vbl_swap;
763 unsigned int pipe, seqtype, curseq, plane;
764 unsigned long irqflags;
765 struct list_head *list;
769 DRM_ERROR("%s called with no initialization\n", __func__);
773 if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
774 DRM_DEBUG("Rotation not supported\n");
778 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
779 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
781 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
785 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
786 pipe = i915_get_pipe(dev, plane);
788 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
790 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
791 DRM_ERROR("Invalid pipe %d\n", pipe);
795 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
797 /* It makes no sense to schedule a swap for a drawable that doesn't have
798 * valid information at this point. E.g. this could mean that the X
799 * server is too old to push drawable information to the DRM, in which
800 * case all such swaps would become ineffective.
802 if (!drm_get_drawable_info(dev, swap->drawable)) {
803 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
804 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
808 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
810 drm_update_vblank_count(dev, pipe);
811 curseq = drm_vblank_count(dev, pipe);
813 if (seqtype == _DRM_VBLANK_RELATIVE)
814 swap->sequence += curseq;
816 if ((curseq - swap->sequence) <= (1<<23)) {
817 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
818 swap->sequence = curseq + 1;
820 DRM_DEBUG("Missed target sequence\n");
825 if (swap->seqtype & _DRM_VBLANK_FLIP) {
828 if ((curseq - swap->sequence) <= (1<<23)) {
829 struct drm_drawable_info *drw;
831 LOCK_TEST_WITH_RETURN(dev, file_priv);
833 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
835 drw = drm_get_drawable_info(dev, swap->drawable);
838 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
840 DRM_DEBUG("Invalid drawable ID %d\n",
845 i915_dispatch_vsync_flip(dev, drw, plane);
847 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
853 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
855 list_for_each(list, &dev_priv->vbl_swaps.head) {
856 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
858 if (vbl_swap->drw_id == swap->drawable &&
859 vbl_swap->plane == plane &&
860 vbl_swap->sequence == swap->sequence) {
861 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
862 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
863 DRM_DEBUG("Already scheduled\n");
868 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
870 if (dev_priv->swaps_pending >= 100) {
871 DRM_DEBUG("Too many swaps queued\n");
875 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
878 DRM_ERROR("Failed to allocate memory to queue swap\n");
884 ret = drm_vblank_get(dev, pipe);
886 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
890 vbl_swap->drw_id = swap->drawable;
891 vbl_swap->plane = plane;
892 vbl_swap->sequence = swap->sequence;
893 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
898 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
900 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
901 dev_priv->swaps_pending++;
903 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
910 void i915_driver_irq_preinstall(struct drm_device * dev)
912 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
914 I915_WRITE16(I915REG_HWSTAM, 0xeffe);
915 I915_WRITE16(I915REG_INT_MASK_R, 0x0);
916 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
919 int i915_driver_irq_postinstall(struct drm_device * dev)
921 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
922 int ret, num_pipes = 2;
924 DRM_SPININIT(&dev_priv->swaps_lock, "swap");
925 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
926 dev_priv->swaps_pending = 0;
928 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
929 dev_priv->user_irq_refcount = 0;
930 dev_priv->irq_enable_reg = 0;
932 ret = drm_vblank_init(dev, num_pipes);
936 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
938 i915_enable_interrupt(dev);
939 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
942 * Initialize the hardware status page IRQ location.
945 I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
949 void i915_driver_irq_uninstall(struct drm_device * dev)
951 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
957 dev_priv->irq_enabled = 0;
958 I915_WRITE(I915REG_HWSTAM, 0xffffffff);
959 I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
960 I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
962 temp = I915_READ(I915REG_PIPEASTAT);
963 I915_WRITE(I915REG_PIPEASTAT, temp);
964 temp = I915_READ(I915REG_PIPEBSTAT);
965 I915_WRITE(I915REG_PIPEBSTAT, temp);
966 temp = I915_READ(I915REG_INT_IDENTITY_R);
967 I915_WRITE(I915REG_INT_IDENTITY_R, temp);