shared-core/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /**
  37  * i915_get_pipe - return the the pipe associated with a given plane
  38  * @dev: DRM device
  39  * @plane: plane to look for
  40  *
  41  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  42  * rather than a pipe number, since they may not always be equal.  This routine
  43  * maps the given @plane back to a pipe number.
  44  */
  45 static int
  46 i915_get_pipe(struct drm_device *dev, int plane)
  47 {
  48         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  49         u32 dspcntr;
  50
  51         dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
  52
  53         return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
  54 }
  55
  56 /**
  57  * i915_get_plane - return the the plane associated with a given pipe
  58  * @dev: DRM device
  59  * @pipe: pipe to look for
  60  *
  61  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  62  * rather than a plane number, since they may not always be equal.  This routine
  63  * maps the given @pipe back to a plane number.
  64  */
  65 static int
  66 i915_get_plane(struct drm_device *dev, int pipe)
  67 {
  68         if (i915_get_pipe(dev, 0) == pipe)
  69                 return 0;
  70         return 1;
  71 }
  72
  73 /**
  74  * i915_pipe_enabled - check if a pipe is enabled
  75  * @dev: DRM device
  76  * @pipe: pipe to check
  77  *
  78  * Reading certain registers when the pipe is disabled can hang the chip.
  79  * Use this routine to make sure the PLL is running and the pipe is active
  80  * before reading such registers if unsure.
  81  */
  82 static int
  83 i915_pipe_enabled(struct drm_device *dev, int pipe)
  84 {
  85         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
  86         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
  87
  88         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
  89                 return 1;
  90
  91         return 0;
  92 }
  93
  94 /**
  95  * Emit a synchronous flip.
  96  *
  97  * This function must be called with the drawable spinlock held.
  98  */
  99 static void
 100 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
 101                          int plane)
 102 {
 103         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 104         drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
 105         u16 x1, y1, x2, y2;
 106         int pf_planes = 1 << plane;
 107
 108         DRM_SPINLOCK_ASSERT(&dev->drw_lock);
 109
 110         /* If the window is visible on the other plane, we have to flip on that
 111          * plane as well.
 112          */
 113         if (plane == 1) {
 114                 x1 = sarea_priv->planeA_x;
 115                 y1 = sarea_priv->planeA_y;
 116                 x2 = x1 + sarea_priv->planeA_w;
 117                 y2 = y1 + sarea_priv->planeA_h;
 118         } else {
 119                 x1 = sarea_priv->planeB_x;
 120                 y1 = sarea_priv->planeB_y;
 121                 x2 = x1 + sarea_priv->planeB_w;
 122                 y2 = y1 + sarea_priv->planeB_h;
 123         }
 124
 125         if (x2 > 0 && y2 > 0) {
 126                 int i, num_rects = drw->num_rects;
 127                 struct drm_clip_rect *rect = drw->rects;
 128
 129                 for (i = 0; i < num_rects; i++)
 130                         if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
 131                               rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
 132                                 pf_planes = 0x3;
 133
 134                                 break;
 135                         }
 136         }
 137
 138         i915_dispatch_flip(dev, pf_planes, 1);
 139 }
 140
 141 /**
 142  * Emit blits for scheduled buffer swaps.
 143  *
 144  * This function will be called with the HW lock held.
 145  */
 146 static void i915_vblank_tasklet(struct drm_device *dev)
 147 {
 148         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 149         struct list_head *list, *tmp, hits, *hit;
 150         int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
 151         unsigned counter[2];
 152         struct drm_drawable_info *drw;
 153         drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
 154         u32 cpp = dev_priv->cpp,  offsets[3];
 155         u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
 156                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
 157                                 XY_SRC_COPY_BLT_WRITE_RGB)
 158                              : XY_SRC_COPY_BLT_CMD;
 159         u32 src_pitch = sarea_priv->pitch * cpp;
 160         u32 dst_pitch = sarea_priv->pitch * cpp;
 161         /* COPY rop (0xcc), map cpp to magic color depth constants */
 162         u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
 163         RING_LOCALS;
 164
 165         if (sarea_priv->front_tiled) {
 166                 cmd |= XY_SRC_COPY_BLT_DST_TILED;
 167                 dst_pitch >>= 2;
 168         }
 169         if (sarea_priv->back_tiled) {
 170                 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
 171                 src_pitch >>= 2;
 172         }
 173
 174         counter[0] = drm_vblank_count(dev, 0);
 175         counter[1] = drm_vblank_count(dev, 1);
 176
 177         DRM_DEBUG("\n");
 178
 179         INIT_LIST_HEAD(&hits);
 180
 181         nhits = nrects = 0;
 182
 183         /* No irqsave/restore necessary.  This tasklet may be run in an
 184          * interrupt context or normal context, but we don't have to worry
 185          * about getting interrupted by something acquiring the lock, because
 186          * we are the interrupt context thing that acquires the lock.
 187          */
 188         DRM_SPINLOCK(&dev_priv->swaps_lock);
 189
 190         /* Find buffer swaps scheduled for this vertical blank */
 191         list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
 192                 drm_i915_vbl_swap_t *vbl_swap =
 193                         list_entry(list, drm_i915_vbl_swap_t, head);
 194                 int pipe = i915_get_pipe(dev, vbl_swap->plane);
 195
 196                 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
 197                         continue;
 198
 199                 list_del(list);
 200                 dev_priv->swaps_pending--;
 201                 drm_vblank_put(dev, pipe);
 202
 203                 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
 204                 DRM_SPINLOCK(&dev->drw_lock);
 205
 206                 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
 207
 208                 if (!drw) {
 209                         DRM_SPINUNLOCK(&dev->drw_lock);
 210                         drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 211                         DRM_SPINLOCK(&dev_priv->swaps_lock);
 212                         continue;
 213                 }
 214
 215                 list_for_each(hit, &hits) {
 216                         drm_i915_vbl_swap_t *swap_cmp =
 217                                 list_entry(hit, drm_i915_vbl_swap_t, head);
 218                         struct drm_drawable_info *drw_cmp =
 219                                 drm_get_drawable_info(dev, swap_cmp->drw_id);
 220
 221                         if (drw_cmp &&
 222                             drw_cmp->rects[0].y1 > drw->rects[0].y1) {
 223                                 list_add_tail(list, hit);
 224                                 break;
 225                         }
 226                 }
 227
 228                 DRM_SPINUNLOCK(&dev->drw_lock);
 229
 230                 /* List of hits was empty, or we reached the end of it */
 231                 if (hit == &hits)
 232                         list_add_tail(list, hits.prev);
 233
 234                 nhits++;
 235
 236                 DRM_SPINLOCK(&dev_priv->swaps_lock);
 237         }
 238
 239         DRM_SPINUNLOCK(&dev_priv->swaps_lock);
 240
 241         if (nhits == 0) {
 242                 return;
 243         }
 244
 245         i915_kernel_lost_context(dev);
 246
 247         upper[0] = upper[1] = 0;
 248         slice[0] = max(sarea_priv->planeA_h / nhits, 1);
 249         slice[1] = max(sarea_priv->planeB_h / nhits, 1);
 250         lower[0] = sarea_priv->planeA_y + slice[0];
 251         lower[1] = sarea_priv->planeB_y + slice[0];
 252
 253         offsets[0] = sarea_priv->front_offset;
 254         offsets[1] = sarea_priv->back_offset;
 255         offsets[2] = sarea_priv->third_offset;
 256         num_pages = sarea_priv->third_handle ? 3 : 2;
 257
 258         DRM_SPINLOCK(&dev->drw_lock);
 259
 260         /* Emit blits for buffer swaps, partitioning both outputs into as many
 261          * slices as there are buffer swaps scheduled in order to avoid tearing
 262          * (based on the assumption that a single buffer swap would always
 263          * complete before scanout starts).
 264          */
 265         for (i = 0; i++ < nhits;
 266              upper[0] = lower[0], lower[0] += slice[0],
 267              upper[1] = lower[1], lower[1] += slice[1]) {
 268                 int init_drawrect = 1;
 269
 270                 if (i == nhits)
 271                         lower[0] = lower[1] = sarea_priv->height;
 272
 273                 list_for_each(hit, &hits) {
 274                         drm_i915_vbl_swap_t *swap_hit =
 275                                 list_entry(hit, drm_i915_vbl_swap_t, head);
 276                         struct drm_clip_rect *rect;
 277                         int num_rects, plane, front, back;
 278                         unsigned short top, bottom;
 279
 280                         drw = drm_get_drawable_info(dev, swap_hit->drw_id);
 281
 282                         if (!drw)
 283                                 continue;
 284
 285                         plane = swap_hit->plane;
 286
 287                         if (swap_hit->flip) {
 288                                 i915_dispatch_vsync_flip(dev, drw, plane);
 289                                 continue;
 290                         }
 291
 292                         if (init_drawrect) {
 293                                 int width  = sarea_priv->width;
 294                                 int height = sarea_priv->height;
 295                                 if (IS_I965G(dev)) {
 296                                         BEGIN_LP_RING(4);
 297
 298                                         OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 299                                         OUT_RING(0);
 300                                         OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
 301                                         OUT_RING(0);
 302
 303                                         ADVANCE_LP_RING();
 304                                 } else {
 305                                         BEGIN_LP_RING(6);
 306
 307                                         OUT_RING(GFX_OP_DRAWRECT_INFO);
 308                                         OUT_RING(0);
 309                                         OUT_RING(0);
 310                                         OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
 311                                         OUT_RING(0);
 312                                         OUT_RING(0);
 313
 314                                         ADVANCE_LP_RING();
 315                                 }
 316
 317                                 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
 318
 319                                 init_drawrect = 0;
 320                         }
 321
 322                         rect = drw->rects;
 323                         top = upper[plane];
 324                         bottom = lower[plane];
 325
 326                         front = (dev_priv->sarea_priv->pf_current_page >>
 327                                  (2 * plane)) & 0x3;
 328                         back = (front + 1) % num_pages;
 329
 330                         for (num_rects = drw->num_rects; num_rects--; rect++) {
 331                                 int y1 = max(rect->y1, top);
 332                                 int y2 = min(rect->y2, bottom);
 333
 334                                 if (y1 >= y2)
 335                                         continue;
 336
 337                                 BEGIN_LP_RING(8);
 338
 339                                 OUT_RING(cmd);
 340                                 OUT_RING(ropcpp | dst_pitch);
 341                                 OUT_RING((y1 << 16) | rect->x1);
 342                                 OUT_RING((y2 << 16) | rect->x2);
 343                                 OUT_RING(offsets[front]);
 344                                 OUT_RING((y1 << 16) | rect->x1);
 345                                 OUT_RING(src_pitch);
 346                                 OUT_RING(offsets[back]);
 347
 348                                 ADVANCE_LP_RING();
 349                         }
 350                 }
 351         }
 352
 353         DRM_SPINUNLOCK(&dev->drw_lock);
 354
 355         list_for_each_safe(hit, tmp, &hits) {
 356                 drm_i915_vbl_swap_t *swap_hit =
 357                         list_entry(hit, drm_i915_vbl_swap_t, head);
 358
 359                 list_del(hit);
 360
 361                 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
 362         }
 363 }
 364 #if 0
 365 static int i915_in_vblank(struct drm_device *dev, int pipe)
 366 {
 367         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 368         unsigned long pipedsl, vblank, vtotal;
 369         unsigned long vbl_start, vbl_end, cur_line;
 370
 371         pipedsl = pipe ? PIPEBDSL : PIPEADSL;
 372         vblank = pipe ? VBLANK_B : VBLANK_A;
 373         vtotal = pipe ? VTOTAL_B : VTOTAL_A;
 374
 375         vbl_start = I915_READ(vblank) & VBLANK_START_MASK;
 376         vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;
 377
 378         cur_line = I915_READ(pipedsl);
 379
 380         if (cur_line >= vbl_start)
 381                 return 1;
 382
 383         return 0;
 384 }
 385 #endif
 386 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
 387 {
 388         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 389         unsigned long high_frame;
 390         unsigned long low_frame;
 391         u32 high1, high2, low, count;
 392         int pipe;
 393
 394         pipe = i915_get_pipe(dev, plane);
 395         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 396         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 397
 398         if (!i915_pipe_enabled(dev, pipe)) {
 399             DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 400             return 0;
 401         }
 402
 403         /*
 404          * High & low register fields aren't synchronized, so make sure
 405          * we get a low value that's stable across two reads of the high
 406          * register.
 407          */
 408         do {
 409                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 410                          PIPE_FRAME_HIGH_SHIFT);
 411                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 412                         PIPE_FRAME_LOW_SHIFT);
 413                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 414                          PIPE_FRAME_HIGH_SHIFT);
 415         } while (high1 != high2);
 416
 417         count = (high1 << 8) | low;
 418
 419         /*
 420          * If we're in the middle of the vblank period, the
 421          * above regs won't have been updated yet, so return
 422          * an incremented count to stay accurate
 423          */
 424 #if 0
 425         if (i915_in_vblank(dev, pipe))
 426                 count++;
 427 #endif
 428         /* count may be reset by other driver(e.g. 2D driver),
 429            we have no way to know if it is wrapped or resetted
 430            when count is zero. do a rough guess.
 431         */
 432         if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
 433                 dev->last_vblank[pipe] = 0;
 434
 435         return count;
 436 }
 437
 438 /**
 439  * Handler for user interrupts in process context (able to sleep, do VFS
 440  * operations, etc.
 441  *
 442  * If another IRQ comes in while we're in this handler, it will still get put
 443  * on the queue again to be rerun when we finish.
 444  */
 445 void
 446 i915_user_interrupt_handler(struct work_struct *work)
 447 {
 448         drm_i915_private_t *dev_priv;
 449         struct drm_device *dev;
 450
 451         dev_priv = container_of(work, drm_i915_private_t,
 452                                 user_interrupt_task);
 453         dev = dev_priv->dev;
 454
 455         mutex_lock(&dev->struct_mutex);
 456         i915_gem_retire_requests(dev);
 457         mutex_unlock(&dev->struct_mutex);
 458 }
 459
 460 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 461 {
 462         struct drm_device *dev = (struct drm_device *) arg;
 463         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 464         u32 iir;
 465         u32 pipea_stats, pipeb_stats;
 466         int vblank = 0;
 467
 468         iir = I915_READ(I915REG_INT_IDENTITY_R);
 469 #if 0
 470         DRM_DEBUG("flag=%08x\n", iir);
 471 #endif
 472         if (iir == 0) {
 473                 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
 474                            iir,
 475                            I915_READ(I915REG_INT_MASK_R),
 476                            I915_READ(I915REG_INT_ENABLE_R),
 477                            I915_READ(I915REG_PIPEASTAT),
 478                            I915_READ(I915REG_PIPEBSTAT));
 479                 return IRQ_NONE;
 480         }
 481
 482         /*
 483          * Clear the PIPE(A|B)STAT regs before the IIR otherwise
 484          * we may get extra interrupts.
 485          */
 486         if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 487                 pipea_stats = I915_READ(I915REG_PIPEASTAT);
 488                 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
 489                                    I915_VBLANK_INTERRUPT_STATUS))
 490                 {
 491                         vblank++;
 492                         drm_handle_vblank(dev, i915_get_plane(dev, 0));
 493                 }
 494                 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
 495         }
 496         if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 497                 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
 498                 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
 499                                    I915_VBLANK_INTERRUPT_STATUS))
 500                 {
 501                         vblank++;
 502                         drm_handle_vblank(dev, i915_get_plane(dev, 1));
 503                 }
 504                 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
 505         }
 506
 507         if (dev_priv->sarea_priv)
 508             dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 509
 510         I915_WRITE(I915REG_INT_IDENTITY_R, iir | I915_USER_INTERRUPT);
 511         (void) I915_READ(I915REG_INT_IDENTITY_R); /* Flush posted write */
 512
 513         if (iir & I915_USER_INTERRUPT) {
 514                 DRM_WAKEUP(&dev_priv->irq_queue);
 515 #ifdef I915_HAVE_FENCE
 516                 i915_fence_handler(dev);
 517                 schedule_work(&dev_priv->user_interrupt_task);
 518 #endif
 519         }
 520
 521         if (vblank) {
 522                 if (dev_priv->swaps_pending > 0)
 523                         drm_locked_tasklet(dev, i915_vblank_tasklet);
 524         }
 525
 526         return IRQ_HANDLED;
 527 }
 528
 529 int i915_emit_irq(struct drm_device *dev)
 530 {
 531         drm_i915_private_t *dev_priv = dev->dev_private;
 532         RING_LOCALS;
 533
 534         i915_kernel_lost_context(dev);
 535
 536         DRM_DEBUG("\n");
 537
 538         i915_emit_breadcrumb(dev);
 539
 540         BEGIN_LP_RING(2);
 541         OUT_RING(0);
 542         OUT_RING(GFX_OP_USER_INTERRUPT);
 543         ADVANCE_LP_RING();
 544
 545         return dev_priv->counter;
 546 }
 547
 548 void i915_user_irq_on(drm_i915_private_t *dev_priv)
 549 {
 550         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 551         if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
 552                 dev_priv->irq_mask_reg &= ~I915_USER_INTERRUPT;
 553                 I915_WRITE(I915REG_INT_MASK_R, dev_priv->irq_mask_reg);
 554                 (void) I915_READ (I915REG_INT_ENABLE_R);
 555         }
 556         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 557
 558 }
 559
 560 void i915_user_irq_off(drm_i915_private_t *dev_priv)
 561 {
 562         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 563         BUG_ON(dev_priv->user_irq_refcount <= 0);
 564         if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
 565                 dev_priv->irq_mask_reg |= I915_USER_INTERRUPT;
 566                 I915_WRITE(I915REG_INT_MASK_R, dev_priv->irq_mask_reg);
 567                 (void) I915_READ(I915REG_INT_MASK_R);
 568         }
 569         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 570 }
 571
 572
 573 int i915_wait_irq(struct drm_device * dev, int irq_nr)
 574 {
 575         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 576         int ret = 0;
 577
 578         if (!dev_priv) {
 579                 DRM_ERROR("called with no initialization\n");
 580                 return -EINVAL;
 581         }
 582
 583         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 584                   READ_BREADCRUMB(dev_priv));
 585
 586         if (READ_BREADCRUMB(dev_priv) >= irq_nr)
 587                 return 0;
 588
 589         i915_user_irq_on(dev_priv);
 590         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 591                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 592         i915_user_irq_off(dev_priv);
 593
 594         if (ret == -EBUSY) {
 595                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 596                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 597         }
 598
 599         if (dev_priv->sarea_priv)
 600                 dev_priv->sarea_priv->last_dispatch =
 601                         READ_BREADCRUMB(dev_priv);
 602         return ret;
 603 }
 604
 605 /* Needs the lock as it touches the ring.
 606  */
 607 int i915_irq_emit(struct drm_device *dev, void *data,
 608                          struct drm_file *file_priv)
 609 {
 610         drm_i915_private_t *dev_priv = dev->dev_private;
 611         drm_i915_irq_emit_t *emit = data;
 612         int result;
 613
 614         LOCK_TEST_WITH_RETURN(dev, file_priv);
 615
 616         if (!dev_priv) {
 617                 DRM_ERROR("called with no initialization\n");
 618                 return -EINVAL;
 619         }
 620
 621         result = i915_emit_irq(dev);
 622
 623         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 624                 DRM_ERROR("copy_to_user\n");
 625                 return -EFAULT;
 626         }
 627
 628         return 0;
 629 }
 630
 631 /* Doesn't need the hardware lock.
 632  */
 633 int i915_irq_wait(struct drm_device *dev, void *data,
 634                   struct drm_file *file_priv)
 635 {
 636         drm_i915_private_t *dev_priv = dev->dev_private;
 637         drm_i915_irq_wait_t *irqwait = data;
 638
 639         if (!dev_priv) {
 640                 DRM_ERROR("called with no initialization\n");
 641                 return -EINVAL;
 642         }
 643
 644         return i915_wait_irq(dev, irqwait->irq_seq);
 645 }
 646
 647 int i915_enable_vblank(struct drm_device *dev, int plane)
 648 {
 649         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 650         int pipe = i915_get_pipe(dev, plane);
 651         u32     pipestat_reg = 0;
 652         u32     mask_reg = 0;
 653         u32     pipestat;
 654
 655         switch (pipe) {
 656         case 0:
 657                 pipestat_reg = I915REG_PIPEASTAT;
 658                 mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 659                 break;
 660         case 1:
 661                 pipestat_reg = I915REG_PIPEBSTAT;
 662                 mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 663                 break;
 664         default:
 665                 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
 666                           pipe);
 667                 break;
 668         }
 669
 670         if (pipestat_reg)
 671         {
 672                 pipestat = I915_READ (pipestat_reg);
 673                 /*
 674                  * Older chips didn't have the start vblank interrupt,
 675                  * but
 676                  */
 677                 if (IS_I965G (dev))
 678                         pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
 679                 else
 680                         pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
 681                 /*
 682                  * Clear any pending status
 683                  */
 684                 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
 685                              I915_VBLANK_INTERRUPT_STATUS);
 686                 I915_WRITE(pipestat_reg, pipestat);
 687         }
 688         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 689         dev_priv->irq_mask_reg &= ~mask_reg;
 690         I915_WRITE(I915REG_INT_MASK_R, dev_priv->irq_mask_reg);
 691         I915_READ(I915REG_INT_MASK_R);
 692         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 693
 694         return 0;
 695 }
 696
 697 void i915_disable_vblank(struct drm_device *dev, int plane)
 698 {
 699         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 700         int pipe = i915_get_pipe(dev, plane);
 701         u32     pipestat_reg = 0;
 702         u32     mask_reg = 0;
 703         u32     pipestat;
 704
 705         switch (pipe) {
 706         case 0:
 707                 pipestat_reg = I915REG_PIPEASTAT;
 708                 mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 709                 break;
 710         case 1:
 711                 pipestat_reg = I915REG_PIPEBSTAT;
 712                 mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 713                 break;
 714         default:
 715                 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
 716                           pipe);
 717                 break;
 718         }
 719
 720         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 721         dev_priv->irq_mask_reg |= mask_reg;
 722         I915_WRITE(I915REG_INT_MASK_R, dev_priv->irq_mask_reg);
 723         (void) I915_READ (I915REG_INT_MASK_R);
 724         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 725         if (pipestat_reg)
 726         {
 727                 pipestat = I915_READ (pipestat_reg);
 728                 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
 729                               I915_VBLANK_INTERRUPT_ENABLE);
 730                 /*
 731                  * Clear any pending status
 732                  */
 733                 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
 734                              I915_VBLANK_INTERRUPT_STATUS);
 735                 I915_WRITE(pipestat_reg, pipestat);
 736                 (void) I915_READ(pipestat_reg);
 737         }
 738 }
 739
 740 static void i915_enable_interrupt (struct drm_device *dev)
 741 {
 742         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 743
 744         dev_priv->irq_mask_reg = (I915_USER_INTERRUPT |
 745                                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
 746                                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
 747         I915_WRITE(I915REG_INT_MASK_R, dev_priv->irq_mask_reg);
 748         I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_mask_reg);
 749         (void) I915_READ (I915REG_INT_ENABLE_R);
 750         dev_priv->irq_enabled = 1;
 751 }
 752
 753 static void i915_disable_interrupt (struct drm_device *dev)
 754 {
 755         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 756
 757         I915_WRITE(I915REG_HWSTAM, 0xffffffff);
 758         I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
 759         I915_WRITE(I915REG_INT_ENABLE_R, 0);
 760         I915_WRITE(I915REG_INT_IDENTITY_R, 0xffffffff);
 761         (void) I915_READ (I915REG_INT_IDENTITY_R);
 762         dev_priv->irq_enabled = 0;
 763 }
 764
 765 /* Set the vblank monitor pipe
 766  */
 767 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 768                          struct drm_file *file_priv)
 769 {
 770         drm_i915_private_t *dev_priv = dev->dev_private;
 771         drm_i915_vblank_pipe_t *pipe = data;
 772
 773         if (!dev_priv) {
 774                 DRM_ERROR("called with no initialization\n");
 775                 return -EINVAL;
 776         }
 777
 778         if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
 779                 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
 780                 return -EINVAL;
 781         }
 782
 783         dev_priv->vblank_pipe = pipe->pipe;
 784
 785         return 0;
 786 }
 787
 788 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 789                          struct drm_file *file_priv)
 790 {
 791         drm_i915_private_t *dev_priv = dev->dev_private;
 792         drm_i915_vblank_pipe_t *pipe = data;
 793         u16 flag;
 794
 795         if (!dev_priv) {
 796                 DRM_ERROR("called with no initialization\n");
 797                 return -EINVAL;
 798         }
 799
 800         flag = I915_READ(I915REG_INT_ENABLE_R);
 801         pipe->pipe = 0;
 802         if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
 803                 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
 804         if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
 805                 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
 806
 807         return 0;
 808 }
 809
 810 /**
 811  * Schedule buffer swap at given vertical blank.
 812  */
 813 int i915_vblank_swap(struct drm_device *dev, void *data,
 814                      struct drm_file *file_priv)
 815 {
 816         drm_i915_private_t *dev_priv = dev->dev_private;
 817         drm_i915_vblank_swap_t *swap = data;
 818         drm_i915_vbl_swap_t *vbl_swap;
 819         unsigned int pipe, seqtype, curseq, plane;
 820         unsigned long irqflags;
 821         struct list_head *list;
 822         int ret;
 823
 824         if (!dev_priv) {
 825                 DRM_ERROR("%s called with no initialization\n", __func__);
 826                 return -EINVAL;
 827         }
 828
 829         if (!dev_priv->sarea_priv || dev_priv->sarea_priv->rotation) {
 830                 DRM_DEBUG("Rotation not supported\n");
 831                 return -EINVAL;
 832         }
 833
 834         if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
 835                              _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
 836                              _DRM_VBLANK_FLIP)) {
 837                 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
 838                 return -EINVAL;
 839         }
 840
 841         plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
 842         pipe = i915_get_pipe(dev, plane);
 843
 844         seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
 845
 846         if (!(dev_priv->vblank_pipe & (1 << pipe))) {
 847                 DRM_ERROR("Invalid pipe %d\n", pipe);
 848                 return -EINVAL;
 849         }
 850
 851         DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
 852
 853         /* It makes no sense to schedule a swap for a drawable that doesn't have
 854          * valid information at this point. E.g. this could mean that the X
 855          * server is too old to push drawable information to the DRM, in which
 856          * case all such swaps would become ineffective.
 857          */
 858         if (!drm_get_drawable_info(dev, swap->drawable)) {
 859                 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
 860                 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
 861                 return -EINVAL;
 862         }
 863
 864         DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
 865
 866         drm_update_vblank_count(dev, pipe);
 867         curseq = drm_vblank_count(dev, pipe);
 868
 869         if (seqtype == _DRM_VBLANK_RELATIVE)
 870                 swap->sequence += curseq;
 871
 872         if ((curseq - swap->sequence) <= (1<<23)) {
 873                 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
 874                         swap->sequence = curseq + 1;
 875                 } else {
 876                         DRM_DEBUG("Missed target sequence\n");
 877                         return -EINVAL;
 878                 }
 879         }
 880
 881         if (swap->seqtype & _DRM_VBLANK_FLIP) {
 882                 swap->sequence--;
 883
 884                 if ((curseq - swap->sequence) <= (1<<23)) {
 885                         struct drm_drawable_info *drw;
 886
 887                         LOCK_TEST_WITH_RETURN(dev, file_priv);
 888
 889                         DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
 890
 891                         drw = drm_get_drawable_info(dev, swap->drawable);
 892
 893                         if (!drw) {
 894                                 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
 895                                     irqflags);
 896                                 DRM_DEBUG("Invalid drawable ID %d\n",
 897                                           swap->drawable);
 898                                 return -EINVAL;
 899                         }
 900
 901                         i915_dispatch_vsync_flip(dev, drw, plane);
 902
 903                         DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
 904
 905                         return 0;
 906                 }
 907         }
 908
 909         DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
 910
 911         list_for_each(list, &dev_priv->vbl_swaps.head) {
 912                 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
 913
 914                 if (vbl_swap->drw_id == swap->drawable &&
 915                     vbl_swap->plane == plane &&
 916                     vbl_swap->sequence == swap->sequence) {
 917                         vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
 918                         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
 919                         DRM_DEBUG("Already scheduled\n");
 920                         return 0;
 921                 }
 922         }
 923
 924         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
 925
 926         if (dev_priv->swaps_pending >= 100) {
 927                 DRM_DEBUG("Too many swaps queued\n");
 928                 return -EBUSY;
 929         }
 930
 931         vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 932
 933         if (!vbl_swap) {
 934                 DRM_ERROR("Failed to allocate memory to queue swap\n");
 935                 return -ENOMEM;
 936         }
 937
 938         DRM_DEBUG("\n");
 939
 940         ret = drm_vblank_get(dev, pipe);
 941         if (ret) {
 942                 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 943                 return ret;
 944         }
 945
 946         vbl_swap->drw_id = swap->drawable;
 947         vbl_swap->plane = plane;
 948         vbl_swap->sequence = swap->sequence;
 949         vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
 950
 951         if (vbl_swap->flip)
 952                 swap->sequence++;
 953
 954         DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
 955
 956         list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
 957         dev_priv->swaps_pending++;
 958
 959         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
 960
 961         return 0;
 962 }
 963
 964 /* drm_dma.h hooks
 965 */
 966 void i915_driver_irq_preinstall(struct drm_device * dev)
 967 {
 968         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 969
 970         I915_WRITE(I915REG_HWSTAM, 0xffff);
 971         I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
 972         I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
 973         I915_WRITE(I915REG_INT_IDENTITY_R, 0xffffffff);
 974         (void) I915_READ(I915REG_INT_IDENTITY_R);
 975 }
 976
 977 int i915_driver_irq_postinstall(struct drm_device * dev)
 978 {
 979         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 980         int ret, num_pipes = 2;
 981
 982         DRM_SPININIT(&dev_priv->swaps_lock, "swap");
 983         INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
 984         dev_priv->swaps_pending = 0;
 985
 986         DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
 987         dev_priv->user_irq_refcount = 0;
 988         dev_priv->irq_mask_reg = 0;
 989
 990         ret = drm_vblank_init(dev, num_pipes);
 991         if (ret)
 992                 return ret;
 993
 994         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 995
 996         i915_enable_interrupt(dev);
 997         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 998
 999         /*
1000          * Initialize the hardware status page IRQ location.
1001          */
1002
1003         I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
1004         return 0;
1005 }
1006
1007 void i915_driver_irq_uninstall(struct drm_device * dev)
1008 {
1009         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1010         u32 temp;
1011
1012         if (!dev_priv)
1013                 return;
1014
1015         i915_disable_interrupt (dev);
1016
1017         temp = I915_READ(I915REG_PIPEASTAT);
1018         I915_WRITE(I915REG_PIPEASTAT, temp);
1019         temp = I915_READ(I915REG_PIPEBSTAT);
1020         I915_WRITE(I915REG_PIPEBSTAT, temp);
1021 }