shared-core/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "drm_crtc_helper.h"
  35
  36 #define MAX_NOPID ((u32)~0)
  37
  38 /*
  39  * These are the interrupts used by the driver
  40  */
  41 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
  42                                     I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
  43                                     I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  44
  45 static inline void
  46 i915_enable_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  47 {
  48         if ((dev_priv->irq_mask_reg & mask) != 0) {
  49                 dev_priv->irq_mask_reg &= ~mask;
  50                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  51                 (void) I915_READ(IMR);
  52         }
  53 }
  54
  55 static inline void
  56 i915_disable_irq(struct drm_i915_private *dev_priv, uint32_t mask)
  57 {
  58         if ((dev_priv->irq_mask_reg & mask) != mask) {
  59                 dev_priv->irq_mask_reg |= mask;
  60                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  61                 (void) I915_READ(IMR);
  62         }
  63 }
  64
  65 /**
  66  * i915_get_pipe - return the the pipe associated with a given plane
  67  * @dev: DRM device
  68  * @plane: plane to look for
  69  *
  70  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  71  * rather than a pipe number, since they may not always be equal.  This routine
  72  * maps the given @plane back to a pipe number.
  73  */
  74 static int
  75 i915_get_pipe(struct drm_device *dev, int plane)
  76 {
  77         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
  78         u32 dspcntr;
  79
  80         dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
  81
  82         return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
  83 }
  84
  85 /**
  86  * i915_get_plane - return the the plane associated with a given pipe
  87  * @dev: DRM device
  88  * @pipe: pipe to look for
  89  *
  90  * The Intel Mesa & 2D drivers call the vblank routines with a plane number
  91  * rather than a plane number, since they may not always be equal.  This routine
  92  * maps the given @pipe back to a plane number.
  93  */
  94 static int
  95 i915_get_plane(struct drm_device *dev, int pipe)
  96 {
  97         if (i915_get_pipe(dev, 0) == pipe)
  98                 return 0;
  99         return 1;
 100 }
 101
 102 /**
 103  * i915_pipe_enabled - check if a pipe is enabled
 104  * @dev: DRM device
 105  * @pipe: pipe to check
 106  *
 107  * Reading certain registers when the pipe is disabled can hang the chip.
 108  * Use this routine to make sure the PLL is running and the pipe is active
 109  * before reading such registers if unsure.
 110  */
 111 static int
 112 i915_pipe_enabled(struct drm_device *dev, int pipe)
 113 {
 114         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 115         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 116
 117         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 118                 return 1;
 119
 120         return 0;
 121 }
 122
 123 /**
 124  * Emit a synchronous flip.
 125  *
 126  * This function must be called with the drawable spinlock held.
 127  */
 128 static void
 129 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
 130                          int plane)
 131 {
 132         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 133         struct drm_i915_sarea *sarea_priv = master_priv->sarea_priv;
 134         u16 x1, y1, x2, y2;
 135         int pf_planes = 1 << plane;
 136
 137         DRM_SPINLOCK_ASSERT(&dev->drw_lock);
 138
 139         /* If the window is visible on the other plane, we have to flip on that
 140          * plane as well.
 141          */
 142         if (plane == 1) {
 143                 x1 = sarea_priv->planeA_x;
 144                 y1 = sarea_priv->planeA_y;
 145                 x2 = x1 + sarea_priv->planeA_w;
 146                 y2 = y1 + sarea_priv->planeA_h;
 147         } else {
 148                 x1 = sarea_priv->planeB_x;
 149                 y1 = sarea_priv->planeB_y;
 150                 x2 = x1 + sarea_priv->planeB_w;
 151                 y2 = y1 + sarea_priv->planeB_h;
 152         }
 153
 154         if (x2 > 0 && y2 > 0) {
 155                 int i, num_rects = drw->num_rects;
 156                 struct drm_clip_rect *rect = drw->rects;
 157
 158                 for (i = 0; i < num_rects; i++)
 159                         if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
 160                               rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
 161                                 pf_planes = 0x3;
 162
 163                                 break;
 164                         }
 165         }
 166
 167         i915_dispatch_flip(dev, pf_planes, 1);
 168 }
 169
 170 /**
 171  * Emit blits for scheduled buffer swaps.
 172  *
 173  * This function will be called with the HW lock held.
 174  */
 175 static void i915_vblank_tasklet(struct drm_device *dev)
 176 {
 177         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 178         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 179         struct list_head *list, *tmp, hits, *hit;
 180         int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
 181         unsigned counter[2];
 182         struct drm_drawable_info *drw;
 183         struct drm_i915_sarea *sarea_priv = master_priv->sarea_priv;
 184         u32 cpp = dev_priv->cpp,  offsets[3];
 185         u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
 186                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
 187                                 XY_SRC_COPY_BLT_WRITE_RGB)
 188                              : XY_SRC_COPY_BLT_CMD;
 189         u32 src_pitch = sarea_priv->pitch * cpp;
 190         u32 dst_pitch = sarea_priv->pitch * cpp;
 191         /* COPY rop (0xcc), map cpp to magic color depth constants */
 192         u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
 193         RING_LOCALS;
 194
 195         if (sarea_priv->front_tiled) {
 196                 cmd |= XY_SRC_COPY_BLT_DST_TILED;
 197                 dst_pitch >>= 2;
 198         }
 199         if (sarea_priv->back_tiled) {
 200                 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
 201                 src_pitch >>= 2;
 202         }
 203
 204         counter[0] = drm_vblank_count(dev, 0);
 205         counter[1] = drm_vblank_count(dev, 1);
 206
 207         DRM_DEBUG("\n");
 208
 209         INIT_LIST_HEAD(&hits);
 210
 211         nhits = nrects = 0;
 212
 213         /* No irqsave/restore necessary.  This tasklet may be run in an
 214          * interrupt context or normal context, but we don't have to worry
 215          * about getting interrupted by something acquiring the lock, because
 216          * we are the interrupt context thing that acquires the lock.
 217          */
 218         DRM_SPINLOCK(&dev_priv->swaps_lock);
 219
 220         /* Find buffer swaps scheduled for this vertical blank */
 221         list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
 222                 struct drm_i915_vbl_swap *vbl_swap =
 223                         list_entry(list, struct drm_i915_vbl_swap, head);
 224                 int pipe = i915_get_pipe(dev, vbl_swap->plane);
 225
 226                 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
 227                         continue;
 228
 229                 master_priv = vbl_swap->minor->master->driver_priv;
 230                 sarea_priv = master_priv->sarea_priv;
 231
 232                 list_del(list);
 233                 dev_priv->swaps_pending--;
 234                 drm_vblank_put(dev, pipe);
 235
 236                 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
 237                 DRM_SPINLOCK(&dev->drw_lock);
 238
 239                 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
 240
 241                 if (!drw) {
 242                         DRM_SPINUNLOCK(&dev->drw_lock);
 243                         drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
 244                         DRM_SPINLOCK(&dev_priv->swaps_lock);
 245                         continue;
 246                 }
 247
 248                 list_for_each(hit, &hits) {
 249                         struct drm_i915_vbl_swap *swap_cmp =
 250                                 list_entry(hit, struct drm_i915_vbl_swap, head);
 251                         struct drm_drawable_info *drw_cmp =
 252                                 drm_get_drawable_info(dev, swap_cmp->drw_id);
 253
 254                         if (drw_cmp &&
 255                             drw_cmp->rects[0].y1 > drw->rects[0].y1) {
 256                                 list_add_tail(list, hit);
 257                                 break;
 258                         }
 259                 }
 260
 261                 DRM_SPINUNLOCK(&dev->drw_lock);
 262
 263                 /* List of hits was empty, or we reached the end of it */
 264                 if (hit == &hits)
 265                         list_add_tail(list, hits.prev);
 266
 267                 nhits++;
 268
 269                 DRM_SPINLOCK(&dev_priv->swaps_lock);
 270         }
 271
 272         DRM_SPINUNLOCK(&dev_priv->swaps_lock);
 273
 274         if (nhits == 0) {
 275                 return;
 276         }
 277
 278         i915_kernel_lost_context(dev);
 279
 280         upper[0] = upper[1] = 0;
 281         slice[0] = max(sarea_priv->planeA_h / nhits, 1);
 282         slice[1] = max(sarea_priv->planeB_h / nhits, 1);
 283         lower[0] = sarea_priv->planeA_y + slice[0];
 284         lower[1] = sarea_priv->planeB_y + slice[0];
 285
 286         offsets[0] = sarea_priv->front_offset;
 287         offsets[1] = sarea_priv->back_offset;
 288         offsets[2] = sarea_priv->third_offset;
 289         num_pages = sarea_priv->third_handle ? 3 : 2;
 290
 291         DRM_SPINLOCK(&dev->drw_lock);
 292
 293         /* Emit blits for buffer swaps, partitioning both outputs into as many
 294          * slices as there are buffer swaps scheduled in order to avoid tearing
 295          * (based on the assumption that a single buffer swap would always
 296          * complete before scanout starts).
 297          */
 298         for (i = 0; i++ < nhits;
 299              upper[0] = lower[0], lower[0] += slice[0],
 300              upper[1] = lower[1], lower[1] += slice[1]) {
 301                 int init_drawrect = 1;
 302
 303                 if (i == nhits)
 304                         lower[0] = lower[1] = sarea_priv->height;
 305
 306                 list_for_each(hit, &hits) {
 307                         struct drm_i915_vbl_swap *swap_hit =
 308                                 list_entry(hit, struct drm_i915_vbl_swap, head);
 309                         struct drm_clip_rect *rect;
 310                         int num_rects, plane, front, back;
 311                         unsigned short top, bottom;
 312
 313                         drw = drm_get_drawable_info(dev, swap_hit->drw_id);
 314
 315                         if (!drw)
 316                                 continue;
 317
 318                         plane = swap_hit->plane;
 319
 320                         if (swap_hit->flip) {
 321                                 i915_dispatch_vsync_flip(dev, drw, plane);
 322                                 continue;
 323                         }
 324
 325                         if (init_drawrect) {
 326                                 int width  = sarea_priv->width;
 327                                 int height = sarea_priv->height;
 328                                 if (IS_I965G(dev)) {
 329                                         BEGIN_LP_RING(4);
 330
 331                                         OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 332                                         OUT_RING(0);
 333                                         OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
 334                                         OUT_RING(0);
 335
 336                                         ADVANCE_LP_RING();
 337                                 } else {
 338                                         BEGIN_LP_RING(6);
 339
 340                                         OUT_RING(GFX_OP_DRAWRECT_INFO);
 341                                         OUT_RING(0);
 342                                         OUT_RING(0);
 343                                         OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
 344                                         OUT_RING(0);
 345                                         OUT_RING(0);
 346
 347                                         ADVANCE_LP_RING();
 348                                 }
 349
 350                                 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
 351
 352                                 init_drawrect = 0;
 353                         }
 354
 355                         rect = drw->rects;
 356                         top = upper[plane];
 357                         bottom = lower[plane];
 358
 359                         front = (master_priv->sarea_priv->pf_current_page >>
 360                                  (2 * plane)) & 0x3;
 361                         back = (front + 1) % num_pages;
 362
 363                         for (num_rects = drw->num_rects; num_rects--; rect++) {
 364                                 int y1 = max(rect->y1, top);
 365                                 int y2 = min(rect->y2, bottom);
 366
 367                                 if (y1 >= y2)
 368                                         continue;
 369
 370                                 BEGIN_LP_RING(8);
 371
 372                                 OUT_RING(cmd);
 373                                 OUT_RING(ropcpp | dst_pitch);
 374                                 OUT_RING((y1 << 16) | rect->x1);
 375                                 OUT_RING((y2 << 16) | rect->x2);
 376                                 OUT_RING(offsets[front]);
 377                                 OUT_RING((y1 << 16) | rect->x1);
 378                                 OUT_RING(src_pitch);
 379                                 OUT_RING(offsets[back]);
 380
 381                                 ADVANCE_LP_RING();
 382                         }
 383                 }
 384         }
 385
 386         DRM_SPINUNLOCK(&dev->drw_lock);
 387
 388         list_for_each_safe(hit, tmp, &hits) {
 389                 struct drm_i915_vbl_swap *swap_hit =
 390                         list_entry(hit, struct drm_i915_vbl_swap, head);
 391
 392                 list_del(hit);
 393
 394                 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
 395         }
 396 }
 397 #if 0
 398 static int i915_in_vblank(struct drm_device *dev, int pipe)
 399 {
 400         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 401         unsigned long pipedsl, vblank, vtotal;
 402         unsigned long vbl_start, vbl_end, cur_line;
 403
 404         pipedsl = pipe ? PIPEBDSL : PIPEADSL;
 405         vblank = pipe ? VBLANK_B : VBLANK_A;
 406         vtotal = pipe ? VTOTAL_B : VTOTAL_A;
 407
 408         vbl_start = I915_READ(vblank) & VBLANK_START_MASK;
 409         vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;
 410
 411         cur_line = I915_READ(pipedsl);
 412
 413         if (cur_line >= vbl_start)
 414                 return 1;
 415
 416         return 0;
 417 }
 418 #endif
 419 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
 420 {
 421         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 422         unsigned long high_frame;
 423         unsigned long low_frame;
 424         u32 high1, high2, low, count;
 425         int pipe;
 426
 427         pipe = i915_get_pipe(dev, plane);
 428         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 429         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 430
 431         if (!i915_pipe_enabled(dev, pipe)) {
 432             DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 433             return 0;
 434         }
 435
 436         /*
 437          * High & low register fields aren't synchronized, so make sure
 438          * we get a low value that's stable across two reads of the high
 439          * register.
 440          */
 441         do {
 442                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 443                          PIPE_FRAME_HIGH_SHIFT);
 444                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 445                         PIPE_FRAME_LOW_SHIFT);
 446                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 447                          PIPE_FRAME_HIGH_SHIFT);
 448         } while (high1 != high2);
 449
 450         count = (high1 << 8) | low;
 451
 452         /*
 453          * If we're in the middle of the vblank period, the
 454          * above regs won't have been updated yet, so return
 455          * an incremented count to stay accurate
 456          */
 457 #if 0
 458         if (i915_in_vblank(dev, pipe))
 459                 count++;
 460 #endif
 461         /* count may be reset by other driver(e.g. 2D driver),
 462            we have no way to know if it is wrapped or resetted
 463            when count is zero. do a rough guess.
 464         */
 465         if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
 466                 dev->last_vblank[pipe] = 0;
 467
 468         return count;
 469 }
 470
 471 static struct drm_device *hotplug_dev;
 472
 473 /**
 474  * Handler for user interrupts in process context (able to sleep, do VFS
 475  * operations, etc.
 476  *
 477  * If another IRQ comes in while we're in this handler, it will still get put
 478  * on the queue again to be rerun when we finish.
 479  */
 480 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
 481 static void i915_hotplug_work_func(void *work)
 482 #else
 483 static void i915_hotplug_work_func(struct work_struct *work)
 484 #endif
 485 {
 486         struct drm_device *dev = hotplug_dev;
 487
 488         drm_helper_hotplug_stage_two(dev);
 489         drm_handle_hotplug(dev);
 490 }
 491
 492 static int i915_run_hotplug_tasklet(struct drm_device *dev, uint32_t stat)
 493 {
 494 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
 495         static DECLARE_WORK(hotplug, i915_hotplug_work_func, NULL);
 496 #else
 497         static DECLARE_WORK(hotplug, i915_hotplug_work_func);
 498 #endif
 499         struct drm_i915_private *dev_priv = dev->dev_private;
 500
 501         hotplug_dev = dev;
 502
 503         if (stat & TV_HOTPLUG_INT_STATUS) {
 504                 DRM_DEBUG("TV event\n");
 505         }
 506
 507         if (stat & CRT_HOTPLUG_INT_STATUS) {
 508                 DRM_DEBUG("CRT event\n");
 509         }
 510
 511         if (stat & SDVOB_HOTPLUG_INT_STATUS) {
 512                 DRM_DEBUG("sDVOB event\n");
 513         }
 514
 515         if (stat & SDVOC_HOTPLUG_INT_STATUS) {
 516                 DRM_DEBUG("sDVOC event\n");
 517         }
 518         queue_work(dev_priv->wq, &hotplug);
 519
 520         return 0;
 521 }
 522
 523 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 524 {
 525         struct drm_device *dev = (struct drm_device *) arg;
 526         struct drm_i915_master_private *master_priv;
 527         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 528         u32 iir;
 529         u32 pipea_stats = 0, pipeb_stats = 0, tvdac;
 530         int hotplug = 0;
 531         int vblank = 0;
 532
 533         if (dev->pdev->msi_enabled)
 534                 I915_WRITE(IMR, ~0);
 535         iir = I915_READ(IIR);
 536 #if 0
 537         DRM_DEBUG("flag=%08x\n", iir);
 538 #endif
 539         atomic_inc(&dev_priv->irq_received);
 540         if (iir == 0) {
 541                 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
 542                            iir,
 543                            I915_READ(IMR),
 544                            I915_READ(IER),
 545                            I915_READ(PIPEASTAT),
 546                            I915_READ(PIPEBSTAT));
 547                 if (dev->pdev->msi_enabled) {
 548                         I915_WRITE(IMR,
 549                                    dev_priv->irq_mask_reg);
 550                         (void) I915_READ(IMR);
 551                 }
 552                 return IRQ_NONE;
 553         }
 554
 555         /*
 556          * Clear the PIPE(A|B)STAT regs before the IIR otherwise
 557          * we may get extra interrupts.
 558          */
 559         if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 560                 pipea_stats = I915_READ(PIPEASTAT);
 561                 I915_WRITE(PIPEASTAT, pipea_stats);
 562         }
 563
 564         if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 565                 pipeb_stats = I915_READ(PIPEBSTAT);
 566                 I915_WRITE(PIPEBSTAT, pipeb_stats);
 567         }
 568
 569         I915_WRITE(IIR, iir);
 570         if (dev->pdev->msi_enabled)
 571                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
 572         (void) I915_READ(IIR); /* Flush posted writes */
 573
 574         /* This is a global event, and not a pipe A event */
 575         if (pipea_stats & PIPE_HOTPLUG_INTERRUPT_STATUS)
 576                 hotplug = 1;
 577
 578         if (pipea_stats & PIPE_HOTPLUG_TV_INTERRUPT_STATUS) {
 579                 hotplug = 1;
 580                 /* Toggle hotplug detection to clear hotplug status */
 581                 tvdac = I915_READ(TV_DAC);
 582                 I915_WRITE(TV_DAC, tvdac & ~TVDAC_STATE_CHG_EN);
 583                 I915_WRITE(TV_DAC, tvdac | TVDAC_STATE_CHG_EN);
 584         }
 585
 586         if (dev->primary->master) {
 587                 master_priv = dev->primary->master->driver_priv;
 588                 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 589         }
 590
 591         if (iir & I915_USER_INTERRUPT) {
 592                 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 593                 DRM_WAKEUP(&dev_priv->irq_queue);
 594 #ifdef I915_HAVE_FENCE
 595                 i915_fence_handler(dev);
 596 #endif
 597         }
 598
 599         if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 600                            PIPE_VBLANK_INTERRUPT_STATUS)) {
 601                 vblank++;
 602                 drm_handle_vblank(dev, i915_get_plane(dev, 0));
 603         }
 604
 605         if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
 606                            PIPE_VBLANK_INTERRUPT_STATUS)) {
 607                 vblank++;
 608                 drm_handle_vblank(dev, i915_get_plane(dev, 1));
 609         }
 610
 611         if (vblank) {
 612                 if (dev_priv->swaps_pending > 0)
 613                         drm_locked_tasklet(dev, i915_vblank_tasklet);
 614         }
 615
 616         if ((iir & I915_DISPLAY_PORT_INTERRUPT) || hotplug) {
 617                 u32 temp2 = 0;
 618
 619                 DRM_INFO("Hotplug event received\n");
 620
 621                 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev)) {
 622                         if (pipea_stats & PIPE_HOTPLUG_INTERRUPT_STATUS)
 623                                 temp2 |= SDVOB_HOTPLUG_INT_STATUS |
 624                                         SDVOC_HOTPLUG_INT_STATUS;
 625                         if (pipea_stats & PIPE_HOTPLUG_TV_INTERRUPT_STATUS)
 626                                 temp2 |= TV_HOTPLUG_INT_STATUS;
 627                 } else {
 628                         temp2 = I915_READ(PORT_HOTPLUG_STAT);
 629
 630                         I915_WRITE(PORT_HOTPLUG_STAT, temp2);
 631                 }
 632                 i915_run_hotplug_tasklet(dev, temp2);
 633         }
 634
 635         return IRQ_HANDLED;
 636 }
 637
 638 int i915_emit_irq(struct drm_device *dev)
 639 {
 640         struct drm_i915_private *dev_priv = dev->dev_private;
 641         RING_LOCALS;
 642
 643         i915_kernel_lost_context(dev);
 644
 645         DRM_DEBUG("\n");
 646
 647         i915_emit_breadcrumb(dev);
 648
 649         BEGIN_LP_RING(2);
 650         OUT_RING(0);
 651         OUT_RING(MI_USER_INTERRUPT);
 652         ADVANCE_LP_RING();
 653
 654         return dev_priv->counter;
 655 }
 656
 657 void i915_user_irq_on(struct drm_device *dev)
 658 {
 659         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 660
 661         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 662         if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 663                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 664         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 665 }
 666
 667 void i915_user_irq_off(struct drm_device *dev)
 668 {
 669         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 670
 671         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 672         BUG_ON(dev_priv->irq_enabled && dev_priv->user_irq_refcount <= 0);
 673         if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 674                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 675         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 676 }
 677
 678
 679 int i915_wait_irq(struct drm_device * dev, int irq_nr)
 680 {
 681         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 682         struct drm_i915_master_private *master_priv;
 683         int ret = 0;
 684
 685         if (!dev_priv) {
 686                 DRM_ERROR("called with no initialization\n");
 687                 return -EINVAL;
 688         }
 689
 690         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 691                   READ_BREADCRUMB(dev_priv));
 692
 693         master_priv = dev->primary->master->driver_priv;
 694
 695         if (!master_priv) {
 696                 DRM_ERROR("no master priv?\n");
 697                 return -EINVAL;
 698         }
 699
 700         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 701                 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 702                 return 0;
 703         }
 704
 705         i915_user_irq_on(dev);
 706         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 707                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 708         i915_user_irq_off(dev);
 709
 710         if (ret == -EBUSY) {
 711                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 712                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 713         }
 714
 715         if (READ_BREADCRUMB(dev_priv) >= irq_nr)
 716                 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 717
 718         return ret;
 719 }
 720
 721 /* Needs the lock as it touches the ring.
 722  */
 723 int i915_irq_emit(struct drm_device *dev, void *data,
 724                          struct drm_file *file_priv)
 725 {
 726         struct drm_i915_private *dev_priv = dev->dev_private;
 727         struct drm_i915_irq_emit *emit = data;
 728         int result;
 729
 730         LOCK_TEST_WITH_RETURN(dev, file_priv);
 731
 732         if (!dev_priv) {
 733                 DRM_ERROR("called with no initialization\n");
 734                 return -EINVAL;
 735         }
 736
 737         result = i915_emit_irq(dev);
 738
 739         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 740                 DRM_ERROR("copy_to_user\n");
 741                 return -EFAULT;
 742         }
 743
 744         return 0;
 745 }
 746
 747 /* Doesn't need the hardware lock.
 748  */
 749 int i915_irq_wait(struct drm_device *dev, void *data,
 750                   struct drm_file *file_priv)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         struct drm_i915_irq_wait *irqwait = data;
 754
 755         if (!dev_priv) {
 756                 DRM_ERROR("called with no initialization\n");
 757                 return -EINVAL;
 758         }
 759
 760         return i915_wait_irq(dev, irqwait->irq_seq);
 761 }
 762
 763 int i915_enable_vblank(struct drm_device *dev, int plane)
 764 {
 765         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 766         int pipe = i915_get_pipe(dev, plane);
 767         u32     pipestat_reg = 0;
 768         u32     mask_reg = 0;
 769         u32     pipestat;
 770
 771         switch (pipe) {
 772         case 0:
 773                 pipestat_reg = PIPEASTAT;
 774                 mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 775                 break;
 776         case 1:
 777                 pipestat_reg = PIPEBSTAT;
 778                 mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 779                 break;
 780         default:
 781                 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
 782                           pipe);
 783                 break;
 784         }
 785
 786         if (pipestat_reg)
 787         {
 788                 pipestat = I915_READ (pipestat_reg);
 789                 /*
 790                  * Older chips didn't have the start vblank interrupt,
 791                  * but
 792                  */
 793                 if (IS_I965G (dev))
 794                         pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
 795                 else
 796                         pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
 797                 /*
 798                  * Clear any pending status
 799                  */
 800                 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 801                              PIPE_VBLANK_INTERRUPT_STATUS);
 802                 I915_WRITE(pipestat_reg, pipestat);
 803         }
 804
 805         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 806         i915_enable_irq(dev_priv, mask_reg);
 807         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 808
 809         return 0;
 810 }
 811
 812 void i915_disable_vblank(struct drm_device *dev, int plane)
 813 {
 814         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 815         int pipe = i915_get_pipe(dev, plane);
 816         u32     pipestat_reg = 0;
 817         u32     mask_reg = 0;
 818         u32     pipestat;
 819
 820         switch (pipe) {
 821         case 0:
 822                 pipestat_reg = PIPEASTAT;
 823                 mask_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 824                 break;
 825         case 1:
 826                 pipestat_reg = PIPEBSTAT;
 827                 mask_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
 828                 break;
 829         default:
 830                 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
 831                           pipe);
 832                 break;
 833         }
 834
 835         DRM_SPINLOCK(&dev_priv->user_irq_lock);
 836         i915_disable_irq(dev_priv, mask_reg);
 837         DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
 838
 839         if (pipestat_reg) {
 840                 pipestat = I915_READ (pipestat_reg);
 841                 pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
 842                               PIPE_VBLANK_INTERRUPT_ENABLE);
 843                 /*
 844                  * Clear any pending status
 845                  */
 846                 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
 847                              PIPE_VBLANK_INTERRUPT_STATUS);
 848                 I915_WRITE(pipestat_reg, pipestat);
 849                 (void) I915_READ(pipestat_reg);
 850         }
 851 }
 852
 853 void i915_enable_interrupt (struct drm_device *dev)
 854 {
 855         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
 856         struct drm_connector *o;
 857
 858         dev_priv->irq_mask_reg &= ~0;
 859
 860         if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
 861                 if (dev->mode_config.num_connector)
 862                         dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT;
 863         } else {
 864                 if (dev->mode_config.num_connector)
 865                         dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
 866
 867                 /* Enable global interrupts for hotplug - not a pipeA event */
 868                 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) |
 869                            PIPE_HOTPLUG_INTERRUPT_ENABLE |
 870                            PIPE_HOTPLUG_TV_INTERRUPT_ENABLE |
 871                            PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
 872                            PIPE_HOTPLUG_INTERRUPT_STATUS);
 873         }
 874
 875         if (!(dev_priv->irq_mask_reg & I915_DISPLAY_PORT_INTERRUPT) ||
 876             !(dev_priv->irq_mask_reg & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) {
 877                 u32 temp = 0;
 878
 879                 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
 880                         temp = I915_READ(PORT_HOTPLUG_EN);
 881
 882                         /* Activate the CRT */
 883                         temp |= CRT_HOTPLUG_INT_EN;
 884                 }
 885
 886                 if (IS_I9XX(dev)) {
 887                         /* SDVOB */
 888                         o = intel_sdvo_find(dev, 1);
 889                         if (o && intel_sdvo_supports_hotplug(o)) {
 890                                 intel_sdvo_set_hotplug(o, 1);
 891                                 temp |= SDVOB_HOTPLUG_INT_EN;
 892                         }
 893
 894                         /* SDVOC */
 895                         o = intel_sdvo_find(dev, 0);
 896                         if (o && intel_sdvo_supports_hotplug(o)) {
 897                                 intel_sdvo_set_hotplug(o, 1);
 898                                 temp |= SDVOC_HOTPLUG_INT_EN;
 899                         }
 900
 901                         I915_WRITE(SDVOB, I915_READ(SDVOB) | SDVO_INTERRUPT_ENABLE);
 902                         I915_WRITE(SDVOC, I915_READ(SDVOC) | SDVO_INTERRUPT_ENABLE);
 903
 904                         /* TV */
 905                         I915_WRITE(TV_DAC, I915_READ(TV_DAC) | TVDAC_STATE_CHG_EN);
 906                 } else {
 907                         /* DVO ???? */
 908                 }
 909
 910                 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
 911                         I915_WRITE(PORT_HOTPLUG_EN, temp);
 912
 913                         DRM_DEBUG("HEN %08x\n",I915_READ(PORT_HOTPLUG_EN));
 914                         DRM_DEBUG("HST %08x\n",I915_READ(PORT_HOTPLUG_STAT));
 915
 916                         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
 917                 }
 918         }
 919
 920         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 921         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 922         (void) I915_READ (IER);
 923         dev_priv->irq_enabled = 1;
 924 }
 925
 926 /* Set the vblank monitor pipe
 927  */
 928 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 929                          struct drm_file *file_priv)
 930 {
 931         struct drm_i915_private *dev_priv = dev->dev_private;
 932         struct drm_i915_vblank_pipe *pipe = data;
 933
 934         if (!dev_priv) {
 935                 DRM_ERROR("called with no initialization\n");
 936                 return -EINVAL;
 937         }
 938
 939         if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
 940                 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
 941                 return -EINVAL;
 942         }
 943
 944         dev_priv->vblank_pipe = pipe->pipe;
 945
 946         return 0;
 947 }
 948
 949 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 950                          struct drm_file *file_priv)
 951 {
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953         struct drm_i915_vblank_pipe *pipe = data;
 954         u32 flag = 0;
 955
 956         if (!dev_priv) {
 957                 DRM_ERROR("called with no initialization\n");
 958                 return -EINVAL;
 959         }
 960
 961         if (dev_priv->irq_enabled)
 962             flag = ~dev_priv->irq_mask_reg;
 963
 964         pipe->pipe = 0;
 965         if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
 966                 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
 967         if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
 968                 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
 969
 970         return 0;
 971 }
 972
 973 /**
 974  * Schedule buffer swap at given vertical blank.
 975  */
 976 int i915_vblank_swap(struct drm_device *dev, void *data,
 977                      struct drm_file *file_priv)
 978 {
 979         struct drm_i915_private *dev_priv = dev->dev_private;
 980         struct drm_i915_master_private *master_priv;
 981         struct drm_i915_vblank_swap *swap = data;
 982         struct drm_i915_vbl_swap *vbl_swap;
 983         unsigned int pipe, seqtype, curseq, plane;
 984         unsigned long irqflags;
 985         struct list_head *list;
 986         int ret;
 987
 988         if (!dev_priv) {
 989                 DRM_ERROR("%s called with no initialization\n", __func__);
 990                 return -EINVAL;
 991         }
 992
 993         if (!dev->primary->master)
 994                 return -EINVAL;
 995
 996         master_priv = dev->primary->master->driver_priv;
 997
 998         if (master_priv->sarea_priv->rotation) {
 999                 DRM_DEBUG("Rotation not supported\n");
1000                 return -EINVAL;
1001         }
1002
1003         if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
1004                              _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
1005                              _DRM_VBLANK_FLIP)) {
1006                 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
1007                 return -EINVAL;
1008         }
1009
1010         plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
1011         pipe = i915_get_pipe(dev, plane);
1012
1013         seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
1014
1015         if (!(dev_priv->vblank_pipe & (1 << pipe))) {
1016                 DRM_ERROR("Invalid pipe %d\n", pipe);
1017                 return -EINVAL;
1018         }
1019
1020         DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
1021
1022         /* It makes no sense to schedule a swap for a drawable that doesn't have
1023          * valid information at this point. E.g. this could mean that the X
1024          * server is too old to push drawable information to the DRM, in which
1025          * case all such swaps would become ineffective.
1026          */
1027         if (!drm_get_drawable_info(dev, swap->drawable)) {
1028                 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1029                 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
1030                 return -EINVAL;
1031         }
1032
1033         DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1034
1035         drm_update_vblank_count(dev, pipe);
1036         curseq = drm_vblank_count(dev, pipe);
1037
1038         if (seqtype == _DRM_VBLANK_RELATIVE)
1039                 swap->sequence += curseq;
1040
1041         if ((curseq - swap->sequence) <= (1<<23)) {
1042                 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
1043                         swap->sequence = curseq + 1;
1044                 } else {
1045                         DRM_DEBUG("Missed target sequence\n");
1046                         return -EINVAL;
1047                 }
1048         }
1049
1050         if (swap->seqtype & _DRM_VBLANK_FLIP) {
1051                 swap->sequence--;
1052
1053                 if ((curseq - swap->sequence) <= (1<<23)) {
1054                         struct drm_drawable_info *drw;
1055
1056                         LOCK_TEST_WITH_RETURN(dev, file_priv);
1057
1058                         DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
1059
1060                         drw = drm_get_drawable_info(dev, swap->drawable);
1061
1062                         if (!drw) {
1063                                 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
1064                                     irqflags);
1065                                 DRM_DEBUG("Invalid drawable ID %d\n",
1066                                           swap->drawable);
1067                                 return -EINVAL;
1068                         }
1069
1070                         i915_dispatch_vsync_flip(dev, drw, plane);
1071
1072                         DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1073
1074                         return 0;
1075                 }
1076         }
1077
1078         DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
1079
1080         list_for_each(list, &dev_priv->vbl_swaps.head) {
1081                 vbl_swap = list_entry(list, struct drm_i915_vbl_swap, head);
1082
1083                 if (vbl_swap->drw_id == swap->drawable &&
1084                     vbl_swap->plane == plane &&
1085                     vbl_swap->sequence == swap->sequence) {
1086                         vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
1087                         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1088                         DRM_DEBUG("Already scheduled\n");
1089                         return 0;
1090                 }
1091         }
1092
1093         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1094
1095         if (dev_priv->swaps_pending >= 100) {
1096                 DRM_DEBUG("Too many swaps queued\n");
1097                 return -EBUSY;
1098         }
1099
1100         vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
1101
1102         if (!vbl_swap) {
1103                 DRM_ERROR("Failed to allocate memory to queue swap\n");
1104                 return -ENOMEM;
1105         }
1106
1107         DRM_DEBUG("\n");
1108
1109         ret = drm_vblank_get(dev, pipe);
1110         if (ret) {
1111                 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
1112                 return ret;
1113         }
1114
1115         vbl_swap->drw_id = swap->drawable;
1116         vbl_swap->plane = plane;
1117         vbl_swap->sequence = swap->sequence;
1118         vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
1119         vbl_swap->minor = file_priv->minor;
1120
1121         if (vbl_swap->flip)
1122                 swap->sequence++;
1123
1124         DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
1125
1126         list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
1127         dev_priv->swaps_pending++;
1128
1129         DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1130
1131         return 0;
1132 }
1133
1134 /* drm_dma.h hooks
1135 */
1136 void i915_driver_irq_preinstall(struct drm_device * dev)
1137 {
1138         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1139         u32 tmp;
1140
1141         tmp = I915_READ(PIPEASTAT);
1142         I915_WRITE(PIPEASTAT, tmp);
1143         tmp = I915_READ(PIPEBSTAT);
1144         I915_WRITE(PIPEBSTAT, tmp);
1145
1146         atomic_set(&dev_priv->irq_received, 0);
1147         I915_WRITE(HWSTAM, 0xffff);
1148         I915_WRITE(IER, 0x0);
1149         I915_WRITE(IMR, 0xffffffff);
1150         I915_WRITE(IIR, 0xffffffff);
1151         (void) I915_READ(IIR);
1152 }
1153
1154 int i915_driver_irq_postinstall(struct drm_device * dev)
1155 {
1156         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1157         int ret, num_pipes = 2;
1158
1159         DRM_SPININIT(&dev_priv->swaps_lock, "swap");
1160         INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
1161         dev_priv->swaps_pending = 0;
1162
1163         DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
1164         dev_priv->user_irq_refcount = 0;
1165         dev_priv->irq_mask_reg = ~0;
1166
1167         ret = drm_vblank_init(dev, num_pipes);
1168         if (ret)
1169                 return ret;
1170
1171         ret = drm_hotplug_init(dev);
1172         if (ret)
1173                 return ret;
1174
1175         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1176
1177         i915_enable_interrupt(dev);
1178         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1179
1180         /*
1181          * Initialize the hardware status page IRQ location.
1182          */
1183
1184         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1185         return 0;
1186 }
1187
1188 void i915_driver_irq_uninstall(struct drm_device * dev)
1189 {
1190         struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1191         u32 temp;
1192
1193         if (!dev_priv)
1194                 return;
1195
1196         dev_priv->irq_enabled = 1;
1197
1198         temp = I915_READ(PIPEASTAT);
1199         I915_WRITE(PIPEASTAT, temp);
1200         temp = I915_READ(PIPEBSTAT);
1201         I915_WRITE(PIPEBSTAT, temp);
1202         if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
1203                 I915_WRITE(HWSTAM, 0xffffffff);
1204                 I915_WRITE(IMR, 0xffffffff);
1205                 I915_WRITE(IER, 0x0);
1206
1207                 temp = I915_READ(IIR);
1208                 I915_WRITE(IIR, temp);
1209         } else {
1210                 I915_WRITE16(HWSTAM, 0xffff);
1211                 I915_WRITE16(IMR, 0xffff);
1212                 I915_WRITE16(IER, 0x0);
1213
1214                 temp = I915_READ16(IIR);
1215                 I915_WRITE16(IIR, temp);
1216         }
1217 }