1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include "intel_drv.h"
34 #include "drm_crtc_helper.h"
36 #define MAX_NOPID ((u32)~0)
39 * i915_get_pipe - return the the pipe associated with a given plane
41 * @plane: plane to look for
43 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
44 * rather than a pipe number, since they may not always be equal. This routine
45 * maps the given @plane back to a pipe number.
48 i915_get_pipe(struct drm_device *dev, int plane)
50 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
53 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
55 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
59 * i915_get_plane - return the the plane associated with a given pipe
61 * @pipe: pipe to look for
63 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
64 * rather than a plane number, since they may not always be equal. This routine
65 * maps the given @pipe back to a plane number.
68 i915_get_plane(struct drm_device *dev, int pipe)
70 if (i915_get_pipe(dev, 0) == pipe)
76 * i915_pipe_enabled - check if a pipe is enabled
78 * @pipe: pipe to check
80 * Reading certain registers when the pipe is disabled can hang the chip.
81 * Use this routine to make sure the PLL is running and the pipe is active
82 * before reading such registers if unsure.
85 i915_pipe_enabled(struct drm_device *dev, int pipe)
87 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
88 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
90 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
97 * Emit a synchronous flip.
99 * This function must be called with the drawable spinlock held.
102 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
105 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
106 struct drm_i915_sarea *sarea_priv = master_priv->sarea_priv;
108 int pf_planes = 1 << plane;
110 DRM_SPINLOCK_ASSERT(&dev->drw_lock);
112 /* If the window is visible on the other plane, we have to flip on that
116 x1 = sarea_priv->planeA_x;
117 y1 = sarea_priv->planeA_y;
118 x2 = x1 + sarea_priv->planeA_w;
119 y2 = y1 + sarea_priv->planeA_h;
121 x1 = sarea_priv->planeB_x;
122 y1 = sarea_priv->planeB_y;
123 x2 = x1 + sarea_priv->planeB_w;
124 y2 = y1 + sarea_priv->planeB_h;
127 if (x2 > 0 && y2 > 0) {
128 int i, num_rects = drw->num_rects;
129 struct drm_clip_rect *rect = drw->rects;
131 for (i = 0; i < num_rects; i++)
132 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
133 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
140 i915_dispatch_flip(dev, pf_planes, 1);
144 * Emit blits for scheduled buffer swaps.
146 * This function will be called with the HW lock held.
148 static void i915_vblank_tasklet(struct drm_device *dev)
150 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
151 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
152 struct list_head *list, *tmp, hits, *hit;
153 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
155 struct drm_drawable_info *drw;
156 struct drm_i915_sarea *sarea_priv = master_priv->sarea_priv;
157 u32 cpp = dev_priv->cpp, offsets[3];
158 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
159 XY_SRC_COPY_BLT_WRITE_ALPHA |
160 XY_SRC_COPY_BLT_WRITE_RGB)
161 : XY_SRC_COPY_BLT_CMD;
162 u32 src_pitch = sarea_priv->pitch * cpp;
163 u32 dst_pitch = sarea_priv->pitch * cpp;
164 /* COPY rop (0xcc), map cpp to magic color depth constants */
165 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
168 if (sarea_priv->front_tiled) {
169 cmd |= XY_SRC_COPY_BLT_DST_TILED;
172 if (sarea_priv->back_tiled) {
173 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
177 counter[0] = drm_vblank_count(dev, 0);
178 counter[1] = drm_vblank_count(dev, 1);
182 INIT_LIST_HEAD(&hits);
186 /* No irqsave/restore necessary. This tasklet may be run in an
187 * interrupt context or normal context, but we don't have to worry
188 * about getting interrupted by something acquiring the lock, because
189 * we are the interrupt context thing that acquires the lock.
191 DRM_SPINLOCK(&dev_priv->swaps_lock);
193 /* Find buffer swaps scheduled for this vertical blank */
194 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
195 struct drm_i915_vbl_swap *vbl_swap =
196 list_entry(list, struct drm_i915_vbl_swap, head);
197 int pipe = i915_get_pipe(dev, vbl_swap->plane);
199 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
202 master_priv = vbl_swap->minor->master->driver_priv;
203 sarea_priv = master_priv->sarea_priv;
206 dev_priv->swaps_pending--;
207 drm_vblank_put(dev, pipe);
209 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
210 DRM_SPINLOCK(&dev->drw_lock);
212 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
215 DRM_SPINUNLOCK(&dev->drw_lock);
216 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
217 DRM_SPINLOCK(&dev_priv->swaps_lock);
221 list_for_each(hit, &hits) {
222 struct drm_i915_vbl_swap *swap_cmp =
223 list_entry(hit, struct drm_i915_vbl_swap, head);
224 struct drm_drawable_info *drw_cmp =
225 drm_get_drawable_info(dev, swap_cmp->drw_id);
228 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
229 list_add_tail(list, hit);
234 DRM_SPINUNLOCK(&dev->drw_lock);
236 /* List of hits was empty, or we reached the end of it */
238 list_add_tail(list, hits.prev);
242 DRM_SPINLOCK(&dev_priv->swaps_lock);
245 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
251 i915_kernel_lost_context(dev);
253 upper[0] = upper[1] = 0;
254 slice[0] = max(sarea_priv->planeA_h / nhits, 1);
255 slice[1] = max(sarea_priv->planeB_h / nhits, 1);
256 lower[0] = sarea_priv->planeA_y + slice[0];
257 lower[1] = sarea_priv->planeB_y + slice[0];
259 offsets[0] = sarea_priv->front_offset;
260 offsets[1] = sarea_priv->back_offset;
261 offsets[2] = sarea_priv->third_offset;
262 num_pages = sarea_priv->third_handle ? 3 : 2;
264 DRM_SPINLOCK(&dev->drw_lock);
266 /* Emit blits for buffer swaps, partitioning both outputs into as many
267 * slices as there are buffer swaps scheduled in order to avoid tearing
268 * (based on the assumption that a single buffer swap would always
269 * complete before scanout starts).
271 for (i = 0; i++ < nhits;
272 upper[0] = lower[0], lower[0] += slice[0],
273 upper[1] = lower[1], lower[1] += slice[1]) {
274 int init_drawrect = 1;
277 lower[0] = lower[1] = sarea_priv->height;
279 list_for_each(hit, &hits) {
280 struct drm_i915_vbl_swap *swap_hit =
281 list_entry(hit, struct drm_i915_vbl_swap, head);
282 struct drm_clip_rect *rect;
283 int num_rects, plane, front, back;
284 unsigned short top, bottom;
286 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
291 plane = swap_hit->plane;
293 if (swap_hit->flip) {
294 i915_dispatch_vsync_flip(dev, drw, plane);
299 int width = sarea_priv->width;
300 int height = sarea_priv->height;
304 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
306 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
313 OUT_RING(GFX_OP_DRAWRECT_INFO);
316 OUT_RING(((width - 1) & 0xffff) | ((height - 1) << 16));
323 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
330 bottom = lower[plane];
332 front = (master_priv->sarea_priv->pf_current_page >>
334 back = (front + 1) % num_pages;
336 for (num_rects = drw->num_rects; num_rects--; rect++) {
337 int y1 = max(rect->y1, top);
338 int y2 = min(rect->y2, bottom);
346 OUT_RING(ropcpp | dst_pitch);
347 OUT_RING((y1 << 16) | rect->x1);
348 OUT_RING((y2 << 16) | rect->x2);
349 OUT_RING(offsets[front]);
350 OUT_RING((y1 << 16) | rect->x1);
352 OUT_RING(offsets[back]);
359 DRM_SPINUNLOCK(&dev->drw_lock);
361 list_for_each_safe(hit, tmp, &hits) {
362 struct drm_i915_vbl_swap *swap_hit =
363 list_entry(hit, struct drm_i915_vbl_swap, head);
367 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
371 static int i915_in_vblank(struct drm_device *dev, int pipe)
373 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
374 unsigned long pipedsl, vblank, vtotal;
375 unsigned long vbl_start, vbl_end, cur_line;
377 pipedsl = pipe ? PIPEBDSL : PIPEADSL;
378 vblank = pipe ? VBLANK_B : VBLANK_A;
379 vtotal = pipe ? VTOTAL_B : VTOTAL_A;
381 vbl_start = I915_READ(vblank) & VBLANK_START_MASK;
382 vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;
384 cur_line = I915_READ(pipedsl);
386 if (cur_line >= vbl_start)
392 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
394 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
395 unsigned long high_frame;
396 unsigned long low_frame;
397 u32 high1, high2, low, count;
400 pipe = i915_get_pipe(dev, plane);
401 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
402 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
404 if (!i915_pipe_enabled(dev, pipe)) {
405 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
410 * High & low register fields aren't synchronized, so make sure
411 * we get a low value that's stable across two reads of the high
415 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
416 PIPE_FRAME_HIGH_SHIFT);
417 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
418 PIPE_FRAME_LOW_SHIFT);
419 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
420 PIPE_FRAME_HIGH_SHIFT);
421 } while (high1 != high2);
423 count = (high1 << 8) | low;
426 * If we're in the middle of the vblank period, the
427 * above regs won't have been updated yet, so return
428 * an incremented count to stay accurate
431 if (i915_in_vblank(dev, pipe))
434 /* count may be reset by other driver(e.g. 2D driver),
435 we have no way to know if it is wrapped or resetted
436 when count is zero. do a rough guess.
438 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
439 dev->last_vblank[pipe] = 0;
444 static struct drm_device *hotplug_dev;
447 * This code is called in a more safe envirmoent to handle the hotplugs.
448 * Add code here for hotplug love to userspace.
450 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
451 static void i915_hotplug_work_func(void *work)
453 static void i915_hotplug_work_func(struct work_struct *work)
456 struct drm_device *dev = hotplug_dev;
458 drm_helper_hotplug_stage_two(dev);
459 drm_handle_hotplug(dev);
462 static int i915_run_hotplug_tasklet(struct drm_device *dev, uint32_t stat)
464 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
465 static DECLARE_WORK(hotplug, i915_hotplug_work_func, NULL);
467 static DECLARE_WORK(hotplug, i915_hotplug_work_func);
469 struct drm_i915_private *dev_priv = dev->dev_private;
473 if (stat & TV_HOTPLUG_INT_STATUS) {
474 DRM_DEBUG("TV event\n");
477 if (stat & CRT_HOTPLUG_INT_STATUS) {
478 DRM_DEBUG("CRT event\n");
481 if (stat & SDVOB_HOTPLUG_INT_STATUS) {
482 DRM_DEBUG("sDVOB event\n");
485 if (stat & SDVOC_HOTPLUG_INT_STATUS) {
486 DRM_DEBUG("sDVOC event\n");
489 queue_work(dev_priv->wq, &hotplug);
494 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
496 struct drm_device *dev = (struct drm_device *) arg;
497 struct drm_i915_master_private *master_priv;
498 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
500 u32 pipea_stats = 0, pipeb_stats, tvdac;
504 /* On i8xx/i915 hw the IIR and IER are 16bit on i9xx its 32bit */
505 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
506 iir = I915_READ(IIR);
508 iir = I915_READ16(IIR);
510 iir &= (dev_priv->irq_enable_reg | I915_USER_INTERRUPT);
513 DRM_DEBUG("flag=%08x\n", iir);
517 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
521 I915_READ(PIPEASTAT),
522 I915_READ(PIPEBSTAT));
528 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
529 * we may get extra interrupts.
531 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
532 pipea_stats = I915_READ(PIPEASTAT);
533 if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
534 PIPE_VBLANK_INTERRUPT_STATUS))
537 drm_handle_vblank(dev, i915_get_plane(dev, 0));
540 /* This is a global event, and not a pipe A event */
541 if (pipea_stats & PIPE_HOTPLUG_INTERRUPT_STATUS)
544 if (pipea_stats & PIPE_HOTPLUG_TV_INTERRUPT_STATUS) {
546 /* Toggle hotplug detection to clear hotplug status */
547 tvdac = I915_READ(TV_DAC);
548 I915_WRITE(TV_DAC, tvdac & ~TVDAC_STATE_CHG_EN);
549 I915_WRITE(TV_DAC, tvdac | TVDAC_STATE_CHG_EN);
552 I915_WRITE(PIPEASTAT, pipea_stats);
555 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
556 pipeb_stats = I915_READ(PIPEBSTAT);
557 if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
558 PIPE_VBLANK_INTERRUPT_STATUS))
561 drm_handle_vblank(dev, i915_get_plane(dev, 1));
563 I915_WRITE(PIPEBSTAT, pipeb_stats);
566 /* Clear the generated interrupt */
567 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
568 I915_WRITE(IIR, iir);
569 (void) I915_READ(IIR);
571 I915_WRITE16(IIR, iir);
572 (void) I915_READ16(IIR);
575 if (dev->primary->master) {
576 master_priv = dev->primary->master->driver_priv;
577 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
580 if (iir & I915_USER_INTERRUPT) {
581 DRM_WAKEUP(&dev_priv->irq_queue);
582 #ifdef I915_HAVE_FENCE
583 i915_fence_handler(dev);
588 if (dev_priv->swaps_pending > 0)
589 drm_locked_tasklet(dev, i915_vblank_tasklet);
592 if ((iir & I915_DISPLAY_PORT_INTERRUPT) || hotplug) {
595 DRM_INFO("Hotplug event received\n");
597 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev)) {
598 if (pipea_stats & PIPE_HOTPLUG_INTERRUPT_STATUS)
599 temp2 |= SDVOB_HOTPLUG_INT_STATUS |
600 SDVOC_HOTPLUG_INT_STATUS;
601 if (pipea_stats & PIPE_HOTPLUG_TV_INTERRUPT_STATUS)
602 temp2 |= TV_HOTPLUG_INT_STATUS;
604 temp2 = I915_READ(PORT_HOTPLUG_STAT);
606 I915_WRITE(PORT_HOTPLUG_STAT, temp2);
608 i915_run_hotplug_tasklet(dev, temp2);
614 int i915_emit_irq(struct drm_device *dev)
616 struct drm_i915_private *dev_priv = dev->dev_private;
619 i915_kernel_lost_context(dev);
623 i915_emit_breadcrumb(dev);
627 OUT_RING(MI_USER_INTERRUPT);
630 return dev_priv->counter;
633 void i915_user_irq_on(struct drm_device *dev)
635 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
637 DRM_SPINLOCK(&dev_priv->user_irq_lock);
638 if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
639 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
640 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
641 I915_WRITE(IER, dev_priv->irq_enable_reg);
643 I915_WRITE16(IER, dev_priv->irq_enable_reg);
645 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
649 void i915_user_irq_off(struct drm_device *dev)
651 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
653 DRM_SPINLOCK(&dev_priv->user_irq_lock);
654 if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
655 // dev_priv->irq_enable_reg &= ~I915_USER_INTERRUPT;
656 // if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
657 // I915_WRITE(IER, dev_priv->irq_enable_reg);
659 // I915_WRITE16(IER, dev_priv->irq_enable_reg);
661 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
665 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
667 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
668 struct drm_i915_master_private *master_priv;
671 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
672 READ_BREADCRUMB(dev_priv));
674 if (READ_BREADCRUMB(dev_priv) >= irq_nr)
677 i915_user_irq_on(dev);
678 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
679 READ_BREADCRUMB(dev_priv) >= irq_nr);
680 i915_user_irq_off(dev);
683 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
684 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
687 if (dev->primary->master) {
688 master_priv = dev->primary->master->driver_priv;
689 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
695 /* Needs the lock as it touches the ring.
697 int i915_irq_emit(struct drm_device *dev, void *data,
698 struct drm_file *file_priv)
700 struct drm_i915_private *dev_priv = dev->dev_private;
701 struct drm_i915_irq_emit *emit = data;
704 LOCK_TEST_WITH_RETURN(dev, file_priv);
707 DRM_ERROR("called with no initialization\n");
711 result = i915_emit_irq(dev);
713 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
714 DRM_ERROR("copy_to_user\n");
721 /* Doesn't need the hardware lock.
723 int i915_irq_wait(struct drm_device *dev, void *data,
724 struct drm_file *file_priv)
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 struct drm_i915_irq_wait *irqwait = data;
730 DRM_ERROR("called with no initialization\n");
734 return i915_wait_irq(dev, irqwait->irq_seq);
737 int i915_enable_vblank(struct drm_device *dev, int plane)
739 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
740 int pipe = i915_get_pipe(dev, plane);
741 u32 pipestat_reg = 0;
746 pipestat_reg = PIPEASTAT;
747 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
750 pipestat_reg = PIPEBSTAT;
751 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
754 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
761 pipestat = I915_READ (pipestat_reg);
763 * Older chips didn't have the start vblank interrupt,
767 pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
769 pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
771 * Clear any pending status
773 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
774 PIPE_VBLANK_INTERRUPT_STATUS);
775 I915_WRITE(pipestat_reg, pipestat);
778 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
779 I915_WRITE(IER, dev_priv->irq_enable_reg);
781 I915_WRITE16(IER, dev_priv->irq_enable_reg);
787 void i915_disable_vblank(struct drm_device *dev, int plane)
789 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
790 int pipe = i915_get_pipe(dev, plane);
791 u32 pipestat_reg = 0;
796 pipestat_reg = PIPEASTAT;
797 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
800 pipestat_reg = PIPEBSTAT;
801 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
804 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
809 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
810 I915_WRITE(IER, dev_priv->irq_enable_reg);
812 I915_WRITE16(IER, dev_priv->irq_enable_reg);
816 pipestat = I915_READ (pipestat_reg);
817 pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
818 PIPE_VBLANK_INTERRUPT_ENABLE);
820 * Clear any pending status
822 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
823 PIPE_VBLANK_INTERRUPT_STATUS);
824 I915_WRITE(pipestat_reg, pipestat);
828 void i915_enable_interrupt (struct drm_device *dev)
830 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
831 struct drm_connector *o;
833 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
835 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
836 if (dev->mode_config.num_connector)
837 dev_priv->irq_enable_reg |= I915_DISPLAY_PORT_INTERRUPT;
839 if (dev->mode_config.num_connector)
840 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
842 /* Enable global interrupts for hotplug - not a pipeA event */
843 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) |
844 PIPE_HOTPLUG_INTERRUPT_ENABLE |
845 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE |
846 PIPE_HOTPLUG_TV_INTERRUPT_STATUS |
847 PIPE_HOTPLUG_INTERRUPT_STATUS);
850 if (dev_priv->irq_enable_reg & (I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) {
853 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
854 temp = I915_READ(PORT_HOTPLUG_EN);
856 /* Activate the CRT */
857 temp |= CRT_HOTPLUG_INT_EN;
862 o = intel_sdvo_find(dev, 1);
863 if (o && intel_sdvo_supports_hotplug(o)) {
864 intel_sdvo_set_hotplug(o, 1);
865 temp |= SDVOB_HOTPLUG_INT_EN;
869 o = intel_sdvo_find(dev, 0);
870 if (o && intel_sdvo_supports_hotplug(o)) {
871 intel_sdvo_set_hotplug(o, 1);
872 temp |= SDVOC_HOTPLUG_INT_EN;
875 I915_WRITE(SDVOB, I915_READ(SDVOB) | SDVO_INTERRUPT_ENABLE);
876 I915_WRITE(SDVOC, I915_READ(SDVOC) | SDVO_INTERRUPT_ENABLE);
879 I915_WRITE(TV_DAC, I915_READ(TV_DAC) | TVDAC_STATE_CHG_EN);
884 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
885 I915_WRITE(PORT_HOTPLUG_EN, temp);
887 DRM_DEBUG("HEN %08x\n",I915_READ(PORT_HOTPLUG_EN));
888 DRM_DEBUG("HST %08x\n",I915_READ(PORT_HOTPLUG_STAT));
890 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
894 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
895 I915_WRITE(IER, dev_priv->irq_enable_reg);
897 I915_WRITE16(IER, dev_priv->irq_enable_reg);
899 dev_priv->irq_enabled = 1;
902 /* Set the vblank monitor pipe
904 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
905 struct drm_file *file_priv)
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 struct drm_i915_vblank_pipe *pipe = data;
911 DRM_ERROR("called with no initialization\n");
915 if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
916 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
920 dev_priv->vblank_pipe = pipe->pipe;
925 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
926 struct drm_file *file_priv)
928 struct drm_i915_private *dev_priv = dev->dev_private;
929 struct drm_i915_vblank_pipe *pipe = data;
933 DRM_ERROR("called with no initialization\n");
937 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
938 flag = I915_READ(IER);
940 flag = I915_READ16(IER);
943 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
944 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
945 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
946 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
952 * Schedule buffer swap at given vertical blank.
954 int i915_vblank_swap(struct drm_device *dev, void *data,
955 struct drm_file *file_priv)
957 struct drm_i915_private *dev_priv = dev->dev_private;
958 struct drm_i915_master_private *master_priv;
959 struct drm_i915_vblank_swap *swap = data;
960 struct drm_i915_vbl_swap *vbl_swap;
961 unsigned int pipe, seqtype, curseq, plane;
962 unsigned long irqflags;
963 struct list_head *list;
967 DRM_ERROR("%s called with no initialization\n", __func__);
971 if (!dev->primary->master)
974 master_priv = dev->primary->master->driver_priv;
976 if (master_priv->sarea_priv->rotation) {
977 DRM_DEBUG("Rotation not supported\n");
981 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
982 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
984 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
988 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
989 pipe = i915_get_pipe(dev, plane);
991 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
993 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
994 DRM_ERROR("Invalid pipe %d\n", pipe);
998 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
1000 /* It makes no sense to schedule a swap for a drawable that doesn't have
1001 * valid information at this point. E.g. this could mean that the X
1002 * server is too old to push drawable information to the DRM, in which
1003 * case all such swaps would become ineffective.
1005 if (!drm_get_drawable_info(dev, swap->drawable)) {
1006 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1007 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
1011 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1013 drm_update_vblank_count(dev, pipe);
1014 curseq = drm_vblank_count(dev, pipe);
1016 if (seqtype == _DRM_VBLANK_RELATIVE)
1017 swap->sequence += curseq;
1019 if ((curseq - swap->sequence) <= (1<<23)) {
1020 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
1021 swap->sequence = curseq + 1;
1023 DRM_DEBUG("Missed target sequence\n");
1028 if (swap->seqtype & _DRM_VBLANK_FLIP) {
1031 if ((curseq - swap->sequence) <= (1<<23)) {
1032 struct drm_drawable_info *drw;
1034 LOCK_TEST_WITH_RETURN(dev, file_priv);
1036 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
1038 drw = drm_get_drawable_info(dev, swap->drawable);
1041 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
1043 DRM_DEBUG("Invalid drawable ID %d\n",
1048 i915_dispatch_vsync_flip(dev, drw, plane);
1050 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1056 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
1058 list_for_each(list, &dev_priv->vbl_swaps.head) {
1059 vbl_swap = list_entry(list, struct drm_i915_vbl_swap, head);
1061 if (vbl_swap->drw_id == swap->drawable &&
1062 vbl_swap->plane == plane &&
1063 vbl_swap->sequence == swap->sequence) {
1064 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
1065 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1066 DRM_DEBUG("Already scheduled\n");
1071 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1073 if (dev_priv->swaps_pending >= 100) {
1074 DRM_DEBUG("Too many swaps queued\n");
1078 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
1081 DRM_ERROR("Failed to allocate memory to queue swap\n");
1087 ret = drm_vblank_get(dev, pipe);
1089 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
1093 vbl_swap->drw_id = swap->drawable;
1094 vbl_swap->plane = plane;
1095 vbl_swap->sequence = swap->sequence;
1096 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
1097 vbl_swap->minor = file_priv->minor;
1102 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
1104 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
1105 dev_priv->swaps_pending++;
1107 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1114 void i915_driver_irq_preinstall(struct drm_device * dev)
1116 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1119 tmp = I915_READ(PIPEASTAT);
1120 I915_WRITE(PIPEASTAT, tmp);
1121 tmp = I915_READ(PIPEBSTAT);
1122 I915_WRITE(PIPEBSTAT, tmp);
1125 I915_WRITE16(HWSTAM, 0xeffe);
1126 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
1127 I915_WRITE(IMR, 0x0);
1128 I915_WRITE(IER, 0x0);
1129 tmp = I915_READ(IIR);
1130 I915_WRITE(IIR, tmp);
1132 I915_WRITE16(IMR, 0x0);
1133 I915_WRITE16(IER, 0x0);
1134 tmp = I915_READ16(IIR);
1135 I915_WRITE16(IIR, tmp);
1140 int i915_driver_irq_postinstall(struct drm_device * dev)
1142 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1143 int ret, num_pipes = 2;
1145 DRM_SPININIT(&dev_priv->swaps_lock, "swap");
1146 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
1147 dev_priv->swaps_pending = 0;
1149 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
1150 dev_priv->user_irq_refcount = 0;
1151 dev_priv->irq_enable_reg = 0;
1153 ret = drm_vblank_init(dev, num_pipes);
1157 ret = drm_hotplug_init(dev);
1161 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1163 i915_enable_interrupt(dev);
1164 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1167 * Initialize the hardware status page IRQ location.
1170 I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1174 void i915_driver_irq_uninstall(struct drm_device * dev)
1176 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1182 dev_priv->irq_enabled = 0;
1184 temp = I915_READ(PIPEASTAT);
1185 I915_WRITE(PIPEASTAT, temp);
1186 temp = I915_READ(PIPEBSTAT);
1187 I915_WRITE(PIPEBSTAT, temp);
1188 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
1189 I915_WRITE(HWSTAM, 0xffffffff);
1190 I915_WRITE(IMR, 0xffffffff);
1191 I915_WRITE(IER, 0x0);
1193 temp = I915_READ(IIR);
1194 I915_WRITE(IIR, temp);
1196 I915_WRITE16(HWSTAM, 0xffff);
1197 I915_WRITE16(IMR, 0xffff);
1198 I915_WRITE16(IER, 0x0);
1200 temp = I915_READ16(IIR);
1201 I915_WRITE16(IIR, temp);