1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include "intel_drv.h"
35 #define MAX_NOPID ((u32)~0)
38 * i915_get_pipe - return the the pipe associated with a given plane
40 * @plane: plane to look for
42 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
43 * rather than a pipe number, since they may not always be equal. This routine
44 * maps the given @plane back to a pipe number.
47 i915_get_pipe(struct drm_device *dev, int plane)
49 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
52 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
54 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
58 * i915_get_plane - return the the plane associated with a given pipe
60 * @pipe: pipe to look for
62 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
63 * rather than a plane number, since they may not always be equal. This routine
64 * maps the given @pipe back to a plane number.
67 i915_get_plane(struct drm_device *dev, int pipe)
69 if (i915_get_pipe(dev, 0) == pipe)
75 * i915_pipe_enabled - check if a pipe is enabled
77 * @pipe: pipe to check
79 * Reading certain registers when the pipe is disabled can hang the chip.
80 * Use this routine to make sure the PLL is running and the pipe is active
81 * before reading such registers if unsure.
84 i915_pipe_enabled(struct drm_device *dev, int pipe)
86 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
87 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
89 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
96 * Emit a synchronous flip.
98 * This function must be called with the drawable spinlock held.
101 i915_dispatch_vsync_flip(struct drm_device *dev, struct drm_drawable_info *drw,
104 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
105 struct drm_i915_sarea *sarea_priv = master_priv->sarea_priv;
107 int pf_planes = 1 << plane;
109 DRM_SPINLOCK_ASSERT(&dev->drw_lock);
111 /* If the window is visible on the other plane, we have to flip on that
115 x1 = sarea_priv->planeA_x;
116 y1 = sarea_priv->planeA_y;
117 x2 = x1 + sarea_priv->planeA_w;
118 y2 = y1 + sarea_priv->planeA_h;
120 x1 = sarea_priv->planeB_x;
121 y1 = sarea_priv->planeB_y;
122 x2 = x1 + sarea_priv->planeB_w;
123 y2 = y1 + sarea_priv->planeB_h;
126 if (x2 > 0 && y2 > 0) {
127 int i, num_rects = drw->num_rects;
128 struct drm_clip_rect *rect = drw->rects;
130 for (i = 0; i < num_rects; i++)
131 if (!(rect[i].x1 >= x2 || rect[i].y1 >= y2 ||
132 rect[i].x2 <= x1 || rect[i].y2 <= y1)) {
139 i915_dispatch_flip(dev, pf_planes, 1);
143 * Emit blits for scheduled buffer swaps.
145 * This function will be called with the HW lock held.
147 static void i915_vblank_tasklet(struct drm_device *dev)
149 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
150 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
151 struct list_head *list, *tmp, hits, *hit;
152 int nhits, nrects, slice[2], upper[2], lower[2], i, num_pages;
154 struct drm_drawable_info *drw;
155 struct drm_i915_sarea *sarea_priv = master_priv->sarea_priv;
156 u32 cpp = dev_priv->cpp, offsets[3];
157 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
158 XY_SRC_COPY_BLT_WRITE_ALPHA |
159 XY_SRC_COPY_BLT_WRITE_RGB)
160 : XY_SRC_COPY_BLT_CMD;
161 u32 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
162 (cpp << 23) | (1 << 24);
165 counter[0] = drm_vblank_count(dev, 0);
166 counter[1] = drm_vblank_count(dev, 1);
170 INIT_LIST_HEAD(&hits);
174 /* No irqsave/restore necessary. This tasklet may be run in an
175 * interrupt context or normal context, but we don't have to worry
176 * about getting interrupted by something acquiring the lock, because
177 * we are the interrupt context thing that acquires the lock.
179 DRM_SPINLOCK(&dev_priv->swaps_lock);
181 /* Find buffer swaps scheduled for this vertical blank */
182 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
183 struct drm_i915_vbl_swap *vbl_swap =
184 list_entry(list, struct drm_i915_vbl_swap, head);
185 int pipe = i915_get_pipe(dev, vbl_swap->plane);
187 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
190 master_priv = vbl_swap->minor->master->driver_priv;
191 sarea_priv = master_priv->sarea_priv;
193 pitchropcpp = (sarea_priv->pitch * cpp) | (0xcc << 16) |
194 (cpp << 23) | (1 << 24);
197 dev_priv->swaps_pending--;
198 drm_vblank_put(dev, pipe);
200 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
201 DRM_SPINLOCK(&dev->drw_lock);
203 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
206 DRM_SPINUNLOCK(&dev->drw_lock);
207 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
208 DRM_SPINLOCK(&dev_priv->swaps_lock);
212 list_for_each(hit, &hits) {
213 struct drm_i915_vbl_swap *swap_cmp =
214 list_entry(hit, struct drm_i915_vbl_swap, head);
215 struct drm_drawable_info *drw_cmp =
216 drm_get_drawable_info(dev, swap_cmp->drw_id);
219 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
220 list_add_tail(list, hit);
225 DRM_SPINUNLOCK(&dev->drw_lock);
227 /* List of hits was empty, or we reached the end of it */
229 list_add_tail(list, hits.prev);
233 DRM_SPINLOCK(&dev_priv->swaps_lock);
236 DRM_SPINUNLOCK(&dev_priv->swaps_lock);
242 i915_kernel_lost_context(dev);
244 upper[0] = upper[1] = 0;
245 slice[0] = max(sarea_priv->planeA_h / nhits, 1);
246 slice[1] = max(sarea_priv->planeB_h / nhits, 1);
247 lower[0] = sarea_priv->planeA_y + slice[0];
248 lower[1] = sarea_priv->planeB_y + slice[0];
250 offsets[0] = sarea_priv->front_offset;
251 offsets[1] = sarea_priv->back_offset;
252 offsets[2] = sarea_priv->third_offset;
253 num_pages = sarea_priv->third_handle ? 3 : 2;
255 DRM_SPINLOCK(&dev->drw_lock);
257 /* Emit blits for buffer swaps, partitioning both outputs into as many
258 * slices as there are buffer swaps scheduled in order to avoid tearing
259 * (based on the assumption that a single buffer swap would always
260 * complete before scanout starts).
262 for (i = 0; i++ < nhits;
263 upper[0] = lower[0], lower[0] += slice[0],
264 upper[1] = lower[1], lower[1] += slice[1]) {
265 int init_drawrect = 1;
268 lower[0] = lower[1] = sarea_priv->height;
270 list_for_each(hit, &hits) {
271 struct drm_i915_vbl_swap *swap_hit =
272 list_entry(hit, struct drm_i915_vbl_swap, head);
273 struct drm_clip_rect *rect;
274 int num_rects, plane, front, back;
275 unsigned short top, bottom;
277 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
282 plane = swap_hit->plane;
284 if (swap_hit->flip) {
285 i915_dispatch_vsync_flip(dev, drw, plane);
292 OUT_RING(GFX_OP_DRAWRECT_INFO);
295 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
296 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
301 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
308 bottom = lower[plane];
310 front = (master_priv->sarea_priv->pf_current_page >>
312 back = (front + 1) % num_pages;
314 for (num_rects = drw->num_rects; num_rects--; rect++) {
315 int y1 = max(rect->y1, top);
316 int y2 = min(rect->y2, bottom);
324 OUT_RING(pitchropcpp);
325 OUT_RING((y1 << 16) | rect->x1);
326 OUT_RING((y2 << 16) | rect->x2);
327 OUT_RING(offsets[front]);
328 OUT_RING((y1 << 16) | rect->x1);
329 OUT_RING(pitchropcpp & 0xffff);
330 OUT_RING(offsets[back]);
337 DRM_SPINUNLOCK(&dev->drw_lock);
339 list_for_each_safe(hit, tmp, &hits) {
340 struct drm_i915_vbl_swap *swap_hit =
341 list_entry(hit, struct drm_i915_vbl_swap, head);
345 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
349 static int i915_in_vblank(struct drm_device *dev, int pipe)
351 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
352 unsigned long pipedsl, vblank, vtotal;
353 unsigned long vbl_start, vbl_end, cur_line;
355 pipedsl = pipe ? PIPEBDSL : PIPEADSL;
356 vblank = pipe ? VBLANK_B : VBLANK_A;
357 vtotal = pipe ? VTOTAL_B : VTOTAL_A;
359 vbl_start = I915_READ(vblank) & VBLANK_START_MASK;
360 vbl_end = (I915_READ(vblank) >> VBLANK_END_SHIFT) & VBLANK_END_MASK;
362 cur_line = I915_READ(pipedsl);
364 if (cur_line >= vbl_start)
370 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
372 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
373 unsigned long high_frame;
374 unsigned long low_frame;
375 u32 high1, high2, low, count;
378 pipe = i915_get_pipe(dev, plane);
379 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
380 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
382 if (!i915_pipe_enabled(dev, pipe)) {
383 printk(KERN_ERR "trying to get vblank count for disabled "
389 * High & low register fields aren't synchronized, so make sure
390 * we get a low value that's stable across two reads of the high
394 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
395 PIPE_FRAME_HIGH_SHIFT);
396 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
397 PIPE_FRAME_LOW_SHIFT);
398 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
399 PIPE_FRAME_HIGH_SHIFT);
400 } while (high1 != high2);
402 count = (high1 << 8) | low;
405 * If we're in the middle of the vblank period, the
406 * above regs won't have been updated yet, so return
407 * an incremented count to stay accurate
410 if (i915_in_vblank(dev, pipe))
413 /* count may be reset by other driver(e.g. 2D driver),
414 we have no way to know if it is wrapped or resetted
415 when count is zero. do a rough guess.
417 if (count == 0 && dev->last_vblank[pipe] < dev->max_vblank_count/2)
418 dev->last_vblank[pipe] = 0;
423 #define HOTPLUG_CMD_CRT 1
424 #define HOTPLUG_CMD_CRT_DIS 2
425 #define HOTPLUG_CMD_SDVOB 4
426 #define HOTPLUG_CMD_SDVOC 8
427 #define HOTPLUG_CMD_TV 16
429 static struct drm_device *hotplug_dev;
430 static int hotplug_cmd = 0;
431 static spinlock_t hotplug_lock = SPIN_LOCK_UNLOCKED;
433 static void i915_hotplug_tv(struct drm_device *dev)
435 struct drm_output *output;
436 struct intel_output *iout;
437 enum drm_output_status status;
439 mutex_lock(&dev->mode_config.mutex);
441 /* find the crt output */
442 list_for_each_entry(output, &dev->mode_config.output_list, head) {
443 iout = output->driver_private;
444 if (iout->type == INTEL_OUTPUT_TVOUT)
453 /* may need to I915_WRITE(TVDAC, 1<<31) to ack the interrupt */
454 status = output->funcs->detect(output);
455 drm_hotplug_stage_two(dev, output,
456 status == output_status_connected ? 1 : 0);
459 mutex_unlock(&dev->mode_config.mutex);
462 static void i915_hotplug_crt(struct drm_device *dev, bool isconnected)
464 struct drm_output *output;
465 struct intel_output *iout;
467 mutex_lock(&dev->mode_config.mutex);
469 /* find the crt output */
470 list_for_each_entry(output, &dev->mode_config.output_list, head) {
471 iout = output->driver_private;
472 if (iout->type == INTEL_OUTPUT_ANALOG)
481 drm_hotplug_stage_two(dev, output, isconnected);
484 mutex_unlock(&dev->mode_config.mutex);
487 static void i915_hotplug_sdvo(struct drm_device *dev, int sdvoB)
489 struct drm_output *output = 0;
490 enum drm_output_status status;
492 mutex_lock(&dev->mode_config.mutex);
494 output = intel_sdvo_find(dev, sdvoB);
499 status = output->funcs->detect(output);
501 if (status != output_status_connected)
502 drm_hotplug_stage_two(dev, output, false);
504 drm_hotplug_stage_two(dev, output, true);
506 intel_sdvo_set_hotplug(output, 1);
509 mutex_unlock(&dev->mode_config.mutex);
512 * This code is called in a more safe envirmoent to handle the hotplugs.
513 * Add code here for hotplug love to userspace.
515 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
516 static void i915_hotplug_work_func(void *work)
518 static void i915_hotplug_work_func(struct work_struct *work)
521 struct drm_device *dev = hotplug_dev;
528 spin_lock(&hotplug_lock);
529 tv = hotplug_cmd & HOTPLUG_CMD_TV;
530 crt = hotplug_cmd & HOTPLUG_CMD_CRT;
531 crtDis = hotplug_cmd & HOTPLUG_CMD_CRT_DIS;
532 sdvoB = hotplug_cmd & HOTPLUG_CMD_SDVOB;
533 sdvoC = hotplug_cmd & HOTPLUG_CMD_SDVOC;
535 spin_unlock(&hotplug_lock);
538 i915_hotplug_tv(dev);
540 i915_hotplug_crt(dev, true);
542 i915_hotplug_crt(dev, false);
545 i915_hotplug_sdvo(dev, 1);
548 i915_hotplug_sdvo(dev, 0);
550 drm_handle_hotplug(dev);
553 static int i915_run_hotplug_tasklet(struct drm_device *dev, uint32_t stat)
555 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
556 static DECLARE_WORK(hotplug, i915_hotplug_work_func, NULL);
558 static DECLARE_WORK(hotplug, i915_hotplug_work_func);
560 struct drm_i915_private *dev_priv = dev->dev_private;
564 if (stat & TV_HOTPLUG_INT_STATUS) {
565 DRM_DEBUG("TV event\n");
567 spin_lock(&hotplug_lock);
568 hotplug_cmd |= HOTPLUG_CMD_TV;
569 spin_unlock(&hotplug_lock);
572 if (stat & CRT_HOTPLUG_INT_STATUS) {
573 DRM_DEBUG("CRT event\n");
575 if (stat & CRT_HOTPLUG_MONITOR_MASK) {
576 spin_lock(&hotplug_lock);
577 hotplug_cmd |= HOTPLUG_CMD_CRT;
578 spin_unlock(&hotplug_lock);
580 spin_lock(&hotplug_lock);
581 hotplug_cmd |= HOTPLUG_CMD_CRT_DIS;
582 spin_unlock(&hotplug_lock);
586 if (stat & SDVOB_HOTPLUG_INT_STATUS) {
587 DRM_DEBUG("sDVOB event\n");
589 spin_lock(&hotplug_lock);
590 hotplug_cmd |= HOTPLUG_CMD_SDVOB;
591 spin_unlock(&hotplug_lock);
594 if (stat & SDVOC_HOTPLUG_INT_STATUS) {
595 DRM_DEBUG("sDVOC event\n");
597 spin_lock(&hotplug_lock);
598 hotplug_cmd |= HOTPLUG_CMD_SDVOC;
599 spin_unlock(&hotplug_lock);
602 queue_work(dev_priv->wq, &hotplug);
607 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
609 struct drm_device *dev = (struct drm_device *) arg;
610 struct drm_i915_master_private *master_priv;
611 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
613 u32 pipea_stats, pipeb_stats;
617 /* On i8xx/i915 hw the IIR and IER are 16bit on i9xx its 32bit */
618 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
619 iir = I915_READ(I915REG_INT_IDENTITY_R);
621 iir = I915_READ16(I915REG_INT_IDENTITY_R);
623 iir &= (dev_priv->irq_enable_reg | I915_USER_INTERRUPT);
626 DRM_DEBUG("flag=%08x\n", iir);
630 DRM_DEBUG ("iir 0x%08x im 0x%08x ie 0x%08x pipea 0x%08x pipeb 0x%08x\n",
632 I915_READ(I915REG_INT_MASK_R),
633 I915_READ(I915REG_INT_ENABLE_R),
634 I915_READ(I915REG_PIPEASTAT),
635 I915_READ(I915REG_PIPEBSTAT));
641 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
642 * we may get extra interrupts.
644 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
645 pipea_stats = I915_READ(I915REG_PIPEASTAT);
646 if (pipea_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
647 I915_VBLANK_INTERRUPT_STATUS))
650 drm_handle_vblank(dev, i915_get_plane(dev, 0));
653 /* This is a global event, and not a pipe A event */
654 if ((pipea_stats & I915_HOTPLUG_INTERRUPT_STATUS) ||
655 (pipea_stats & I915_HOTPLUG_TV_INTERRUPT_STATUS))
658 I915_WRITE(I915REG_PIPEASTAT, pipea_stats);
661 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
662 pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
663 if (pipeb_stats & (I915_START_VBLANK_INTERRUPT_STATUS|
664 I915_VBLANK_INTERRUPT_STATUS))
667 drm_handle_vblank(dev, i915_get_plane(dev, 1));
669 I915_WRITE(I915REG_PIPEBSTAT, pipeb_stats);
672 /* Clear the generated interrupt */
673 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
674 I915_WRITE(I915REG_INT_IDENTITY_R, iir);
675 (void) I915_READ(I915REG_INT_IDENTITY_R);
677 I915_WRITE16(I915REG_INT_IDENTITY_R, iir);
678 (void) I915_READ16(I915REG_INT_IDENTITY_R);
681 if (dev->primary->master) {
682 master_priv = dev->primary->master->driver_priv;
683 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
686 if (iir & I915_USER_INTERRUPT) {
687 DRM_WAKEUP(&dev_priv->irq_queue);
688 #ifdef I915_HAVE_FENCE
689 i915_fence_handler(dev);
694 if (dev_priv->swaps_pending > 0)
695 drm_locked_tasklet(dev, i915_vblank_tasklet);
698 if ((iir & I915_DISPLAY_PORT_INTERRUPT) || hotplug) {
701 DRM_INFO("Hotplug event received\n");
703 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev)) {
704 if (pipea_stats & I915_HOTPLUG_INTERRUPT_STATUS)
705 temp2 |= SDVOB_HOTPLUG_INT_STATUS |
706 SDVOC_HOTPLUG_INT_STATUS;
707 if (pipea_stats & I915_HOTPLUG_TV_INTERRUPT_STATUS)
708 temp2 |= TV_HOTPLUG_INT_STATUS;
710 temp2 = I915_READ(PORT_HOTPLUG_STAT);
712 I915_WRITE(PORT_HOTPLUG_STAT, temp2);
714 i915_run_hotplug_tasklet(dev, temp2);
720 int i915_emit_irq(struct drm_device *dev)
722 struct drm_i915_private *dev_priv = dev->dev_private;
725 i915_kernel_lost_context(dev);
729 i915_emit_breadcrumb(dev);
733 OUT_RING(GFX_OP_USER_INTERRUPT);
736 return dev_priv->counter;
739 void i915_user_irq_on(struct drm_device *dev)
741 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
743 DRM_SPINLOCK(&dev_priv->user_irq_lock);
744 if (dev_priv->irq_enabled && (++dev_priv->user_irq_refcount == 1)){
745 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
746 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
747 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
749 I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
751 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
755 void i915_user_irq_off(struct drm_device *dev)
757 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
759 DRM_SPINLOCK(&dev_priv->user_irq_lock);
760 if (dev_priv->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
761 // dev_priv->irq_enable_reg &= ~I915_USER_INTERRUPT;
762 // if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
763 // I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
765 // I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
767 DRM_SPINUNLOCK(&dev_priv->user_irq_lock);
771 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
773 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
774 struct drm_i915_master_private *master_priv;
777 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
778 READ_BREADCRUMB(dev_priv));
780 if (READ_BREADCRUMB(dev_priv) >= irq_nr)
783 i915_user_irq_on(dev);
784 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
785 READ_BREADCRUMB(dev_priv) >= irq_nr);
786 i915_user_irq_off(dev);
789 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
790 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
793 if (dev->primary->master) {
794 master_priv = dev->primary->master->driver_priv;
795 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
801 /* Needs the lock as it touches the ring.
803 int i915_irq_emit(struct drm_device *dev, void *data,
804 struct drm_file *file_priv)
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 struct drm_i915_irq_emit *emit = data;
810 LOCK_TEST_WITH_RETURN(dev, file_priv);
813 DRM_ERROR("called with no initialization\n");
817 result = i915_emit_irq(dev);
819 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
820 DRM_ERROR("copy_to_user\n");
827 /* Doesn't need the hardware lock.
829 int i915_irq_wait(struct drm_device *dev, void *data,
830 struct drm_file *file_priv)
832 struct drm_i915_private *dev_priv = dev->dev_private;
833 struct drm_i915_irq_wait *irqwait = data;
836 DRM_ERROR("called with no initialization\n");
840 return i915_wait_irq(dev, irqwait->irq_seq);
843 int i915_enable_vblank(struct drm_device *dev, int plane)
845 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
846 int pipe = i915_get_pipe(dev, plane);
847 u32 pipestat_reg = 0;
852 pipestat_reg = I915REG_PIPEASTAT;
853 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
856 pipestat_reg = I915REG_PIPEBSTAT;
857 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
860 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
867 pipestat = I915_READ (pipestat_reg);
869 * Older chips didn't have the start vblank interrupt,
873 pipestat |= I915_START_VBLANK_INTERRUPT_ENABLE;
875 pipestat |= I915_VBLANK_INTERRUPT_ENABLE;
877 * Clear any pending status
879 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
880 I915_VBLANK_INTERRUPT_STATUS);
881 I915_WRITE(pipestat_reg, pipestat);
884 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
885 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
887 I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
893 void i915_disable_vblank(struct drm_device *dev, int plane)
895 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
896 int pipe = i915_get_pipe(dev, plane);
897 u32 pipestat_reg = 0;
902 pipestat_reg = I915REG_PIPEASTAT;
903 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
906 pipestat_reg = I915REG_PIPEBSTAT;
907 dev_priv->irq_enable_reg &= ~I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
910 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
915 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
916 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
918 I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
922 pipestat = I915_READ (pipestat_reg);
923 pipestat &= ~(I915_START_VBLANK_INTERRUPT_ENABLE |
924 I915_VBLANK_INTERRUPT_ENABLE);
926 * Clear any pending status
928 pipestat |= (I915_START_VBLANK_INTERRUPT_STATUS |
929 I915_VBLANK_INTERRUPT_STATUS);
930 I915_WRITE(pipestat_reg, pipestat);
934 void i915_enable_interrupt (struct drm_device *dev)
936 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
937 struct drm_output *o;
939 dev_priv->irq_enable_reg |= I915_USER_INTERRUPT;
941 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
942 if (dev->mode_config.num_output)
943 dev_priv->irq_enable_reg |= I915_DISPLAY_PORT_INTERRUPT;
945 if (dev->mode_config.num_output)
946 dev_priv->irq_enable_reg |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
948 /* Enable global interrupts for hotplug - not a pipeA event */
949 I915_WRITE(I915REG_PIPEASTAT, I915_READ(I915REG_PIPEASTAT) |
950 I915_HOTPLUG_INTERRUPT_ENABLE |
951 I915_HOTPLUG_TV_INTERRUPT_ENABLE |
952 I915_HOTPLUG_TV_CLEAR |
956 if (dev_priv->irq_enable_reg & (I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)) {
959 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
960 temp = I915_READ(PORT_HOTPLUG_EN);
962 /* Activate the CRT */
963 temp |= CRT_HOTPLUG_INT_EN;
968 o = intel_sdvo_find(dev, 1);
969 if (o && intel_sdvo_supports_hotplug(o)) {
970 intel_sdvo_set_hotplug(o, 1);
971 temp |= SDVOB_HOTPLUG_INT_EN;
975 o = intel_sdvo_find(dev, 0);
976 if (o && intel_sdvo_supports_hotplug(o)) {
977 intel_sdvo_set_hotplug(o, 1);
978 temp |= SDVOC_HOTPLUG_INT_EN;
981 I915_WRITE(SDVOB, I915_READ(SDVOB) | SDVO_INTERRUPT_ENABLE);
982 I915_WRITE(SDVOC, I915_READ(SDVOC) | SDVO_INTERRUPT_ENABLE);
987 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
988 I915_WRITE(PORT_HOTPLUG_EN, temp);
990 DRM_DEBUG("HEN %08x\n",I915_READ(PORT_HOTPLUG_EN));
991 DRM_DEBUG("HST %08x\n",I915_READ(PORT_HOTPLUG_STAT));
993 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
997 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
998 I915_WRITE(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
1000 I915_WRITE16(I915REG_INT_ENABLE_R, dev_priv->irq_enable_reg);
1002 dev_priv->irq_enabled = 1;
1005 /* Set the vblank monitor pipe
1007 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1008 struct drm_file *file_priv)
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct drm_i915_vblank_pipe *pipe = data;
1014 DRM_ERROR("called with no initialization\n");
1018 if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
1019 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
1023 dev_priv->vblank_pipe = pipe->pipe;
1028 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1029 struct drm_file *file_priv)
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct drm_i915_vblank_pipe *pipe = data;
1036 DRM_ERROR("called with no initialization\n");
1040 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev))
1041 flag = I915_READ(I915REG_INT_ENABLE_R);
1043 flag = I915_READ16(I915REG_INT_ENABLE_R);
1046 if (flag & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT)
1047 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
1048 if (flag & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
1049 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
1055 * Schedule buffer swap at given vertical blank.
1057 int i915_vblank_swap(struct drm_device *dev, void *data,
1058 struct drm_file *file_priv)
1060 struct drm_i915_private *dev_priv = dev->dev_private;
1061 struct drm_i915_master_private *master_priv;
1062 struct drm_i915_vblank_swap *swap = data;
1063 struct drm_i915_vbl_swap *vbl_swap;
1064 unsigned int pipe, seqtype, curseq, plane;
1065 unsigned long irqflags;
1066 struct list_head *list;
1070 DRM_ERROR("%s called with no initialization\n", __func__);
1074 if (!dev->primary->master)
1077 master_priv = dev->primary->master->driver_priv;
1079 if (master_priv->sarea_priv->rotation) {
1080 DRM_DEBUG("Rotation not supported\n");
1084 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
1085 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS |
1086 _DRM_VBLANK_FLIP)) {
1087 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
1091 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
1092 pipe = i915_get_pipe(dev, plane);
1094 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
1096 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
1097 DRM_ERROR("Invalid pipe %d\n", pipe);
1101 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
1103 /* It makes no sense to schedule a swap for a drawable that doesn't have
1104 * valid information at this point. E.g. this could mean that the X
1105 * server is too old to push drawable information to the DRM, in which
1106 * case all such swaps would become ineffective.
1108 if (!drm_get_drawable_info(dev, swap->drawable)) {
1109 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1110 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
1114 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1116 drm_update_vblank_count(dev, pipe);
1117 curseq = drm_vblank_count(dev, pipe);
1119 if (seqtype == _DRM_VBLANK_RELATIVE)
1120 swap->sequence += curseq;
1122 if ((curseq - swap->sequence) <= (1<<23)) {
1123 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
1124 swap->sequence = curseq + 1;
1126 DRM_DEBUG("Missed target sequence\n");
1131 if (swap->seqtype & _DRM_VBLANK_FLIP) {
1134 if ((curseq - swap->sequence) <= (1<<23)) {
1135 struct drm_drawable_info *drw;
1137 LOCK_TEST_WITH_RETURN(dev, file_priv);
1139 DRM_SPINLOCK_IRQSAVE(&dev->drw_lock, irqflags);
1141 drw = drm_get_drawable_info(dev, swap->drawable);
1144 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock,
1146 DRM_DEBUG("Invalid drawable ID %d\n",
1151 i915_dispatch_vsync_flip(dev, drw, plane);
1153 DRM_SPINUNLOCK_IRQRESTORE(&dev->drw_lock, irqflags);
1159 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
1161 list_for_each(list, &dev_priv->vbl_swaps.head) {
1162 vbl_swap = list_entry(list, struct drm_i915_vbl_swap, head);
1164 if (vbl_swap->drw_id == swap->drawable &&
1165 vbl_swap->plane == plane &&
1166 vbl_swap->sequence == swap->sequence) {
1167 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
1168 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1169 DRM_DEBUG("Already scheduled\n");
1174 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1176 if (dev_priv->swaps_pending >= 100) {
1177 DRM_DEBUG("Too many swaps queued\n");
1181 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
1184 DRM_ERROR("Failed to allocate memory to queue swap\n");
1190 ret = drm_vblank_get(dev, pipe);
1192 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
1196 vbl_swap->drw_id = swap->drawable;
1197 vbl_swap->plane = plane;
1198 vbl_swap->sequence = swap->sequence;
1199 vbl_swap->flip = (swap->seqtype & _DRM_VBLANK_FLIP);
1200 vbl_swap->minor = file_priv->minor;
1205 DRM_SPINLOCK_IRQSAVE(&dev_priv->swaps_lock, irqflags);
1207 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
1208 dev_priv->swaps_pending++;
1210 DRM_SPINUNLOCK_IRQRESTORE(&dev_priv->swaps_lock, irqflags);
1217 void i915_driver_irq_preinstall(struct drm_device * dev)
1219 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1221 I915_WRITE16(I915REG_HWSTAM, 0xeffe);
1222 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
1223 I915_WRITE(I915REG_INT_MASK_R, 0x0);
1224 I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
1226 I915_WRITE16(I915REG_INT_MASK_R, 0x0);
1227 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
1232 int i915_driver_irq_postinstall(struct drm_device * dev)
1234 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1235 int ret, num_pipes = 2;
1237 DRM_SPININIT(&dev_priv->swaps_lock, "swap");
1238 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
1239 dev_priv->swaps_pending = 0;
1241 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
1242 dev_priv->user_irq_refcount = 0;
1243 dev_priv->irq_enable_reg = 0;
1245 ret = drm_vblank_init(dev, num_pipes);
1249 ret = drm_hotplug_init(dev);
1253 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1255 i915_enable_interrupt(dev);
1256 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1259 * Initialize the hardware status page IRQ location.
1262 I915_WRITE(I915REG_INSTPM, (1 << 5) | (1 << 21));
1266 void i915_driver_irq_uninstall(struct drm_device * dev)
1268 struct drm_i915_private *dev_priv = (struct drm_i915_private *) dev->dev_private;
1274 dev_priv->irq_enabled = 0;
1276 temp = I915_READ(I915REG_PIPEASTAT);
1277 I915_WRITE(I915REG_PIPEASTAT, temp);
1278 temp = I915_READ(I915REG_PIPEBSTAT);
1279 I915_WRITE(I915REG_PIPEBSTAT, temp);
1280 if (IS_I9XX(dev) && !IS_I915G(dev) && !IS_I915GM(dev)) {
1281 I915_WRITE(I915REG_HWSTAM, 0xffffffff);
1282 I915_WRITE(I915REG_INT_MASK_R, 0xffffffff);
1283 I915_WRITE(I915REG_INT_ENABLE_R, 0x0);
1285 temp = I915_READ(I915REG_INT_IDENTITY_R);
1286 I915_WRITE(I915REG_INT_IDENTITY_R, temp);
1288 I915_WRITE16(I915REG_HWSTAM, 0xffff);
1289 I915_WRITE16(I915REG_INT_MASK_R, 0xffff);
1290 I915_WRITE16(I915REG_INT_ENABLE_R, 0x0);
1292 temp = I915_READ16(I915REG_INT_IDENTITY_R);
1293 I915_WRITE16(I915REG_INT_IDENTITY_R, temp);