1 /* mach64_dma.c -- DMA support for mach64 (Rage Pro) driver -*- linux-c -*- */
4 * DMA support for mach64 (Rage Pro) driver
6 * \author Gareth Hughes <gareth@valinux.com>
7 * \author Frank C. Earl <fearl@airmail.net>
8 * \author Leif Delgass <ldelgass@retinalburn.net>
9 * \author José Fonseca <j_r_fonseca@yahoo.co.uk>
13 * Copyright 2000 Gareth Hughes
14 * Copyright 2002 Frank C. Earl
15 * Copyright 2002-2003 Leif Delgass
16 * All Rights Reserved.
18 * Permission is hereby granted, free of charge, to any person obtaining a
19 * copy of this software and associated documentation files (the "Software"),
20 * to deal in the Software without restriction, including without limitation
21 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
22 * and/or sell copies of the Software, and to permit persons to whom the
23 * Software is furnished to do so, subject to the following conditions:
25 * The above copyright notice and this permission notice (including the next
26 * paragraph) shall be included in all copies or substantial portions of the
29 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
30 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
31 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
32 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
33 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
34 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
39 #include "mach64_drm.h"
40 #include "mach64_drv.h"
42 /*******************************************************************/
43 /** \name Engine, FIFO control */
47 * Waits for free entries in the FIFO.
49 * \note Most writes to Mach64 registers are automatically routed through
50 * command FIFO which is 16 entry deep. Prior to writing to any draw engine
51 * register one has to ensure that enough FIFO entries are available by calling
52 * this function. Failure to do so may cause the engine to lock.
54 * \param dev_priv pointer to device private data structure.
55 * \param entries number of free entries in the FIFO to wait for.
57 * \returns zero on success, or -EBUSY if the timeout (specificed by
58 * drm_mach64_private::usec_timeout) occurs.
60 int mach64_do_wait_for_fifo(drm_mach64_private_t *dev_priv, int entries)
64 for (i = 0; i < dev_priv->usec_timeout; i++) {
65 slots = (MACH64_READ(MACH64_FIFO_STAT) & MACH64_FIFO_SLOT_MASK);
66 if (slots <= (0x8000 >> entries))
71 DRM_INFO("failed! slots=%d entries=%d\n", slots, entries);
76 * Wait for the draw engine to be idle.
78 int mach64_do_wait_for_idle(drm_mach64_private_t *dev_priv)
82 ret = mach64_do_wait_for_fifo(dev_priv, 16);
86 for (i = 0; i < dev_priv->usec_timeout; i++) {
87 if (!(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE))
92 DRM_INFO("failed! GUI_STAT=0x%08x\n", MACH64_READ(MACH64_GUI_STAT));
93 mach64_dump_ring_info(dev_priv);
98 * Wait for free entries in the ring buffer.
100 * The Mach64 bus master can be configured to act as a virtual FIFO, using a
101 * circular buffer (commonly referred as "ring buffer" in other drivers) with
102 * pointers to engine commands. This allows the CPU to do other things while
103 * the graphics engine is busy, i.e., DMA mode.
105 * This function should be called before writing new entries to the ring
108 * \param dev_priv pointer to device private data structure.
109 * \param n number of free entries in the ring buffer to wait for.
111 * \returns zero on success, or -EBUSY if the timeout (specificed by
112 * drm_mach64_private_t::usec_timeout) occurs.
114 * \sa mach64_dump_ring_info()
116 int mach64_wait_ring(drm_mach64_private_t *dev_priv, int n)
118 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
121 for (i = 0; i < dev_priv->usec_timeout; i++) {
122 mach64_update_ring_snapshot(dev_priv);
123 if (ring->space >= n) {
125 DRM_DEBUG("%d usecs\n", i);
131 /* FIXME: This is being ignored... */
132 DRM_ERROR("failed!\n");
133 mach64_dump_ring_info(dev_priv);
138 * Wait until all DMA requests have been processed...
140 * \sa mach64_wait_ring()
142 static int mach64_ring_idle(drm_mach64_private_t *dev_priv)
144 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
150 while (i < dev_priv->usec_timeout) {
151 mach64_update_ring_snapshot(dev_priv);
152 if (ring->head == ring->tail &&
153 !(MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE)) {
155 DRM_DEBUG("%d usecs\n", i);
158 if (ring->head == head) {
167 DRM_INFO("failed! GUI_STAT=0x%08x\n", MACH64_READ(MACH64_GUI_STAT));
168 mach64_dump_ring_info(dev_priv);
173 * Reset the the ring buffer descriptors.
175 * \sa mach64_do_engine_reset()
177 static void mach64_ring_reset(drm_mach64_private_t *dev_priv)
179 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
181 mach64_do_release_used_buffers(dev_priv);
182 ring->head_addr = ring->start_addr;
183 ring->head = ring->tail = 0;
184 ring->space = ring->size;
186 MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
187 ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
189 dev_priv->ring_running = 0;
193 * Ensure the all the queued commands will be processed.
195 int mach64_do_dma_flush(drm_mach64_private_t *dev_priv)
197 /* FIXME: It's not necessary to wait for idle when flushing
198 * we just need to ensure the ring will be completely processed
199 * in finite time without another ioctl
201 return mach64_ring_idle(dev_priv);
205 * Stop all DMA activity.
207 int mach64_do_dma_idle(drm_mach64_private_t *dev_priv)
211 /* wait for completion */
212 if ((ret = mach64_ring_idle(dev_priv)) < 0) {
213 DRM_ERROR("failed BM_GUI_TABLE=0x%08x tail: %u\n",
214 MACH64_READ(MACH64_BM_GUI_TABLE),
215 dev_priv->ring.tail);
219 mach64_ring_stop(dev_priv);
221 /* clean up after pass */
222 mach64_do_release_used_buffers(dev_priv);
227 * Reset the engine. This will stop the DMA if it is running.
229 int mach64_do_engine_reset(drm_mach64_private_t *dev_priv)
235 /* Kill off any outstanding DMA transfers.
237 tmp = MACH64_READ(MACH64_BUS_CNTL);
238 MACH64_WRITE(MACH64_BUS_CNTL, tmp | MACH64_BUS_MASTER_DIS);
240 /* Reset the GUI engine (high to low transition).
242 tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
243 MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp & ~MACH64_GUI_ENGINE_ENABLE);
244 /* Enable the GUI engine
246 tmp = MACH64_READ(MACH64_GEN_TEST_CNTL);
247 MACH64_WRITE(MACH64_GEN_TEST_CNTL, tmp | MACH64_GUI_ENGINE_ENABLE);
249 /* ensure engine is not locked up by clearing any FIFO or HOST errors
251 tmp = MACH64_READ(MACH64_BUS_CNTL);
252 MACH64_WRITE(MACH64_BUS_CNTL, tmp | 0x00a00000);
254 /* Once GUI engine is restored, disable bus mastering */
255 MACH64_WRITE(MACH64_SRC_CNTL, 0);
257 /* Reset descriptor ring */
258 mach64_ring_reset(dev_priv);
266 /*******************************************************************/
267 /** \name Debugging output */
271 * Dump engine registers values.
273 void mach64_dump_engine_info(drm_mach64_private_t *dev_priv)
276 if (!dev_priv->is_pci) {
277 DRM_INFO(" AGP_BASE = 0x%08x\n",
278 MACH64_READ(MACH64_AGP_BASE));
279 DRM_INFO(" AGP_CNTL = 0x%08x\n",
280 MACH64_READ(MACH64_AGP_CNTL));
282 DRM_INFO(" ALPHA_TST_CNTL = 0x%08x\n",
283 MACH64_READ(MACH64_ALPHA_TST_CNTL));
285 DRM_INFO(" BM_COMMAND = 0x%08x\n",
286 MACH64_READ(MACH64_BM_COMMAND));
287 DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
288 MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
289 DRM_INFO(" BM_GUI_TABLE = 0x%08x\n",
290 MACH64_READ(MACH64_BM_GUI_TABLE));
291 DRM_INFO(" BM_STATUS = 0x%08x\n",
292 MACH64_READ(MACH64_BM_STATUS));
293 DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
294 MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
295 DRM_INFO(" BM_SYSTEM_TABLE = 0x%08x\n",
296 MACH64_READ(MACH64_BM_SYSTEM_TABLE));
297 DRM_INFO(" BUS_CNTL = 0x%08x\n",
298 MACH64_READ(MACH64_BUS_CNTL));
300 /* DRM_INFO( " CLOCK_CNTL = 0x%08x\n", MACH64_READ( MACH64_CLOCK_CNTL ) ); */
301 DRM_INFO(" CLR_CMP_CLR = 0x%08x\n",
302 MACH64_READ(MACH64_CLR_CMP_CLR));
303 DRM_INFO(" CLR_CMP_CNTL = 0x%08x\n",
304 MACH64_READ(MACH64_CLR_CMP_CNTL));
305 /* DRM_INFO( " CLR_CMP_MSK = 0x%08x\n", MACH64_READ( MACH64_CLR_CMP_MSK ) ); */
306 DRM_INFO(" CONFIG_CHIP_ID = 0x%08x\n",
307 MACH64_READ(MACH64_CONFIG_CHIP_ID));
308 DRM_INFO(" CONFIG_CNTL = 0x%08x\n",
309 MACH64_READ(MACH64_CONFIG_CNTL));
310 DRM_INFO(" CONFIG_STAT0 = 0x%08x\n",
311 MACH64_READ(MACH64_CONFIG_STAT0));
312 DRM_INFO(" CONFIG_STAT1 = 0x%08x\n",
313 MACH64_READ(MACH64_CONFIG_STAT1));
314 DRM_INFO(" CONFIG_STAT2 = 0x%08x\n",
315 MACH64_READ(MACH64_CONFIG_STAT2));
316 DRM_INFO(" CRC_SIG = 0x%08x\n", MACH64_READ(MACH64_CRC_SIG));
317 DRM_INFO(" CUSTOM_MACRO_CNTL = 0x%08x\n",
318 MACH64_READ(MACH64_CUSTOM_MACRO_CNTL));
320 /* DRM_INFO( " DAC_CNTL = 0x%08x\n", MACH64_READ( MACH64_DAC_CNTL ) ); */
321 /* DRM_INFO( " DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_DAC_REGS ) ); */
322 DRM_INFO(" DP_BKGD_CLR = 0x%08x\n",
323 MACH64_READ(MACH64_DP_BKGD_CLR));
324 DRM_INFO(" DP_FRGD_CLR = 0x%08x\n",
325 MACH64_READ(MACH64_DP_FRGD_CLR));
326 DRM_INFO(" DP_MIX = 0x%08x\n", MACH64_READ(MACH64_DP_MIX));
327 DRM_INFO(" DP_PIX_WIDTH = 0x%08x\n",
328 MACH64_READ(MACH64_DP_PIX_WIDTH));
329 DRM_INFO(" DP_SRC = 0x%08x\n", MACH64_READ(MACH64_DP_SRC));
330 DRM_INFO(" DP_WRITE_MASK = 0x%08x\n",
331 MACH64_READ(MACH64_DP_WRITE_MASK));
332 DRM_INFO(" DSP_CONFIG = 0x%08x\n",
333 MACH64_READ(MACH64_DSP_CONFIG));
334 DRM_INFO(" DSP_ON_OFF = 0x%08x\n",
335 MACH64_READ(MACH64_DSP_ON_OFF));
336 DRM_INFO(" DST_CNTL = 0x%08x\n",
337 MACH64_READ(MACH64_DST_CNTL));
338 DRM_INFO(" DST_OFF_PITCH = 0x%08x\n",
339 MACH64_READ(MACH64_DST_OFF_PITCH));
341 /* DRM_INFO( " EXT_DAC_REGS = 0x%08x\n", MACH64_READ( MACH64_EXT_DAC_REGS ) ); */
342 DRM_INFO(" EXT_MEM_CNTL = 0x%08x\n",
343 MACH64_READ(MACH64_EXT_MEM_CNTL));
345 DRM_INFO(" FIFO_STAT = 0x%08x\n",
346 MACH64_READ(MACH64_FIFO_STAT));
348 DRM_INFO(" GEN_TEST_CNTL = 0x%08x\n",
349 MACH64_READ(MACH64_GEN_TEST_CNTL));
350 /* DRM_INFO( " GP_IO = 0x%08x\n", MACH64_READ( MACH64_GP_IO ) ); */
351 DRM_INFO(" GUI_CMDFIFO_DATA = 0x%08x\n",
352 MACH64_READ(MACH64_GUI_CMDFIFO_DATA));
353 DRM_INFO(" GUI_CMDFIFO_DEBUG = 0x%08x\n",
354 MACH64_READ(MACH64_GUI_CMDFIFO_DEBUG));
355 DRM_INFO(" GUI_CNTL = 0x%08x\n",
356 MACH64_READ(MACH64_GUI_CNTL));
357 DRM_INFO(" GUI_STAT = 0x%08x\n",
358 MACH64_READ(MACH64_GUI_STAT));
359 DRM_INFO(" GUI_TRAJ_CNTL = 0x%08x\n",
360 MACH64_READ(MACH64_GUI_TRAJ_CNTL));
362 DRM_INFO(" HOST_CNTL = 0x%08x\n",
363 MACH64_READ(MACH64_HOST_CNTL));
364 DRM_INFO(" HW_DEBUG = 0x%08x\n",
365 MACH64_READ(MACH64_HW_DEBUG));
367 DRM_INFO(" MEM_ADDR_CONFIG = 0x%08x\n",
368 MACH64_READ(MACH64_MEM_ADDR_CONFIG));
369 DRM_INFO(" MEM_BUF_CNTL = 0x%08x\n",
370 MACH64_READ(MACH64_MEM_BUF_CNTL));
372 DRM_INFO(" PAT_REG0 = 0x%08x\n",
373 MACH64_READ(MACH64_PAT_REG0));
374 DRM_INFO(" PAT_REG1 = 0x%08x\n",
375 MACH64_READ(MACH64_PAT_REG1));
377 DRM_INFO(" SC_LEFT = 0x%08x\n", MACH64_READ(MACH64_SC_LEFT));
378 DRM_INFO(" SC_RIGHT = 0x%08x\n",
379 MACH64_READ(MACH64_SC_RIGHT));
380 DRM_INFO(" SC_TOP = 0x%08x\n", MACH64_READ(MACH64_SC_TOP));
381 DRM_INFO(" SC_BOTTOM = 0x%08x\n",
382 MACH64_READ(MACH64_SC_BOTTOM));
384 DRM_INFO(" SCALE_3D_CNTL = 0x%08x\n",
385 MACH64_READ(MACH64_SCALE_3D_CNTL));
386 DRM_INFO(" SCRATCH_REG0 = 0x%08x\n",
387 MACH64_READ(MACH64_SCRATCH_REG0));
388 DRM_INFO(" SCRATCH_REG1 = 0x%08x\n",
389 MACH64_READ(MACH64_SCRATCH_REG1));
390 DRM_INFO(" SETUP_CNTL = 0x%08x\n",
391 MACH64_READ(MACH64_SETUP_CNTL));
392 DRM_INFO(" SRC_CNTL = 0x%08x\n",
393 MACH64_READ(MACH64_SRC_CNTL));
395 DRM_INFO(" TEX_CNTL = 0x%08x\n",
396 MACH64_READ(MACH64_TEX_CNTL));
397 DRM_INFO(" TEX_SIZE_PITCH = 0x%08x\n",
398 MACH64_READ(MACH64_TEX_SIZE_PITCH));
399 DRM_INFO(" TIMER_CONFIG = 0x%08x\n",
400 MACH64_READ(MACH64_TIMER_CONFIG));
402 DRM_INFO(" Z_CNTL = 0x%08x\n", MACH64_READ(MACH64_Z_CNTL));
403 DRM_INFO(" Z_OFF_PITCH = 0x%08x\n",
404 MACH64_READ(MACH64_Z_OFF_PITCH));
408 #define MACH64_DUMP_CONTEXT 3
411 * Used by mach64_dump_ring_info() to dump the contents of the current buffer
412 * pointed by the ring head.
414 static void mach64_dump_buf_info(drm_mach64_private_t *dev_priv,
417 u32 addr = GETBUFADDR(buf);
418 u32 used = buf->used >> 2;
419 u32 sys_addr = MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR);
420 u32 *p = GETBUFPTR(buf);
423 DRM_INFO("buffer contents:\n");
428 reg = le32_to_cpu(*p++);
429 if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
430 (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
431 addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
433 GETBUFADDR(buf) + buf->used - MACH64_DUMP_CONTEXT * 4) {
434 DRM_INFO("%08x: 0x%08x\n", addr, reg);
439 count = (reg >> 16) + 1;
442 while (count && used) {
443 if (addr <= GETBUFADDR(buf) + MACH64_DUMP_CONTEXT * 4 ||
444 (addr >= sys_addr - MACH64_DUMP_CONTEXT * 4 &&
445 addr <= sys_addr + MACH64_DUMP_CONTEXT * 4) ||
447 GETBUFADDR(buf) + buf->used -
448 MACH64_DUMP_CONTEXT * 4) {
449 DRM_INFO("%08x: 0x%04x = 0x%08x\n", addr,
450 reg, le32_to_cpu(*p));
471 * Dump the ring state and contents, including the contents of the buffer being
472 * processed by the graphics engine.
474 void mach64_dump_ring_info(drm_mach64_private_t *dev_priv)
476 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
481 DRM_INFO("ring contents:\n");
482 DRM_INFO(" head_addr: 0x%08x head: %u tail: %u\n\n",
483 ring->head_addr, ring->head, ring->tail);
486 for (i = 0; i < ring->size / sizeof(u32); i += 4) {
487 if (i <= MACH64_DUMP_CONTEXT * 4 ||
488 i >= ring->size / sizeof(u32) - MACH64_DUMP_CONTEXT * 4 ||
489 (i >= ring->tail - MACH64_DUMP_CONTEXT * 4 &&
490 i <= ring->tail + MACH64_DUMP_CONTEXT * 4) ||
491 (i >= ring->head - MACH64_DUMP_CONTEXT * 4 &&
492 i <= ring->head + MACH64_DUMP_CONTEXT * 4)) {
493 DRM_INFO(" 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x%s%s\n",
494 (u32)(ring->start_addr + i * sizeof(u32)),
495 le32_to_cpu(((u32 *) ring->start)[i + 0]),
496 le32_to_cpu(((u32 *) ring->start)[i + 1]),
497 le32_to_cpu(((u32 *) ring->start)[i + 2]),
498 le32_to_cpu(((u32 *) ring->start)[i + 3]),
499 i == ring->head ? " (head)" : "",
500 i == ring->tail ? " (tail)" : "");
512 if (ring->head >= 0 && ring->head < ring->size / sizeof(u32)) {
513 struct list_head *ptr;
514 u32 addr = le32_to_cpu(((u32 *) ring->start)[ring->head + 1]);
516 list_for_each(ptr, &dev_priv->pending) {
517 drm_mach64_freelist_t *entry =
518 list_entry(ptr, drm_mach64_freelist_t, list);
519 struct drm_buf *buf = entry->buf;
521 u32 buf_addr = GETBUFADDR(buf);
523 if (buf_addr <= addr && addr < buf_addr + buf->used)
524 mach64_dump_buf_info(dev_priv, buf);
529 DRM_INFO(" BM_GUI_TABLE = 0x%08x\n",
530 MACH64_READ(MACH64_BM_GUI_TABLE));
532 DRM_INFO("BM_FRAME_BUF_OFFSET = 0x%08x\n",
533 MACH64_READ(MACH64_BM_FRAME_BUF_OFFSET));
534 DRM_INFO(" BM_SYSTEM_MEM_ADDR = 0x%08x\n",
535 MACH64_READ(MACH64_BM_SYSTEM_MEM_ADDR));
536 DRM_INFO(" BM_COMMAND = 0x%08x\n",
537 MACH64_READ(MACH64_BM_COMMAND));
539 DRM_INFO(" BM_STATUS = 0x%08x\n",
540 MACH64_READ(MACH64_BM_STATUS));
541 DRM_INFO(" BUS_CNTL = 0x%08x\n",
542 MACH64_READ(MACH64_BUS_CNTL));
543 DRM_INFO(" FIFO_STAT = 0x%08x\n",
544 MACH64_READ(MACH64_FIFO_STAT));
545 DRM_INFO(" GUI_STAT = 0x%08x\n",
546 MACH64_READ(MACH64_GUI_STAT));
547 DRM_INFO(" SRC_CNTL = 0x%08x\n",
548 MACH64_READ(MACH64_SRC_CNTL));
554 /*******************************************************************/
555 /** \name DMA descriptor ring macros */
559 * Add the end mark to the ring's new tail position.
561 * The bus master engine will keep processing the DMA buffers listed in the ring
562 * until it finds this mark, making it stop.
564 * \sa mach64_clear_dma_eol
566 static __inline__ void mach64_set_dma_eol(volatile u32 *addr)
568 #if defined(__i386__)
571 /* Taken from include/asm-i386/bitops.h linux header */
572 __asm__ __volatile__("lock;" "btsl %1,%0":"=m"(*addr)
574 #elif defined(__powerpc__)
576 u32 mask = cpu_to_le32(MACH64_DMA_EOL);
578 /* Taken from the include/asm-ppc/bitops.h linux header */
579 __asm__ __volatile__("\n\
583 bne- 1b":"=&r"(old), "=m"(*addr)
584 :"r"(mask), "r"(addr), "m"(*addr)
586 #elif defined(__alpha__)
588 u32 mask = MACH64_DMA_EOL;
590 /* Taken from the include/asm-alpha/bitops.h linux header */
591 __asm__ __volatile__("1: ldl_l %0,%3\n"
597 ".previous":"=&r"(temp), "=m"(*addr)
598 :"Ir"(mask), "m"(*addr));
600 u32 mask = cpu_to_le32(MACH64_DMA_EOL);
607 * Remove the end mark from the ring's old tail position.
609 * It should be called after calling mach64_set_dma_eol to mark the ring's new
612 * We update the end marks while the bus master engine is in operation. Since
613 * the bus master engine may potentially be reading from the same position
614 * that we write, we must change atomically to avoid having intermediary bad
617 static __inline__ void mach64_clear_dma_eol(volatile u32 *addr)
619 #if defined(__i386__)
622 /* Taken from include/asm-i386/bitops.h linux header */
623 __asm__ __volatile__("lock;" "btrl %1,%0":"=m"(*addr)
625 #elif defined(__powerpc__)
627 u32 mask = cpu_to_le32(MACH64_DMA_EOL);
629 /* Taken from the include/asm-ppc/bitops.h linux header */
630 __asm__ __volatile__("\n\
634 bne- 1b":"=&r"(old), "=m"(*addr)
635 :"r"(mask), "r"(addr), "m"(*addr)
637 #elif defined(__alpha__)
639 u32 mask = ~MACH64_DMA_EOL;
641 /* Taken from the include/asm-alpha/bitops.h linux header */
642 __asm__ __volatile__("1: ldl_l %0,%3\n"
648 ".previous":"=&r"(temp), "=m"(*addr)
649 :"Ir"(mask), "m"(*addr));
651 u32 mask = cpu_to_le32(~MACH64_DMA_EOL);
657 #define RING_LOCALS \
658 int _ring_tail, _ring_write; unsigned int _ring_mask; volatile u32 *_ring
660 #define RING_WRITE_OFS _ring_write
662 #define BEGIN_RING(n) \
664 if (MACH64_VERBOSE) { \
665 DRM_INFO( "BEGIN_RING( %d ) \n", \
668 if (dev_priv->ring.space <= (n) * sizeof(u32)) { \
670 if ((ret = mach64_wait_ring( dev_priv, (n) * sizeof(u32))) < 0 ) { \
671 DRM_ERROR( "wait_ring failed, resetting engine\n"); \
672 mach64_dump_engine_info( dev_priv ); \
673 mach64_do_engine_reset( dev_priv ); \
677 dev_priv->ring.space -= (n) * sizeof(u32); \
678 _ring = (u32 *) dev_priv->ring.start; \
679 _ring_tail = _ring_write = dev_priv->ring.tail; \
680 _ring_mask = dev_priv->ring.tail_mask; \
683 #define OUT_RING( x ) \
685 if (MACH64_VERBOSE) { \
686 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
687 (unsigned int)(x), _ring_write ); \
689 _ring[_ring_write++] = cpu_to_le32( x ); \
690 _ring_write &= _ring_mask; \
693 #define ADVANCE_RING() \
695 if (MACH64_VERBOSE) { \
696 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
697 _ring_write, _ring_tail ); \
699 DRM_MEMORYBARRIER(); \
700 mach64_clear_dma_eol( &_ring[(_ring_tail - 2) & _ring_mask] ); \
701 DRM_MEMORYBARRIER(); \
702 dev_priv->ring.tail = _ring_write; \
703 mach64_ring_tick( dev_priv, &(dev_priv)->ring ); \
707 * Queue a DMA buffer of registers writes into the ring buffer.
709 int mach64_add_buf_to_ring(drm_mach64_private_t *dev_priv,
710 drm_mach64_freelist_t *entry)
712 int bytes, pages, remainder;
715 struct drm_buf *buf = entry->buf;
719 address = GETBUFADDR( buf );
720 pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE;
722 BEGIN_RING( pages * 4 );
724 for ( i = 0 ; i < pages-1 ; i++ ) {
725 page = address + i * MACH64_DMA_CHUNKSIZE;
726 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
728 OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET );
732 /* generate the final descriptor for any remaining commands in this buffer */
733 page = address + i * MACH64_DMA_CHUNKSIZE;
734 remainder = bytes - i * MACH64_DMA_CHUNKSIZE;
736 /* Save dword offset of last descriptor for this buffer.
737 * This is needed to check for completion of the buffer in freelist_get
739 entry->ring_ofs = RING_WRITE_OFS;
741 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
743 OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL );
752 * Queue DMA buffer controlling host data tranfers (e.g., blit).
754 * Almost identical to mach64_add_buf_to_ring.
756 int mach64_add_hostdata_buf_to_ring(drm_mach64_private_t *dev_priv,
757 drm_mach64_freelist_t *entry)
759 int bytes, pages, remainder;
762 struct drm_buf *buf = entry->buf;
765 bytes = buf->used - MACH64_HOSTDATA_BLIT_OFFSET;
766 pages = (bytes + MACH64_DMA_CHUNKSIZE - 1) / MACH64_DMA_CHUNKSIZE;
767 address = GETBUFADDR( buf );
769 BEGIN_RING( 4 + pages * 4 );
771 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_ADDR );
773 OUT_RING( MACH64_HOSTDATA_BLIT_OFFSET | MACH64_DMA_HOLD_OFFSET );
775 address += MACH64_HOSTDATA_BLIT_OFFSET;
777 for ( i = 0 ; i < pages-1 ; i++ ) {
778 page = address + i * MACH64_DMA_CHUNKSIZE;
779 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA );
781 OUT_RING( MACH64_DMA_CHUNKSIZE | MACH64_DMA_HOLD_OFFSET );
785 /* generate the final descriptor for any remaining commands in this buffer */
786 page = address + i * MACH64_DMA_CHUNKSIZE;
787 remainder = bytes - i * MACH64_DMA_CHUNKSIZE;
789 /* Save dword offset of last descriptor for this buffer.
790 * This is needed to check for completion of the buffer in freelist_get
792 entry->ring_ofs = RING_WRITE_OFS;
794 OUT_RING( MACH64_APERTURE_OFFSET + MACH64_BM_HOSTDATA );
796 OUT_RING( remainder | MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL );
807 /*******************************************************************/
808 /** \name DMA test and initialization */
812 * Perform a simple DMA operation using the pattern registers to test whether
815 * \return zero if successful.
817 * \note This function was the testbed for many experiences regarding Mach64
818 * DMA operation. It is left here since it so tricky to get DMA operating
819 * properly in some architectures and hardware.
821 static int mach64_bm_dma_test(struct drm_device * dev)
823 drm_mach64_private_t *dev_priv = dev->dev_private;
824 drm_dma_handle_t *cpu_addr_dmah;
828 u32 src_cntl, pat_reg0, pat_reg1;
829 int i, count, failed;
833 table = (u32 *) dev_priv->ring.start;
835 /* FIXME: get a dma buffer from the freelist here */
836 DRM_DEBUG("Allocating data memory ...\n");
838 drm_pci_alloc(dev, 0x1000, 0x1000, 0xfffffffful);
839 if (!cpu_addr_dmah) {
840 DRM_INFO("data-memory allocation failed!\n");
843 data = (u32 *) cpu_addr_dmah->vaddr;
844 data_addr = (u32) cpu_addr_dmah->busaddr;
847 /* Save the X server's value for SRC_CNTL and restore it
848 * in case our test fails. This prevents the X server
849 * from disabling it's cache for this register
851 src_cntl = MACH64_READ(MACH64_SRC_CNTL);
852 pat_reg0 = MACH64_READ(MACH64_PAT_REG0);
853 pat_reg1 = MACH64_READ(MACH64_PAT_REG1);
855 mach64_do_wait_for_fifo(dev_priv, 3);
857 MACH64_WRITE(MACH64_SRC_CNTL, 0);
858 MACH64_WRITE(MACH64_PAT_REG0, 0x11111111);
859 MACH64_WRITE(MACH64_PAT_REG1, 0x11111111);
861 mach64_do_wait_for_idle(dev_priv);
863 for (i = 0; i < 2; i++) {
865 reg = MACH64_READ((MACH64_PAT_REG0 + i * 4));
866 DRM_DEBUG("(Before DMA Transfer) reg %d = 0x%08x\n", i, reg);
867 if (reg != 0x11111111) {
868 DRM_INFO("Error initializing test registers\n");
869 DRM_INFO("resetting engine ...\n");
870 mach64_do_engine_reset(dev_priv);
871 DRM_INFO("freeing data buffer memory.\n");
872 drm_pci_free(dev, cpu_addr_dmah);
877 /* fill up a buffer with sets of 2 consecutive writes starting with PAT_REG0 */
880 data[count++] = cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16));
881 data[count++] = expected[0] = 0x22222222;
882 data[count++] = expected[1] = 0xaaaaaaaa;
884 while (count < 1020) {
886 cpu_to_le32(DMAREG(MACH64_PAT_REG0) | (1 << 16));
887 data[count++] = 0x22222222;
888 data[count++] = 0xaaaaaaaa;
890 data[count++] = cpu_to_le32(DMAREG(MACH64_SRC_CNTL) | (0 << 16));
893 DRM_DEBUG("Preparing table ...\n");
894 table[MACH64_DMA_FRAME_BUF_OFFSET] = cpu_to_le32(MACH64_BM_ADDR +
895 MACH64_APERTURE_OFFSET);
896 table[MACH64_DMA_SYS_MEM_ADDR] = cpu_to_le32(data_addr);
897 table[MACH64_DMA_COMMAND] = cpu_to_le32(count * sizeof(u32)
898 | MACH64_DMA_HOLD_OFFSET
900 table[MACH64_DMA_RESERVED] = 0;
902 DRM_DEBUG("table[0] = 0x%08x\n", table[0]);
903 DRM_DEBUG("table[1] = 0x%08x\n", table[1]);
904 DRM_DEBUG("table[2] = 0x%08x\n", table[2]);
905 DRM_DEBUG("table[3] = 0x%08x\n", table[3]);
907 for (i = 0; i < 6; i++) {
908 DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]);
911 for (i = count - 5; i < count; i++) {
912 DRM_DEBUG(" data[%d] = 0x%08x\n", i, data[i]);
917 DRM_DEBUG("waiting for idle...\n");
918 if ((i = mach64_do_wait_for_idle(dev_priv))) {
919 DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i);
920 DRM_INFO("resetting engine ...\n");
921 mach64_do_engine_reset(dev_priv);
922 mach64_do_wait_for_fifo(dev_priv, 3);
923 MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
924 MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
925 MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
926 DRM_INFO("freeing data buffer memory.\n");
927 drm_pci_free(dev, cpu_addr_dmah);
930 DRM_DEBUG("waiting for idle...done\n");
932 DRM_DEBUG("BUS_CNTL = 0x%08x\n", MACH64_READ(MACH64_BUS_CNTL));
933 DRM_DEBUG("SRC_CNTL = 0x%08x\n", MACH64_READ(MACH64_SRC_CNTL));
935 DRM_DEBUG("data bus addr = 0x%08x\n", data_addr);
936 DRM_DEBUG("table bus addr = 0x%08x\n", dev_priv->ring.start_addr);
938 DRM_DEBUG("starting DMA transfer...\n");
939 MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
940 dev_priv->ring.start_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
942 MACH64_WRITE(MACH64_SRC_CNTL,
943 MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
944 MACH64_SRC_BM_OP_SYSTEM_TO_REG);
946 /* Kick off the transfer */
947 DRM_DEBUG("starting DMA transfer... done.\n");
948 MACH64_WRITE(MACH64_DST_HEIGHT_WIDTH, 0);
950 DRM_DEBUG("waiting for idle...\n");
952 if ((i = mach64_do_wait_for_idle(dev_priv))) {
953 /* engine locked up, dump register state and reset */
954 DRM_INFO("mach64_do_wait_for_idle failed (result=%d)\n", i);
955 mach64_dump_engine_info(dev_priv);
956 DRM_INFO("resetting engine ...\n");
957 mach64_do_engine_reset(dev_priv);
958 mach64_do_wait_for_fifo(dev_priv, 3);
959 MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
960 MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
961 MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
962 DRM_INFO("freeing data buffer memory.\n");
963 drm_pci_free(dev, cpu_addr_dmah);
967 DRM_DEBUG("waiting for idle...done\n");
969 /* restore SRC_CNTL */
970 mach64_do_wait_for_fifo(dev_priv, 1);
971 MACH64_WRITE(MACH64_SRC_CNTL, src_cntl);
975 /* Check register values to see if the GUI master operation succeeded */
976 for (i = 0; i < 2; i++) {
978 reg = MACH64_READ((MACH64_PAT_REG0 + i * 4));
979 DRM_DEBUG("(After DMA Transfer) reg %d = 0x%08x\n", i, reg);
980 if (reg != expected[i]) {
985 /* restore pattern registers */
986 mach64_do_wait_for_fifo(dev_priv, 2);
987 MACH64_WRITE(MACH64_PAT_REG0, pat_reg0);
988 MACH64_WRITE(MACH64_PAT_REG1, pat_reg1);
990 DRM_DEBUG("freeing data buffer memory.\n");
991 drm_pci_free(dev, cpu_addr_dmah);
992 DRM_DEBUG("returning ...\n");
998 * Called during the DMA initialization ioctl to initialize all the necessary
999 * software and hardware state for DMA operation.
1001 static int mach64_do_dma_init(struct drm_device * dev, drm_mach64_init_t * init)
1003 drm_mach64_private_t *dev_priv;
1009 dev_priv = drm_alloc(sizeof(drm_mach64_private_t), DRM_MEM_DRIVER);
1010 if (dev_priv == NULL)
1013 memset(dev_priv, 0, sizeof(drm_mach64_private_t));
1015 dev_priv->is_pci = init->is_pci;
1017 dev_priv->fb_bpp = init->fb_bpp;
1018 dev_priv->front_offset = init->front_offset;
1019 dev_priv->front_pitch = init->front_pitch;
1020 dev_priv->back_offset = init->back_offset;
1021 dev_priv->back_pitch = init->back_pitch;
1023 dev_priv->depth_bpp = init->depth_bpp;
1024 dev_priv->depth_offset = init->depth_offset;
1025 dev_priv->depth_pitch = init->depth_pitch;
1027 dev_priv->front_offset_pitch = (((dev_priv->front_pitch / 8) << 22) |
1028 (dev_priv->front_offset >> 3));
1029 dev_priv->back_offset_pitch = (((dev_priv->back_pitch / 8) << 22) |
1030 (dev_priv->back_offset >> 3));
1031 dev_priv->depth_offset_pitch = (((dev_priv->depth_pitch / 8) << 22) |
1032 (dev_priv->depth_offset >> 3));
1034 dev_priv->usec_timeout = 1000000;
1036 /* Set up the freelist, placeholder list and pending list */
1037 INIT_LIST_HEAD(&dev_priv->free_list);
1038 INIT_LIST_HEAD(&dev_priv->placeholders);
1039 INIT_LIST_HEAD(&dev_priv->pending);
1041 dev_priv->sarea = drm_getsarea(dev);
1042 if (!dev_priv->sarea) {
1043 DRM_ERROR("can not find sarea!\n");
1044 dev->dev_private = (void *)dev_priv;
1045 mach64_do_cleanup_dma(dev);
1048 dev_priv->fb = drm_core_findmap(dev, init->fb_offset);
1049 if (!dev_priv->fb) {
1050 DRM_ERROR("can not find frame buffer map!\n");
1051 dev->dev_private = (void *)dev_priv;
1052 mach64_do_cleanup_dma(dev);
1055 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
1056 if (!dev_priv->mmio) {
1057 DRM_ERROR("can not find mmio map!\n");
1058 dev->dev_private = (void *)dev_priv;
1059 mach64_do_cleanup_dma(dev);
1063 dev_priv->ring_map = drm_core_findmap(dev, init->ring_offset);
1064 if (!dev_priv->ring_map) {
1065 DRM_ERROR("can not find ring map!\n");
1066 dev->dev_private = (void *)dev_priv;
1067 mach64_do_cleanup_dma(dev);
1071 dev_priv->sarea_priv = (drm_mach64_sarea_t *)
1072 ((u8 *) dev_priv->sarea->handle + init->sarea_priv_offset);
1074 if (!dev_priv->is_pci) {
1075 drm_core_ioremap(dev_priv->ring_map, dev);
1076 if (!dev_priv->ring_map->handle) {
1077 DRM_ERROR("can not ioremap virtual address for"
1078 " descriptor ring\n");
1079 dev->dev_private = (void *)dev_priv;
1080 mach64_do_cleanup_dma(dev);
1083 dev->agp_buffer_token = init->buffers_offset;
1084 dev->agp_buffer_map =
1085 drm_core_findmap(dev, init->buffers_offset);
1086 if (!dev->agp_buffer_map) {
1087 DRM_ERROR("can not find dma buffer map!\n");
1088 dev->dev_private = (void *)dev_priv;
1089 mach64_do_cleanup_dma(dev);
1092 /* there might be a nicer way to do this -
1093 dev isn't passed all the way though the mach64 - DA */
1094 dev_priv->dev_buffers = dev->agp_buffer_map;
1096 drm_core_ioremap(dev->agp_buffer_map, dev);
1097 if (!dev->agp_buffer_map->handle) {
1098 DRM_ERROR("can not ioremap virtual address for"
1100 dev->dev_private = (void *)dev_priv;
1101 mach64_do_cleanup_dma(dev);
1104 dev_priv->agp_textures =
1105 drm_core_findmap(dev, init->agp_textures_offset);
1106 if (!dev_priv->agp_textures) {
1107 DRM_ERROR("can not find agp texture region!\n");
1108 dev->dev_private = (void *)dev_priv;
1109 mach64_do_cleanup_dma(dev);
1114 dev->dev_private = (void *)dev_priv;
1116 dev_priv->driver_mode = init->dma_mode;
1118 /* changing the FIFO size from the default causes problems with DMA */
1119 tmp = MACH64_READ(MACH64_GUI_CNTL);
1120 if ((tmp & MACH64_CMDFIFO_SIZE_MASK) != MACH64_CMDFIFO_SIZE_128) {
1121 DRM_INFO("Setting FIFO size to 128 entries\n");
1122 /* FIFO must be empty to change the FIFO depth */
1123 if ((ret = mach64_do_wait_for_idle(dev_priv))) {
1125 ("wait for idle failed before changing FIFO depth!\n");
1126 mach64_do_cleanup_dma(dev);
1129 MACH64_WRITE(MACH64_GUI_CNTL, ((tmp & ~MACH64_CMDFIFO_SIZE_MASK)
1130 | MACH64_CMDFIFO_SIZE_128));
1131 /* need to read GUI_STAT for proper sync according to docs */
1132 if ((ret = mach64_do_wait_for_idle(dev_priv))) {
1134 ("wait for idle failed when changing FIFO depth!\n");
1135 mach64_do_cleanup_dma(dev);
1140 dev_priv->ring.size = 0x4000; /* 16KB */
1141 dev_priv->ring.start = dev_priv->ring_map->handle;
1142 dev_priv->ring.start_addr = (u32) dev_priv->ring_map->offset;
1144 memset(dev_priv->ring.start, 0, dev_priv->ring.size);
1145 DRM_INFO("descriptor ring: cpu addr %p, bus addr: 0x%08x\n",
1146 dev_priv->ring.start, dev_priv->ring.start_addr);
1149 if (dev_priv->driver_mode != MACH64_MODE_MMIO) {
1151 /* enable block 1 registers and bus mastering */
1152 MACH64_WRITE(MACH64_BUS_CNTL, ((MACH64_READ(MACH64_BUS_CNTL)
1153 | MACH64_BUS_EXT_REG_EN)
1154 & ~MACH64_BUS_MASTER_DIS));
1156 /* try a DMA GUI-mastering pass and fall back to MMIO if it fails */
1157 DRM_DEBUG("Starting DMA test...\n");
1158 if ((ret = mach64_bm_dma_test(dev))) {
1159 dev_priv->driver_mode = MACH64_MODE_MMIO;
1163 switch (dev_priv->driver_mode) {
1164 case MACH64_MODE_MMIO:
1165 MACH64_WRITE(MACH64_BUS_CNTL, (MACH64_READ(MACH64_BUS_CNTL)
1166 | MACH64_BUS_EXT_REG_EN
1167 | MACH64_BUS_MASTER_DIS));
1168 if (init->dma_mode == MACH64_MODE_MMIO)
1169 DRM_INFO("Forcing pseudo-DMA mode\n");
1172 ("DMA test failed (ret=%d), using pseudo-DMA mode\n",
1175 case MACH64_MODE_DMA_SYNC:
1176 DRM_INFO("DMA test succeeded, using synchronous DMA mode\n");
1178 case MACH64_MODE_DMA_ASYNC:
1180 DRM_INFO("DMA test succeeded, using asynchronous DMA mode\n");
1183 dev_priv->ring_running = 0;
1185 /* setup offsets for physical address of table start and end */
1186 dev_priv->ring.head_addr = dev_priv->ring.start_addr;
1187 dev_priv->ring.head = dev_priv->ring.tail = 0;
1188 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1189 dev_priv->ring.space = dev_priv->ring.size;
1191 /* setup physical address and size of descriptor table */
1192 mach64_do_wait_for_fifo(dev_priv, 1);
1193 MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
1195 head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB));
1197 /* init frame counter */
1198 dev_priv->sarea_priv->frames_queued = 0;
1199 for (i = 0; i < MACH64_MAX_QUEUED_FRAMES; i++) {
1200 dev_priv->frame_ofs[i] = ~0; /* All ones indicates placeholder */
1203 /* Allocate the DMA buffer freelist */
1204 if ((ret = mach64_init_freelist(dev))) {
1205 DRM_ERROR("Freelist allocation failed\n");
1206 mach64_do_cleanup_dma(dev);
1213 /*******************************************************************/
1214 /** MMIO Pseudo-DMA (intended primarily for debugging, not performance)
1217 int mach64_do_dispatch_pseudo_dma(drm_mach64_private_t *dev_priv)
1219 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
1220 volatile u32 *ring_read;
1221 struct list_head *ptr;
1222 drm_mach64_freelist_t *entry;
1223 struct drm_buf *buf = NULL;
1225 u32 used, reg, target;
1226 int fifo, count, found, ret, no_idle_wait;
1228 fifo = count = reg = no_idle_wait = 0;
1229 target = MACH64_BM_ADDR;
1231 if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) {
1232 DRM_INFO("idle failed before pseudo-dma dispatch, resetting engine\n");
1233 mach64_dump_engine_info(dev_priv);
1234 mach64_do_engine_reset(dev_priv);
1238 ring_read = (u32 *) ring->start;
1240 while (ring->tail != ring->head) {
1241 u32 buf_addr, new_target, offset;
1242 u32 bytes, remaining, head, eol;
1247 le32_to_cpu(ring_read[head++]) - MACH64_APERTURE_OFFSET;
1248 buf_addr = le32_to_cpu(ring_read[head++]);
1249 eol = le32_to_cpu(ring_read[head]) & MACH64_DMA_EOL;
1250 bytes = le32_to_cpu(ring_read[head++])
1251 & ~(MACH64_DMA_HOLD_OFFSET | MACH64_DMA_EOL);
1253 head &= ring->tail_mask;
1255 /* can't wait for idle between a blit setup descriptor
1256 * and a HOSTDATA descriptor or the engine will lock
1258 if (new_target == MACH64_BM_HOSTDATA
1259 && target == MACH64_BM_ADDR)
1262 target = new_target;
1266 list_for_each(ptr, &dev_priv->pending) {
1267 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1269 offset = buf_addr - GETBUFADDR(buf);
1270 if (offset >= 0 && offset < MACH64_BUFFER_SIZE) {
1276 if (!found || buf == NULL) {
1278 ("Couldn't find pending buffer: head: %u tail: %u buf_addr: 0x%08x %s\n",
1279 head, ring->tail, buf_addr, (eol ? "eol" : ""));
1280 mach64_dump_ring_info(dev_priv);
1281 mach64_do_engine_reset(dev_priv);
1285 /* Hand feed the buffer to the card via MMIO, waiting for the fifo
1288 DRM_DEBUG("target: (0x%08x) %s\n", target,
1290 MACH64_BM_HOSTDATA ? "BM_HOSTDATA" : "BM_ADDR"));
1291 DRM_DEBUG("offset: %u bytes: %u used: %u\n", offset, bytes,
1294 remaining = (buf->used - offset) >> 2; /* dwords remaining in buffer */
1295 used = bytes >> 2; /* dwords in buffer for this descriptor */
1296 buf_ptr = (u32 *) ((char *)GETBUFPTR(buf) + offset);
1301 if (target == MACH64_BM_HOSTDATA) {
1302 reg = DMAREG(MACH64_HOST_DATA0);
1304 (remaining > 16) ? 16 : remaining;
1307 reg = le32_to_cpu(*buf_ptr++);
1309 count = (reg >> 16) + 1;
1313 reg = MMSELECT(reg);
1315 while (count && used) {
1319 mach64_do_wait_for_fifo
1320 (dev_priv, 16)) < 0) {
1326 mach64_do_wait_for_idle
1334 MACH64_WRITE(reg, le32_to_cpu(*buf_ptr++));
1343 ring->head_addr = ring->start_addr + (ring->head * sizeof(u32));
1344 ring->space += (4 * sizeof(u32));
1347 if ((ret = mach64_do_wait_for_idle(dev_priv)) < 0) {
1350 MACH64_WRITE(MACH64_BM_GUI_TABLE_CMD,
1351 ring->head_addr | MACH64_CIRCULAR_BUF_SIZE_16KB);
1353 DRM_DEBUG("completed\n");
1360 /*******************************************************************/
1361 /** \name DMA cleanup */
1364 int mach64_do_cleanup_dma(struct drm_device * dev)
1368 /* Make sure interrupts are disabled here because the uninstall ioctl
1369 * may not have been called from userspace and after dev_private
1370 * is freed, it's too late.
1373 drm_irq_uninstall(dev);
1375 if (dev->dev_private) {
1376 drm_mach64_private_t *dev_priv = dev->dev_private;
1378 if (!dev_priv->is_pci) {
1379 if (dev_priv->ring_map)
1380 drm_core_ioremapfree(dev_priv->ring_map, dev);
1382 if (dev->agp_buffer_map) {
1383 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1384 dev->agp_buffer_map = NULL;
1388 mach64_destroy_freelist(dev);
1390 drm_free(dev_priv, sizeof(drm_mach64_private_t),
1392 dev->dev_private = NULL;
1401 /*******************************************************************/
1402 /** \name IOCTL handlers */
1405 int mach64_dma_init(struct drm_device *dev, void *data,
1406 struct drm_file *file_priv)
1408 drm_mach64_init_t *init = data;
1412 LOCK_TEST_WITH_RETURN(dev, file_priv);
1414 switch (init->func) {
1415 case DRM_MACH64_INIT_DMA:
1416 return mach64_do_dma_init(dev, init);
1417 case DRM_MACH64_CLEANUP_DMA:
1418 return mach64_do_cleanup_dma(dev);
1424 int mach64_dma_idle(struct drm_device *dev, void *data,
1425 struct drm_file *file_priv)
1427 drm_mach64_private_t *dev_priv = dev->dev_private;
1431 LOCK_TEST_WITH_RETURN(dev, file_priv);
1433 return mach64_do_dma_idle(dev_priv);
1436 int mach64_dma_flush(struct drm_device *dev, void *data,
1437 struct drm_file *file_priv)
1439 drm_mach64_private_t *dev_priv = dev->dev_private;
1443 LOCK_TEST_WITH_RETURN(dev, file_priv);
1445 return mach64_do_dma_flush(dev_priv);
1448 int mach64_engine_reset(struct drm_device *dev, void *data,
1449 struct drm_file *file_priv)
1451 drm_mach64_private_t *dev_priv = dev->dev_private;
1455 LOCK_TEST_WITH_RETURN(dev, file_priv);
1457 return mach64_do_engine_reset(dev_priv);
1463 /*******************************************************************/
1464 /** \name Freelist management */
1467 int mach64_init_freelist(struct drm_device * dev)
1469 struct drm_device_dma *dma = dev->dma;
1470 drm_mach64_private_t *dev_priv = dev->dev_private;
1471 drm_mach64_freelist_t *entry;
1472 struct list_head *ptr;
1475 DRM_DEBUG("adding %d buffers to freelist\n", dma->buf_count);
1477 for (i = 0; i < dma->buf_count; i++) {
1479 (drm_mach64_freelist_t *)
1480 drm_alloc(sizeof(drm_mach64_freelist_t),
1481 DRM_MEM_BUFLISTS)) == NULL)
1483 memset(entry, 0, sizeof(drm_mach64_freelist_t));
1484 entry->buf = dma->buflist[i];
1486 list_add_tail(ptr, &dev_priv->free_list);
1492 void mach64_destroy_freelist(struct drm_device * dev)
1494 drm_mach64_private_t *dev_priv = dev->dev_private;
1495 drm_mach64_freelist_t *entry;
1496 struct list_head *ptr;
1497 struct list_head *tmp;
1501 list_for_each_safe(ptr, tmp, &dev_priv->pending) {
1503 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1504 drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
1506 list_for_each_safe(ptr, tmp, &dev_priv->placeholders) {
1508 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1509 drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
1512 list_for_each_safe(ptr, tmp, &dev_priv->free_list) {
1514 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1515 drm_free(entry, sizeof(*entry), DRM_MEM_BUFLISTS);
1519 /* IMPORTANT: This function should only be called when the engine is idle or locked up,
1520 * as it assumes all buffers in the pending list have been completed by the hardware.
1522 int mach64_do_release_used_buffers(drm_mach64_private_t *dev_priv)
1524 struct list_head *ptr;
1525 struct list_head *tmp;
1526 drm_mach64_freelist_t *entry;
1529 if (list_empty(&dev_priv->pending))
1532 /* Iterate the pending list and move all buffers into the freelist... */
1534 list_for_each_safe(ptr, tmp, &dev_priv->pending) {
1535 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1536 if (entry->discard) {
1537 entry->buf->pending = 0;
1539 list_add_tail(ptr, &dev_priv->free_list);
1544 DRM_DEBUG("released %d buffers from pending list\n", i);
1549 static int mach64_do_reclaim_completed(drm_mach64_private_t *dev_priv)
1551 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
1552 struct list_head *ptr;
1553 struct list_head *tmp;
1554 drm_mach64_freelist_t *entry;
1555 u32 head, tail, ofs;
1557 mach64_ring_tick(dev_priv, ring);
1562 #if MACH64_EXTRA_CHECKING
1563 if (MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) {
1564 DRM_ERROR("Empty ring with non-idle engine!\n");
1565 mach64_dump_ring_info(dev_priv);
1569 /* last pass is complete, so release everything */
1570 mach64_do_release_used_buffers(dev_priv);
1571 DRM_DEBUG("idle engine, freed all buffers.\n");
1572 if (list_empty(&dev_priv->free_list)) {
1573 DRM_ERROR("Freelist empty with idle engine\n");
1578 /* Look for a completed buffer and bail out of the loop
1579 * as soon as we find one -- don't waste time trying
1580 * to free extra bufs here, leave that to do_release_used_buffers
1582 list_for_each_safe(ptr, tmp, &dev_priv->pending) {
1583 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1584 ofs = entry->ring_ofs;
1585 if (entry->discard &&
1586 ((head < tail && (ofs < head || ofs >= tail)) ||
1587 (head > tail && (ofs < head && ofs >= tail)))) {
1588 #if MACH64_EXTRA_CHECKING
1591 for (i = head; i != tail; i = (i + 4) & ring->tail_mask)
1593 u32 o1 = le32_to_cpu(((u32 *) ring->
1595 u32 o2 = GETBUFADDR(entry->buf);
1599 ("Attempting to free used buffer: "
1600 "i=%d buf=0x%08x\n",
1602 mach64_dump_ring_info(dev_priv);
1607 /* found a processed buffer */
1608 entry->buf->pending = 0;
1610 list_add_tail(ptr, &dev_priv->free_list);
1612 ("freed processed buffer (head=%d tail=%d "
1613 "buf ring ofs=%d).\n",
1622 struct drm_buf *mach64_freelist_get(drm_mach64_private_t *dev_priv)
1624 drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
1625 drm_mach64_freelist_t *entry;
1626 struct list_head *ptr;
1629 if (list_empty(&dev_priv->free_list)) {
1630 if (list_empty(&dev_priv->pending)) {
1632 ("Couldn't get buffer - pending and free lists empty\n");
1634 list_for_each(ptr, &dev_priv->placeholders) {
1637 DRM_INFO("Placeholders: %d\n", t);
1641 for (t = 0; t < dev_priv->usec_timeout; t++) {
1644 ret = mach64_do_reclaim_completed(dev_priv);
1646 goto _freelist_entry_found;
1652 mach64_dump_ring_info(dev_priv);
1654 ("timeout waiting for buffers: ring head_addr: 0x%08x head: %d tail: %d\n",
1655 ring->head_addr, ring->head, ring->tail);
1659 _freelist_entry_found:
1660 ptr = dev_priv->free_list.next;
1662 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1663 entry->buf->used = 0;
1664 list_add_tail(ptr, &dev_priv->placeholders);
1668 int mach64_freelist_put(drm_mach64_private_t *dev_priv, struct drm_buf *copy_buf)
1670 struct list_head *ptr;
1671 drm_mach64_freelist_t *entry;
1673 #if MACH64_EXTRA_CHECKING
1674 list_for_each(ptr, &dev_priv->pending) {
1675 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1676 if (copy_buf == entry->buf) {
1677 DRM_ERROR("Trying to release a pending buf\n");
1682 ptr = dev_priv->placeholders.next;
1683 entry = list_entry(ptr, drm_mach64_freelist_t, list);
1684 copy_buf->pending = 0;
1686 entry->buf = copy_buf;
1689 list_add_tail(ptr, &dev_priv->free_list);
1697 /*******************************************************************/
1698 /** \name DMA buffer request and submission IOCTL handler */
1701 static int mach64_dma_get_buffers(struct drm_device *dev,
1702 struct drm_file *file_priv,
1706 struct drm_buf *buf;
1707 drm_mach64_private_t *dev_priv = dev->dev_private;
1709 for (i = d->granted_count; i < d->request_count; i++) {
1710 buf = mach64_freelist_get(dev_priv);
1711 #if MACH64_EXTRA_CHECKING
1719 buf->file_priv = file_priv;
1721 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1724 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1725 sizeof(buf->total)))
1733 int mach64_dma_buffers(struct drm_device *dev, void *data,
1734 struct drm_file *file_priv)
1736 struct drm_device_dma *dma = dev->dma;
1737 struct drm_dma *d = data;
1740 LOCK_TEST_WITH_RETURN(dev, file_priv);
1742 /* Please don't send us buffers.
1744 if (d->send_count != 0) {
1745 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1746 DRM_CURRENTPID, d->send_count);
1750 /* We'll send you buffers.
1752 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1753 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1754 DRM_CURRENTPID, d->request_count, dma->buf_count);
1758 d->granted_count = 0;
1760 if (d->request_count) {
1761 ret = mach64_dma_get_buffers(dev, file_priv, d);
1767 void mach64_driver_lastclose(struct drm_device * dev)
1769 mach64_do_cleanup_dma(dev);