shared-core/mga_dma.c

   1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
   2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
   3  */
   4 /* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
   5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  */
  27
  28 /**
  29  * \file mga_dma.c
  30  * DMA support for MGA G200 / G400.
  31  *
  32  * \author Rickard E. (Rik) Faith <faith@valinux.com>
  33  * \author Jeff Hartmann <jhartmann@valinux.com>
  34  * \author Keith Whitwell <keith@tungstengraphics.com>
  35  * \author Gareth Hughes <gareth@valinux.com>
  36  */
  37
  38 #include "drmP.h"
  39 #include "drm.h"
  40 #include "drm_sarea.h"
  41 #include "mga_drm.h"
  42 #include "mga_drv.h"
  43
  44 #define MGA_DEFAULT_USEC_TIMEOUT        10000
  45 #define MGA_FREELIST_DEBUG              0
  46
  47 #define MINIMAL_CLEANUP    0
  48 #define FULL_CLEANUP       1
  49 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
  50
  51 /* ================================================================
  52  * Engine control
  53  */
  54
  55 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
  56 {
  57         u32 status = 0;
  58         int i;
  59         DRM_DEBUG("\n");
  60
  61         for (i = 0; i < dev_priv->usec_timeout; i++) {
  62                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
  63                 if (status == MGA_ENDPRDMASTS) {
  64                         MGA_WRITE8(MGA_CRTC_INDEX, 0);
  65                         return 0;
  66                 }
  67                 DRM_UDELAY(1);
  68         }
  69
  70 #if MGA_DMA_DEBUG
  71         DRM_ERROR("failed!\n");
  72         DRM_INFO("   status=0x%08x\n", status);
  73 #endif
  74         return -EBUSY;
  75 }
  76
  77 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
  78 {
  79         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
  80         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
  81
  82         DRM_DEBUG("\n");
  83
  84         /* The primary DMA stream should look like new right about now.
  85          */
  86         primary->tail = 0;
  87         primary->space = primary->size;
  88         primary->last_flush = 0;
  89
  90         sarea_priv->last_wrap = 0;
  91
  92         /* FIXME: Reset counters, buffer ages etc...
  93          */
  94
  95         /* FIXME: What else do we need to reinitialize?  WARP stuff?
  96          */
  97
  98         return 0;
  99 }
 100
 101 /* ================================================================
 102  * Primary DMA stream
 103  */
 104
 105 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
 106 {
 107         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 108         u32 head, tail;
 109         u32 status = 0;
 110         int i;
 111         DMA_LOCALS;
 112         DRM_DEBUG("\n");
 113
 114         /* We need to wait so that we can do an safe flush */
 115         for (i = 0; i < dev_priv->usec_timeout; i++) {
 116                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
 117                 if (status == MGA_ENDPRDMASTS)
 118                         break;
 119                 DRM_UDELAY(1);
 120         }
 121
 122         if (primary->tail == primary->last_flush) {
 123                 DRM_DEBUG("   bailing out...\n");
 124                 return;
 125         }
 126
 127         tail = primary->tail + dev_priv->primary->offset;
 128
 129         /* We need to pad the stream between flushes, as the card
 130          * actually (partially?) reads the first of these commands.
 131          * See page 4-16 in the G400 manual, middle of the page or so.
 132          */
 133         BEGIN_DMA(1);
 134
 135         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 136                   MGA_DMAPAD, 0x00000000,
 137                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 138
 139         ADVANCE_DMA();
 140
 141         primary->last_flush = primary->tail;
 142
 143         head = MGA_READ(MGA_PRIMADDRESS);
 144
 145         if (head <= tail) {
 146                 primary->space = primary->size - primary->tail;
 147         } else {
 148                 primary->space = head - tail;
 149         }
 150
 151         DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
 152         DRM_DEBUG("   tail = 0x%06lx\n", tail - dev_priv->primary->offset);
 153         DRM_DEBUG("  space = 0x%06x\n", primary->space);
 154
 155         mga_flush_write_combine();
 156         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 157
 158         DRM_DEBUG("done.\n");
 159 }
 160
 161 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
 162 {
 163         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 164         u32 head, tail;
 165         DMA_LOCALS;
 166         DRM_DEBUG("\n");
 167
 168         BEGIN_DMA_WRAP();
 169
 170         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
 171                   MGA_DMAPAD, 0x00000000,
 172                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
 173
 174         ADVANCE_DMA();
 175
 176         tail = primary->tail + dev_priv->primary->offset;
 177
 178         primary->tail = 0;
 179         primary->last_flush = 0;
 180         primary->last_wrap++;
 181
 182         head = MGA_READ(MGA_PRIMADDRESS);
 183
 184         if (head == dev_priv->primary->offset) {
 185                 primary->space = primary->size;
 186         } else {
 187                 primary->space = head - dev_priv->primary->offset;
 188         }
 189
 190         DRM_DEBUG("   head = 0x%06lx\n", head - dev_priv->primary->offset);
 191         DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
 192         DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
 193         DRM_DEBUG("  space = 0x%06x\n", primary->space);
 194
 195         mga_flush_write_combine();
 196         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
 197
 198         set_bit(0, &primary->wrapped);
 199         DRM_DEBUG("done.\n");
 200 }
 201
 202 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
 203 {
 204         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
 205         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
 206         u32 head = dev_priv->primary->offset;
 207         DRM_DEBUG("\n");
 208
 209         sarea_priv->last_wrap++;
 210         DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
 211
 212         mga_flush_write_combine();
 213         MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
 214
 215         clear_bit(0, &primary->wrapped);
 216         DRM_DEBUG("done.\n");
 217 }
 218
 219 /* ================================================================
 220  * Freelist management
 221  */
 222
 223 #define MGA_BUFFER_USED         ~0
 224 #define MGA_BUFFER_FREE         0
 225
 226 #if MGA_FREELIST_DEBUG
 227 static void mga_freelist_print(struct drm_device * dev)
 228 {
 229         drm_mga_private_t *dev_priv = dev->dev_private;
 230         drm_mga_freelist_t *entry;
 231
 232         DRM_INFO("\n");
 233         DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
 234                  dev_priv->sarea_priv->last_dispatch,
 235                  (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
 236                                 dev_priv->primary->offset));
 237         DRM_INFO("current freelist:\n");
 238
 239         for (entry = dev_priv->head->next; entry; entry = entry->next) {
 240                 DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
 241                          entry, entry->buf->idx, entry->age.head,
 242                          entry->age.head - dev_priv->primary->offset);
 243         }
 244         DRM_INFO("\n");
 245 }
 246 #endif
 247
 248 static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
 249 {
 250         struct drm_device_dma *dma = dev->dma;
 251         struct drm_buf *buf;
 252         drm_mga_buf_priv_t *buf_priv;
 253         drm_mga_freelist_t *entry;
 254         int i;
 255         DRM_DEBUG("count=%d\n", dma->buf_count);
 256
 257         dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 258         if (dev_priv->head == NULL)
 259                 return -ENOMEM;
 260
 261         memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
 262         SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
 263
 264         for (i = 0; i < dma->buf_count; i++) {
 265                 buf = dma->buflist[i];
 266                 buf_priv = buf->dev_private;
 267
 268                 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 269                 if (entry == NULL)
 270                         return -ENOMEM;
 271
 272                 memset(entry, 0, sizeof(drm_mga_freelist_t));
 273
 274                 entry->next = dev_priv->head->next;
 275                 entry->prev = dev_priv->head;
 276                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 277                 entry->buf = buf;
 278
 279                 if (dev_priv->head->next != NULL)
 280                         dev_priv->head->next->prev = entry;
 281                 if (entry->next == NULL)
 282                         dev_priv->tail = entry;
 283
 284                 buf_priv->list_entry = entry;
 285                 buf_priv->discard = 0;
 286                 buf_priv->dispatched = 0;
 287
 288                 dev_priv->head->next = entry;
 289         }
 290
 291         return 0;
 292 }
 293
 294 static void mga_freelist_cleanup(struct drm_device * dev)
 295 {
 296         drm_mga_private_t *dev_priv = dev->dev_private;
 297         drm_mga_freelist_t *entry;
 298         drm_mga_freelist_t *next;
 299         DRM_DEBUG("\n");
 300
 301         entry = dev_priv->head;
 302         while (entry) {
 303                 next = entry->next;
 304                 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
 305                 entry = next;
 306         }
 307
 308         dev_priv->head = dev_priv->tail = NULL;
 309 }
 310
 311 #if 0
 312 /* FIXME: Still needed?
 313  */
 314 static void mga_freelist_reset(struct drm_device * dev)
 315 {
 316         drm_device_dma_t *dma = dev->dma;
 317         struct drm_buf *buf;
 318         drm_mga_buf_priv_t *buf_priv;
 319         int i;
 320
 321         for (i = 0; i < dma->buf_count; i++) {
 322                 buf = dma->buflist[i];
 323                 buf_priv = buf->dev_private;
 324                 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
 325         }
 326 }
 327 #endif
 328
 329 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
 330 {
 331         drm_mga_private_t *dev_priv = dev->dev_private;
 332         drm_mga_freelist_t *next;
 333         drm_mga_freelist_t *prev;
 334         drm_mga_freelist_t *tail = dev_priv->tail;
 335         u32 head, wrap;
 336         DRM_DEBUG("\n");
 337
 338         head = MGA_READ(MGA_PRIMADDRESS);
 339         wrap = dev_priv->sarea_priv->last_wrap;
 340
 341         DRM_DEBUG("   tail=0x%06lx %d\n",
 342                   tail->age.head ?
 343                   tail->age.head - dev_priv->primary->offset : 0,
 344                   tail->age.wrap);
 345         DRM_DEBUG("   head=0x%06lx %d\n",
 346                   head - dev_priv->primary->offset, wrap);
 347
 348         if (TEST_AGE(&tail->age, head, wrap)) {
 349                 prev = dev_priv->tail->prev;
 350                 next = dev_priv->tail;
 351                 prev->next = NULL;
 352                 next->prev = next->next = NULL;
 353                 dev_priv->tail = prev;
 354                 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
 355                 return next->buf;
 356         }
 357
 358         DRM_DEBUG("returning NULL!\n");
 359         return NULL;
 360 }
 361
 362 int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
 363 {
 364         drm_mga_private_t *dev_priv = dev->dev_private;
 365         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
 366         drm_mga_freelist_t *head, *entry, *prev;
 367
 368         DRM_DEBUG("age=0x%06lx wrap=%d\n",
 369                   buf_priv->list_entry->age.head -
 370                   dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
 371
 372         entry = buf_priv->list_entry;
 373         head = dev_priv->head;
 374
 375         if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
 376                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
 377                 prev = dev_priv->tail;
 378                 prev->next = entry;
 379                 entry->prev = prev;
 380                 entry->next = NULL;
 381         } else {
 382                 prev = head->next;
 383                 head->next = entry;
 384                 prev->prev = entry;
 385                 entry->prev = head;
 386                 entry->next = prev;
 387         }
 388
 389         return 0;
 390 }
 391
 392 /* ================================================================
 393  * DMA initialization, cleanup
 394  */
 395
 396 int mga_driver_load(struct drm_device *dev, unsigned long flags)
 397 {
 398         drm_mga_private_t *dev_priv;
 399
 400         dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
 401         if (!dev_priv)
 402                 return -ENOMEM;
 403
 404         dev->dev_private = (void *)dev_priv;
 405         memset(dev_priv, 0, sizeof(drm_mga_private_t));
 406
 407         dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
 408         dev_priv->chipset = flags;
 409
 410         dev_priv->mmio_base = drm_get_resource_start(dev, 1);
 411         dev_priv->mmio_size = drm_get_resource_len(dev, 1);
 412
 413         dev->counters += 3;
 414         dev->types[6] = _DRM_STAT_IRQ;
 415         dev->types[7] = _DRM_STAT_PRIMARY;
 416         dev->types[8] = _DRM_STAT_SECONDARY;
 417
 418         return 0;
 419 }
 420
 421 /**
 422  * Bootstrap the driver for AGP DMA.
 423  *
 424  * \todo
 425  * Investigate whether there is any benifit to storing the WARP microcode in
 426  * AGP memory.  If not, the microcode may as well always be put in PCI
 427  * memory.
 428  *
 429  * \todo
 430  * This routine needs to set dma_bs->agp_mode to the mode actually configured
 431  * in the hardware.  Looking just at the Linux AGP driver code, I don't see
 432  * an easy way to determine this.
 433  *
 434  * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
 435  */
 436 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
 437                                     drm_mga_dma_bootstrap_t * dma_bs)
 438 {
 439         drm_mga_private_t *const dev_priv =
 440                 (drm_mga_private_t *)dev->dev_private;
 441         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
 442         int err;
 443         unsigned offset;
 444         const unsigned secondary_size = dma_bs->secondary_bin_count
 445                 * dma_bs->secondary_bin_size;
 446         const unsigned agp_size = (dma_bs->agp_size << 20);
 447         struct drm_buf_desc req;
 448         struct drm_agp_mode mode;
 449         struct drm_agp_info info;
 450         struct drm_agp_buffer agp_req;
 451         struct drm_agp_binding bind_req;
 452
 453         /* Acquire AGP. */
 454         err = drm_agp_acquire(dev);
 455         if (err) {
 456                 DRM_ERROR("Unable to acquire AGP: %d\n", err);
 457                 return err;
 458         }
 459
 460         err = drm_agp_info(dev, &info);
 461         if (err) {
 462                 DRM_ERROR("Unable to get AGP info: %d\n", err);
 463                 return err;
 464         }
 465
 466         mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
 467         err = drm_agp_enable(dev, mode);
 468         if (err) {
 469                 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
 470                 return err;
 471         }
 472
 473         /* In addition to the usual AGP mode configuration, the G200 AGP cards
 474          * need to have the AGP mode "manually" set.
 475          */
 476
 477         if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
 478                 if (mode.mode & 0x02) {
 479                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
 480                 } else {
 481                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
 482                 }
 483         }
 484
 485         /* Allocate and bind AGP memory. */
 486         agp_req.size = agp_size;
 487         agp_req.type = 0;
 488         err = drm_agp_alloc(dev, &agp_req);
 489         if (err) {
 490                 dev_priv->agp_size = 0;
 491                 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
 492                           dma_bs->agp_size);
 493                 return err;
 494         }
 495
 496         dev_priv->agp_size = agp_size;
 497         dev_priv->agp_handle = agp_req.handle;
 498
 499         bind_req.handle = agp_req.handle;
 500         bind_req.offset = 0;
 501         err = drm_agp_bind( dev, &bind_req );
 502         if (err) {
 503                 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
 504                 return err;
 505         }
 506
 507         /* Make drm_addbufs happy by not trying to create a mapping for less
 508          * than a page.
 509          */
 510         if (warp_size < PAGE_SIZE)
 511                 warp_size = PAGE_SIZE;
 512
 513         offset = 0;
 514         err = drm_addmap(dev, offset, warp_size,
 515                          _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
 516         if (err) {
 517                 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
 518                 return err;
 519         }
 520
 521         offset += warp_size;
 522         err = drm_addmap(dev, offset, dma_bs->primary_size,
 523                          _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary);
 524         if (err) {
 525                 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
 526                 return err;
 527         }
 528
 529         offset += dma_bs->primary_size;
 530         err = drm_addmap(dev, offset, secondary_size,
 531                          _DRM_AGP, 0, & dev->agp_buffer_map);
 532         if (err) {
 533                 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
 534                 return err;
 535         }
 536
 537         (void)memset( &req, 0, sizeof(req) );
 538         req.count = dma_bs->secondary_bin_count;
 539         req.size = dma_bs->secondary_bin_size;
 540         req.flags = _DRM_AGP_BUFFER;
 541         req.agp_start = offset;
 542
 543         err = drm_addbufs_agp(dev, &req);
 544         if (err) {
 545                 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
 546                 return err;
 547         }
 548
 549 #ifdef __linux__
 550         {
 551                 struct drm_map_list *_entry;
 552                 unsigned long agp_token = 0;
 553
 554                 list_for_each_entry(_entry, &dev->maplist, head) {
 555                         if (_entry->map == dev->agp_buffer_map)
 556                                 agp_token = _entry->user_token;
 557                 }
 558                 if (!agp_token)
 559                         return -EFAULT;
 560
 561                 dev->agp_buffer_token = agp_token;
 562         }
 563 #endif
 564
 565         offset += secondary_size;
 566         err = drm_addmap(dev, offset, agp_size - offset,
 567                          _DRM_AGP, 0, & dev_priv->agp_textures);
 568         if (err) {
 569                 DRM_ERROR("Unable to map AGP texture region: %d\n", err);
 570                 return err;
 571         }
 572
 573         drm_core_ioremap(dev_priv->warp, dev);
 574         drm_core_ioremap(dev_priv->primary, dev);
 575         drm_core_ioremap(dev->agp_buffer_map, dev);
 576
 577         if (!dev_priv->warp->handle ||
 578             !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
 579                 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
 580                           dev_priv->warp->handle, dev_priv->primary->handle,
 581                           dev->agp_buffer_map->handle);
 582                 return -ENOMEM;
 583         }
 584
 585         dev_priv->dma_access = MGA_PAGPXFER;
 586         dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 587
 588         DRM_INFO("Initialized card for AGP DMA.\n");
 589         return 0;
 590 }
 591
 592 /**
 593  * Bootstrap the driver for PCI DMA.
 594  *
 595  * \todo
 596  * The algorithm for decreasing the size of the primary DMA buffer could be
 597  * better.  The size should be rounded up to the nearest page size, then
 598  * decrease the request size by a single page each pass through the loop.
 599  *
 600  * \todo
 601  * Determine whether the maximum address passed to drm_pci_alloc is correct.
 602  * The same goes for drm_addbufs_pci.
 603  *
 604  * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
 605  */
 606 static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
 607                                     drm_mga_dma_bootstrap_t * dma_bs)
 608 {
 609         drm_mga_private_t *const dev_priv =
 610                 (drm_mga_private_t *) dev->dev_private;
 611         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
 612         unsigned int primary_size;
 613         unsigned int bin_count;
 614         int err;
 615         struct drm_buf_desc req;
 616
 617
 618         if (dev->dma == NULL) {
 619                 DRM_ERROR("dev->dma is NULL\n");
 620                 return -EFAULT;
 621         }
 622
 623         /* Make drm_addbufs happy by not trying to create a mapping for less
 624          * than a page.
 625          */
 626         if (warp_size < PAGE_SIZE)
 627                 warp_size = PAGE_SIZE;
 628
 629         /* The proper alignment is 0x100 for this mapping */
 630         err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
 631                          _DRM_READ_ONLY, &dev_priv->warp);
 632         if (err != 0) {
 633                 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
 634                           err);
 635                 return err;
 636         }
 637
 638         /* Other than the bottom two bits being used to encode other
 639          * information, there don't appear to be any restrictions on the
 640          * alignment of the primary or secondary DMA buffers.
 641          */
 642
 643         for (primary_size = dma_bs->primary_size; primary_size != 0;
 644              primary_size >>= 1 ) {
 645                 /* The proper alignment for this mapping is 0x04 */
 646                 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
 647                                  _DRM_READ_ONLY, &dev_priv->primary);
 648                 if (!err)
 649                         break;
 650         }
 651
 652         if (err != 0) {
 653                 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
 654                 return -ENOMEM;
 655         }
 656
 657         if (dev_priv->primary->size != dma_bs->primary_size) {
 658                 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
 659                          dma_bs->primary_size,
 660                          (unsigned)dev_priv->primary->size);
 661                 dma_bs->primary_size = dev_priv->primary->size;
 662         }
 663
 664         for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
 665              bin_count-- ) {
 666                 (void)memset(&req, 0, sizeof(req));
 667                 req.count = bin_count;
 668                 req.size = dma_bs->secondary_bin_size;
 669
 670                 err = drm_addbufs_pci(dev, &req);
 671                 if (!err) {
 672                         break;
 673                 }
 674         }
 675
 676         if (bin_count == 0) {
 677                 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
 678                 return err;
 679         }
 680
 681         if (bin_count != dma_bs->secondary_bin_count) {
 682                 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
 683                          "to %u.\n", dma_bs->secondary_bin_count, bin_count);
 684
 685                 dma_bs->secondary_bin_count = bin_count;
 686         }
 687
 688         dev_priv->dma_access = 0;
 689         dev_priv->wagp_enable = 0;
 690
 691         dma_bs->agp_mode = 0;
 692
 693         DRM_INFO("Initialized card for PCI DMA.\n");
 694         return 0;
 695 }
 696
 697
 698 static int mga_do_dma_bootstrap(struct drm_device *dev,
 699                                 drm_mga_dma_bootstrap_t *dma_bs)
 700 {
 701         const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
 702         int err;
 703         drm_mga_private_t *const dev_priv =
 704                 (drm_mga_private_t *) dev->dev_private;
 705
 706
 707         dev_priv->used_new_dma_init = 1;
 708
 709         /* The first steps are the same for both PCI and AGP based DMA.  Map
 710          * the cards MMIO registers and map a status page.
 711          */
 712         err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
 713                          _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
 714         if (err) {
 715                 DRM_ERROR("Unable to map MMIO region: %d\n", err);
 716                 return err;
 717         }
 718
 719
 720         err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
 721                          _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
 722                          & dev_priv->status);
 723         if (err) {
 724                 DRM_ERROR("Unable to map status region: %d\n", err);
 725                 return err;
 726         }
 727
 728
 729         /* The DMA initialization procedure is slightly different for PCI and
 730          * AGP cards.  AGP cards just allocate a large block of AGP memory and
 731          * carve off portions of it for internal uses.  The remaining memory
 732          * is returned to user-mode to be used for AGP textures.
 733          */
 734
 735         if (is_agp) {
 736                 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
 737         }
 738
 739         /* If we attempted to initialize the card for AGP DMA but failed,
 740          * clean-up any mess that may have been created.
 741          */
 742
 743         if (err) {
 744                 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
 745         }
 746
 747
 748         /* Not only do we want to try and initialized PCI cards for PCI DMA,
 749          * but we also try to initialized AGP cards that could not be
 750          * initialized for AGP DMA.  This covers the case where we have an AGP
 751          * card in a system with an unsupported AGP chipset.  In that case the
 752          * card will be detected as AGP, but we won't be able to allocate any
 753          * AGP memory, etc.
 754          */
 755
 756         if (!is_agp || err) {
 757                 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
 758         }
 759
 760
 761         return err;
 762 }
 763
 764 int mga_dma_bootstrap(struct drm_device *dev, void *data,
 765                       struct drm_file *file_priv)
 766 {
 767         drm_mga_dma_bootstrap_t *bootstrap = data;
 768         int err;
 769         static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
 770         const drm_mga_private_t *const dev_priv =
 771                 (drm_mga_private_t *) dev->dev_private;
 772
 773
 774         err = mga_do_dma_bootstrap(dev, bootstrap);
 775         if (err) {
 776                 mga_do_cleanup_dma(dev, FULL_CLEANUP);
 777                 return err;
 778         }
 779
 780         if (dev_priv->agp_textures != NULL) {
 781                 bootstrap->texture_handle = dev_priv->agp_textures->offset;
 782                 bootstrap->texture_size = dev_priv->agp_textures->size;
 783         } else {
 784                 bootstrap->texture_handle = 0;
 785                 bootstrap->texture_size = 0;
 786         }
 787
 788         bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
 789
 790         return 0;
 791 }
 792
 793
 794 static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
 795 {
 796         drm_mga_private_t *dev_priv;
 797         int ret;
 798         DRM_DEBUG("\n");
 799
 800
 801         dev_priv = dev->dev_private;
 802
 803         if (init->sgram) {
 804                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
 805         } else {
 806                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
 807         }
 808         dev_priv->maccess = init->maccess;
 809
 810         dev_priv->fb_cpp = init->fb_cpp;
 811         dev_priv->front_offset = init->front_offset;
 812         dev_priv->front_pitch = init->front_pitch;
 813         dev_priv->back_offset = init->back_offset;
 814         dev_priv->back_pitch = init->back_pitch;
 815
 816         dev_priv->depth_cpp = init->depth_cpp;
 817         dev_priv->depth_offset = init->depth_offset;
 818         dev_priv->depth_pitch = init->depth_pitch;
 819
 820         /* FIXME: Need to support AGP textures...
 821          */
 822         dev_priv->texture_offset = init->texture_offset[0];
 823         dev_priv->texture_size = init->texture_size[0];
 824
 825         dev_priv->sarea = drm_getsarea(dev);
 826         if (!dev_priv->sarea) {
 827                 DRM_ERROR("failed to find sarea!\n");
 828                 return -EINVAL;
 829         }
 830
 831         if (!dev_priv->used_new_dma_init) {
 832
 833                 dev_priv->dma_access = MGA_PAGPXFER;
 834                 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
 835
 836                 dev_priv->status = drm_core_findmap(dev, init->status_offset);
 837                 if (!dev_priv->status) {
 838                         DRM_ERROR("failed to find status page!\n");
 839                         return -EINVAL;
 840                 }
 841                 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
 842                 if (!dev_priv->mmio) {
 843                         DRM_ERROR("failed to find mmio region!\n");
 844                         return -EINVAL;
 845                 }
 846                 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
 847                 if (!dev_priv->warp) {
 848                         DRM_ERROR("failed to find warp microcode region!\n");
 849                         return -EINVAL;
 850                 }
 851                 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
 852                 if (!dev_priv->primary) {
 853                         DRM_ERROR("failed to find primary dma region!\n");
 854                         return -EINVAL;
 855                 }
 856                 dev->agp_buffer_token = init->buffers_offset;
 857                 dev->agp_buffer_map =
 858                         drm_core_findmap(dev, init->buffers_offset);
 859                 if (!dev->agp_buffer_map) {
 860                         DRM_ERROR("failed to find dma buffer region!\n");
 861                         return -EINVAL;
 862                 }
 863
 864                 drm_core_ioremap(dev_priv->warp, dev);
 865                 drm_core_ioremap(dev_priv->primary, dev);
 866                 drm_core_ioremap(dev->agp_buffer_map, dev);
 867         }
 868
 869         dev_priv->sarea_priv =
 870             (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
 871                                  init->sarea_priv_offset);
 872
 873         if (!dev_priv->warp->handle ||
 874             !dev_priv->primary->handle ||
 875             ((dev_priv->dma_access != 0) &&
 876              ((dev->agp_buffer_map == NULL) ||
 877               (dev->agp_buffer_map->handle == NULL)))) {
 878                 DRM_ERROR("failed to ioremap agp regions!\n");
 879                 return -ENOMEM;
 880         }
 881
 882         ret = mga_warp_install_microcode(dev_priv);
 883         if (ret != 0) {
 884                 DRM_ERROR("failed to install WARP ucode: %d!\n", ret);
 885                 return ret;
 886         }
 887
 888         ret = mga_warp_init(dev_priv);
 889         if (ret != 0) {
 890                 DRM_ERROR("failed to init WARP engine: %d!\n", ret);
 891                 return ret;
 892         }
 893
 894         dev_priv->prim.status = (u32 *) dev_priv->status->handle;
 895
 896         mga_do_wait_for_idle(dev_priv);
 897
 898         /* Init the primary DMA registers.
 899          */
 900         MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
 901
 902         dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
 903         dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
 904                               + dev_priv->primary->size);
 905         dev_priv->prim.size = dev_priv->primary->size;
 906
 907         dev_priv->prim.tail = 0;
 908         dev_priv->prim.space = dev_priv->prim.size;
 909         dev_priv->prim.wrapped = 0;
 910
 911         dev_priv->prim.last_flush = 0;
 912         dev_priv->prim.last_wrap = 0;
 913
 914         dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
 915
 916         dev_priv->prim.status[0] = dev_priv->primary->offset;
 917         dev_priv->prim.status[1] = 0;
 918
 919         dev_priv->sarea_priv->last_wrap = 0;
 920         dev_priv->sarea_priv->last_frame.head = 0;
 921         dev_priv->sarea_priv->last_frame.wrap = 0;
 922
 923         if (mga_freelist_init(dev, dev_priv) < 0) {
 924                 DRM_ERROR("could not initialize freelist\n");
 925                 return -ENOMEM;
 926         }
 927
 928         return 0;
 929 }
 930
 931 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
 932 {
 933         int err = 0;
 934         DRM_DEBUG("\n");
 935
 936         /* Make sure interrupts are disabled here because the uninstall ioctl
 937          * may not have been called from userspace and after dev_private
 938          * is freed, it's too late.
 939          */
 940         if (dev->irq_enabled)
 941                 drm_irq_uninstall(dev);
 942
 943         if (dev->dev_private) {
 944                 drm_mga_private_t *dev_priv = dev->dev_private;
 945
 946                 if ((dev_priv->warp != NULL)
 947                     && (dev_priv->warp->type != _DRM_CONSISTENT))
 948                         drm_core_ioremapfree(dev_priv->warp, dev);
 949
 950                 if ((dev_priv->primary != NULL)
 951                     && (dev_priv->primary->type != _DRM_CONSISTENT))
 952                         drm_core_ioremapfree(dev_priv->primary, dev);
 953
 954                 if (dev->agp_buffer_map != NULL)
 955                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
 956
 957                 if (dev_priv->used_new_dma_init) {
 958                         if (dev_priv->agp_handle != 0) {
 959                                 struct drm_agp_binding unbind_req;
 960                                 struct drm_agp_buffer free_req;
 961
 962                                 unbind_req.handle = dev_priv->agp_handle;
 963                                 drm_agp_unbind(dev, &unbind_req);
 964
 965                                 free_req.handle = dev_priv->agp_handle;
 966                                 drm_agp_free(dev, &free_req);
 967
 968                                 dev_priv->agp_textures = NULL;
 969                                 dev_priv->agp_size = 0;
 970                                 dev_priv->agp_handle = 0;
 971                         }
 972
 973                         if ((dev->agp != NULL) && dev->agp->acquired) {
 974                                 err = drm_agp_release(dev);
 975                         }
 976                 }
 977
 978                 dev_priv->warp = NULL;
 979                 dev_priv->primary = NULL;
 980                 dev_priv->sarea = NULL;
 981                 dev_priv->sarea_priv = NULL;
 982                 dev->agp_buffer_map = NULL;
 983
 984                 if (full_cleanup) {
 985                         dev_priv->mmio = NULL;
 986                         dev_priv->status = NULL;
 987                         dev_priv->used_new_dma_init = 0;
 988                 }
 989
 990                 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
 991                 dev_priv->warp_pipe = 0;
 992                 memset(dev_priv->warp_pipe_phys, 0,
 993                        sizeof(dev_priv->warp_pipe_phys));
 994
 995                 if (dev_priv->head != NULL) {
 996                         mga_freelist_cleanup(dev);
 997                 }
 998         }
 999
1000         return err;
1001 }
1002
1003 int mga_dma_init(struct drm_device *dev, void *data,
1004                  struct drm_file *file_priv)
1005 {
1006         drm_mga_init_t *init = data;
1007         int err;
1008
1009         LOCK_TEST_WITH_RETURN(dev, file_priv);
1010
1011         switch (init->func) {
1012         case MGA_INIT_DMA:
1013                 err = mga_do_init_dma(dev, init);
1014                 if (err) {
1015                         (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1016                 }
1017                 return err;
1018         case MGA_CLEANUP_DMA:
1019                 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1020         }
1021
1022         return -EINVAL;
1023 }
1024
1025 /* ================================================================
1026  * Primary DMA stream management
1027  */
1028
1029 int mga_dma_flush(struct drm_device *dev, void *data,
1030                   struct drm_file *file_priv)
1031 {
1032         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1033         struct drm_lock *lock = data;
1034
1035         LOCK_TEST_WITH_RETURN(dev, file_priv);
1036
1037         DRM_DEBUG("%s%s%s\n",
1038                   (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1039                   (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1040                   (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1041
1042         WRAP_WAIT_WITH_RETURN(dev_priv);
1043
1044         if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1045                 mga_do_dma_flush(dev_priv);
1046         }
1047
1048         if (lock->flags & _DRM_LOCK_QUIESCENT) {
1049 #if MGA_DMA_DEBUG
1050                 int ret = mga_do_wait_for_idle(dev_priv);
1051                 if (ret < 0)
1052                         DRM_INFO("-EBUSY\n");
1053                 return ret;
1054 #else
1055                 return mga_do_wait_for_idle(dev_priv);
1056 #endif
1057         } else {
1058                 return 0;
1059         }
1060 }
1061
1062 int mga_dma_reset(struct drm_device *dev, void *data,
1063                   struct drm_file *file_priv)
1064 {
1065         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1066
1067         LOCK_TEST_WITH_RETURN(dev, file_priv);
1068
1069         return mga_do_dma_reset(dev_priv);
1070 }
1071
1072 /* ================================================================
1073  * DMA buffer management
1074  */
1075
1076 static int mga_dma_get_buffers(struct drm_device * dev,
1077                                struct drm_file *file_priv, struct drm_dma * d)
1078 {
1079         struct drm_buf *buf;
1080         int i;
1081
1082         for (i = d->granted_count; i < d->request_count; i++) {
1083                 buf = mga_freelist_get(dev);
1084                 if (!buf)
1085                         return -EAGAIN;
1086
1087                 buf->file_priv = file_priv;
1088
1089                 if (DRM_COPY_TO_USER(&d->request_indices[i],
1090                                      &buf->idx, sizeof(buf->idx)))
1091                         return -EFAULT;
1092                 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1093                                      &buf->total, sizeof(buf->total)))
1094                         return -EFAULT;
1095
1096                 d->granted_count++;
1097         }
1098         return 0;
1099 }
1100
1101 int mga_dma_buffers(struct drm_device *dev, void *data,
1102                     struct drm_file *file_priv)
1103 {
1104         struct drm_device_dma *dma = dev->dma;
1105         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1106         struct drm_dma *d = data;
1107         int ret = 0;
1108
1109         LOCK_TEST_WITH_RETURN(dev, file_priv);
1110
1111         /* Please don't send us buffers.
1112          */
1113         if (d->send_count != 0) {
1114                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1115                           DRM_CURRENTPID, d->send_count);
1116                 return -EINVAL;
1117         }
1118
1119         /* We'll send you buffers.
1120          */
1121         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1122                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1123                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1124                 return -EINVAL;
1125         }
1126
1127         WRAP_TEST_WITH_RETURN(dev_priv);
1128
1129         d->granted_count = 0;
1130
1131         if (d->request_count) {
1132                 ret = mga_dma_get_buffers(dev, file_priv, d);
1133         }
1134
1135         return ret;
1136 }
1137
1138 /**
1139  * Called just before the module is unloaded.
1140  */
1141 int mga_driver_unload(struct drm_device * dev)
1142 {
1143         drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1144         dev->dev_private = NULL;
1145
1146         return 0;
1147 }
1148
1149 /**
1150  * Called when the last opener of the device is closed.
1151  */
1152 void mga_driver_lastclose(struct drm_device * dev)
1153 {
1154         mga_do_cleanup_dma(dev, FULL_CLEANUP);
1155 }
1156
1157 int mga_driver_dma_quiescent(struct drm_device * dev)
1158 {
1159         drm_mga_private_t *dev_priv = dev->dev_private;
1160         return mga_do_wait_for_idle(dev_priv);
1161 }