1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 /* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
30 * DMA support for MGA G200 / G400.
32 * \author Rickard E. (Rik) Faith <faith@valinux.com>
33 * \author Jeff Hartmann <jhartmann@valinux.com>
34 * \author Keith Whitwell <keith@tungstengraphics.com>
35 * \author Gareth Hughes <gareth@valinux.com>
40 #include "drm_sarea.h"
44 #define MGA_DEFAULT_USEC_TIMEOUT 10000
45 #define MGA_FREELIST_DEBUG 0
47 #define MINIMAL_CLEANUP 0
48 #define FULL_CLEANUP 1
49 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
51 /* ================================================================
55 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
61 for (i = 0; i < dev_priv->usec_timeout; i++) {
62 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
63 if (status == MGA_ENDPRDMASTS) {
64 MGA_WRITE8(MGA_CRTC_INDEX, 0);
71 DRM_ERROR("failed!\n");
72 DRM_INFO(" status=0x%08x\n", status);
77 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
79 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
80 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
84 /* The primary DMA stream should look like new right about now.
87 primary->space = primary->size;
88 primary->last_flush = 0;
90 sarea_priv->last_wrap = 0;
92 /* FIXME: Reset counters, buffer ages etc...
95 /* FIXME: What else do we need to reinitialize? WARP stuff?
101 /* ================================================================
105 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
107 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
114 /* We need to wait so that we can do an safe flush */
115 for (i = 0; i < dev_priv->usec_timeout; i++) {
116 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
117 if (status == MGA_ENDPRDMASTS)
122 if (primary->tail == primary->last_flush) {
123 DRM_DEBUG(" bailing out...\n");
127 tail = primary->tail + dev_priv->primary->offset;
129 /* We need to pad the stream between flushes, as the card
130 * actually (partially?) reads the first of these commands.
131 * See page 4-16 in the G400 manual, middle of the page or so.
135 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
136 MGA_DMAPAD, 0x00000000,
137 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
141 primary->last_flush = primary->tail;
143 head = MGA_READ(MGA_PRIMADDRESS);
146 primary->space = primary->size - primary->tail;
148 primary->space = head - tail;
151 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
152 DRM_DEBUG(" tail = 0x%06lx\n", tail - dev_priv->primary->offset);
153 DRM_DEBUG(" space = 0x%06x\n", primary->space);
155 mga_flush_write_combine();
156 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
158 DRM_DEBUG("done.\n");
161 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
163 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
170 DMA_BLOCK(MGA_DMAPAD, 0x00000000,
171 MGA_DMAPAD, 0x00000000,
172 MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
176 tail = primary->tail + dev_priv->primary->offset;
179 primary->last_flush = 0;
180 primary->last_wrap++;
182 head = MGA_READ(MGA_PRIMADDRESS);
184 if (head == dev_priv->primary->offset) {
185 primary->space = primary->size;
187 primary->space = head - dev_priv->primary->offset;
190 DRM_DEBUG(" head = 0x%06lx\n", head - dev_priv->primary->offset);
191 DRM_DEBUG(" tail = 0x%06x\n", primary->tail);
192 DRM_DEBUG(" wrap = %d\n", primary->last_wrap);
193 DRM_DEBUG(" space = 0x%06x\n", primary->space);
195 mga_flush_write_combine();
196 MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
198 set_bit(0, &primary->wrapped);
199 DRM_DEBUG("done.\n");
202 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
204 drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205 drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206 u32 head = dev_priv->primary->offset;
209 sarea_priv->last_wrap++;
210 DRM_DEBUG(" wrap = %d\n", sarea_priv->last_wrap);
212 mga_flush_write_combine();
213 MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
215 clear_bit(0, &primary->wrapped);
216 DRM_DEBUG("done.\n");
219 /* ================================================================
220 * Freelist management
223 #define MGA_BUFFER_USED ~0
224 #define MGA_BUFFER_FREE 0
226 #if MGA_FREELIST_DEBUG
227 static void mga_freelist_print(struct drm_device * dev)
229 drm_mga_private_t *dev_priv = dev->dev_private;
230 drm_mga_freelist_t *entry;
233 DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
234 dev_priv->sarea_priv->last_dispatch,
235 (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
236 dev_priv->primary->offset));
237 DRM_INFO("current freelist:\n");
239 for (entry = dev_priv->head->next; entry; entry = entry->next) {
240 DRM_INFO(" %p idx=%2d age=0x%x 0x%06lx\n",
241 entry, entry->buf->idx, entry->age.head,
242 entry->age.head - dev_priv->primary->offset);
248 static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
250 struct drm_device_dma *dma = dev->dma;
252 drm_mga_buf_priv_t *buf_priv;
253 drm_mga_freelist_t *entry;
255 DRM_DEBUG("count=%d\n", dma->buf_count);
257 dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
258 if (dev_priv->head == NULL)
261 memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
262 SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
264 for (i = 0; i < dma->buf_count; i++) {
265 buf = dma->buflist[i];
266 buf_priv = buf->dev_private;
268 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
272 memset(entry, 0, sizeof(drm_mga_freelist_t));
274 entry->next = dev_priv->head->next;
275 entry->prev = dev_priv->head;
276 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
279 if (dev_priv->head->next != NULL)
280 dev_priv->head->next->prev = entry;
281 if (entry->next == NULL)
282 dev_priv->tail = entry;
284 buf_priv->list_entry = entry;
285 buf_priv->discard = 0;
286 buf_priv->dispatched = 0;
288 dev_priv->head->next = entry;
294 static void mga_freelist_cleanup(struct drm_device * dev)
296 drm_mga_private_t *dev_priv = dev->dev_private;
297 drm_mga_freelist_t *entry;
298 drm_mga_freelist_t *next;
301 entry = dev_priv->head;
304 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
308 dev_priv->head = dev_priv->tail = NULL;
312 /* FIXME: Still needed?
314 static void mga_freelist_reset(struct drm_device * dev)
316 drm_device_dma_t *dma = dev->dma;
318 drm_mga_buf_priv_t *buf_priv;
321 for (i = 0; i < dma->buf_count; i++) {
322 buf = dma->buflist[i];
323 buf_priv = buf->dev_private;
324 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
329 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
331 drm_mga_private_t *dev_priv = dev->dev_private;
332 drm_mga_freelist_t *next;
333 drm_mga_freelist_t *prev;
334 drm_mga_freelist_t *tail = dev_priv->tail;
338 head = MGA_READ(MGA_PRIMADDRESS);
339 wrap = dev_priv->sarea_priv->last_wrap;
341 DRM_DEBUG(" tail=0x%06lx %d\n",
343 tail->age.head - dev_priv->primary->offset : 0,
345 DRM_DEBUG(" head=0x%06lx %d\n",
346 head - dev_priv->primary->offset, wrap);
348 if (TEST_AGE(&tail->age, head, wrap)) {
349 prev = dev_priv->tail->prev;
350 next = dev_priv->tail;
352 next->prev = next->next = NULL;
353 dev_priv->tail = prev;
354 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
358 DRM_DEBUG("returning NULL!\n");
362 int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
364 drm_mga_private_t *dev_priv = dev->dev_private;
365 drm_mga_buf_priv_t *buf_priv = buf->dev_private;
366 drm_mga_freelist_t *head, *entry, *prev;
368 DRM_DEBUG("age=0x%06lx wrap=%d\n",
369 buf_priv->list_entry->age.head -
370 dev_priv->primary->offset, buf_priv->list_entry->age.wrap);
372 entry = buf_priv->list_entry;
373 head = dev_priv->head;
375 if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
376 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
377 prev = dev_priv->tail;
392 /* ================================================================
393 * DMA initialization, cleanup
396 int mga_driver_load(struct drm_device *dev, unsigned long flags)
398 drm_mga_private_t *dev_priv;
401 dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
405 dev->dev_private = (void *)dev_priv;
406 memset(dev_priv, 0, sizeof(drm_mga_private_t));
408 dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
409 dev_priv->chipset = flags;
411 dev_priv->mmio_base = drm_get_resource_start(dev, 1);
412 dev_priv->mmio_size = drm_get_resource_len(dev, 1);
415 dev->types[6] = _DRM_STAT_IRQ;
416 dev->types[7] = _DRM_STAT_PRIMARY;
417 dev->types[8] = _DRM_STAT_SECONDARY;
419 ret = drm_vblank_init(dev, 1);
422 (void) mga_driver_unload(dev);
430 * Bootstrap the driver for AGP DMA.
433 * Investigate whether there is any benifit to storing the WARP microcode in
434 * AGP memory. If not, the microcode may as well always be put in PCI
438 * This routine needs to set dma_bs->agp_mode to the mode actually configured
439 * in the hardware. Looking just at the Linux AGP driver code, I don't see
440 * an easy way to determine this.
442 * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
444 static int mga_do_agp_dma_bootstrap(struct drm_device *dev,
445 drm_mga_dma_bootstrap_t * dma_bs)
447 drm_mga_private_t *const dev_priv =
448 (drm_mga_private_t *)dev->dev_private;
449 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
452 const unsigned secondary_size = dma_bs->secondary_bin_count
453 * dma_bs->secondary_bin_size;
454 const unsigned agp_size = (dma_bs->agp_size << 20);
455 struct drm_buf_desc req;
456 struct drm_agp_mode mode;
457 struct drm_agp_info info;
458 struct drm_agp_buffer agp_req;
459 struct drm_agp_binding bind_req;
462 err = drm_agp_acquire(dev);
464 DRM_ERROR("Unable to acquire AGP: %d\n", err);
468 err = drm_agp_info(dev, &info);
470 DRM_ERROR("Unable to get AGP info: %d\n", err);
474 mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
475 err = drm_agp_enable(dev, mode);
477 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
481 /* In addition to the usual AGP mode configuration, the G200 AGP cards
482 * need to have the AGP mode "manually" set.
485 if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
486 if (mode.mode & 0x02) {
487 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
489 MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
493 /* Allocate and bind AGP memory. */
494 agp_req.size = agp_size;
496 err = drm_agp_alloc(dev, &agp_req);
498 dev_priv->agp_size = 0;
499 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
504 dev_priv->agp_size = agp_size;
505 dev_priv->agp_handle = agp_req.handle;
507 bind_req.handle = agp_req.handle;
509 err = drm_agp_bind( dev, &bind_req );
511 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
515 /* Make drm_addbufs happy by not trying to create a mapping for less
518 if (warp_size < PAGE_SIZE)
519 warp_size = PAGE_SIZE;
522 err = drm_addmap(dev, offset, warp_size,
523 _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
525 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
530 err = drm_addmap(dev, offset, dma_bs->primary_size,
531 _DRM_AGP, _DRM_READ_ONLY, & dev_priv->primary);
533 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
537 offset += dma_bs->primary_size;
538 err = drm_addmap(dev, offset, secondary_size,
539 _DRM_AGP, 0, & dev->agp_buffer_map);
541 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
545 (void)memset( &req, 0, sizeof(req) );
546 req.count = dma_bs->secondary_bin_count;
547 req.size = dma_bs->secondary_bin_size;
548 req.flags = _DRM_AGP_BUFFER;
549 req.agp_start = offset;
551 err = drm_addbufs_agp(dev, &req);
553 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
559 struct drm_map_list *_entry;
560 unsigned long agp_token = 0;
562 list_for_each_entry(_entry, &dev->maplist, head) {
563 if (_entry->map == dev->agp_buffer_map)
564 agp_token = _entry->user_token;
569 dev->agp_buffer_token = agp_token;
573 offset += secondary_size;
574 err = drm_addmap(dev, offset, agp_size - offset,
575 _DRM_AGP, 0, & dev_priv->agp_textures);
577 DRM_ERROR("Unable to map AGP texture region: %d\n", err);
581 drm_core_ioremap(dev_priv->warp, dev);
582 drm_core_ioremap(dev_priv->primary, dev);
583 drm_core_ioremap(dev->agp_buffer_map, dev);
585 if (!dev_priv->warp->handle ||
586 !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
587 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
588 dev_priv->warp->handle, dev_priv->primary->handle,
589 dev->agp_buffer_map->handle);
593 dev_priv->dma_access = MGA_PAGPXFER;
594 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
596 DRM_INFO("Initialized card for AGP DMA.\n");
601 * Bootstrap the driver for PCI DMA.
604 * The algorithm for decreasing the size of the primary DMA buffer could be
605 * better. The size should be rounded up to the nearest page size, then
606 * decrease the request size by a single page each pass through the loop.
609 * Determine whether the maximum address passed to drm_pci_alloc is correct.
610 * The same goes for drm_addbufs_pci.
612 * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
614 static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
615 drm_mga_dma_bootstrap_t * dma_bs)
617 drm_mga_private_t *const dev_priv =
618 (drm_mga_private_t *) dev->dev_private;
619 unsigned int warp_size = mga_warp_microcode_size(dev_priv);
620 unsigned int primary_size;
621 unsigned int bin_count;
623 struct drm_buf_desc req;
626 if (dev->dma == NULL) {
627 DRM_ERROR("dev->dma is NULL\n");
631 /* Make drm_addbufs happy by not trying to create a mapping for less
634 if (warp_size < PAGE_SIZE)
635 warp_size = PAGE_SIZE;
637 /* The proper alignment is 0x100 for this mapping */
638 err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
639 _DRM_READ_ONLY, &dev_priv->warp);
641 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
646 /* Other than the bottom two bits being used to encode other
647 * information, there don't appear to be any restrictions on the
648 * alignment of the primary or secondary DMA buffers.
651 for (primary_size = dma_bs->primary_size; primary_size != 0;
652 primary_size >>= 1 ) {
653 /* The proper alignment for this mapping is 0x04 */
654 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
655 _DRM_READ_ONLY, &dev_priv->primary);
661 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
665 if (dev_priv->primary->size != dma_bs->primary_size) {
666 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
667 dma_bs->primary_size,
668 (unsigned)dev_priv->primary->size);
669 dma_bs->primary_size = dev_priv->primary->size;
672 for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
674 (void)memset(&req, 0, sizeof(req));
675 req.count = bin_count;
676 req.size = dma_bs->secondary_bin_size;
678 err = drm_addbufs_pci(dev, &req);
684 if (bin_count == 0) {
685 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
689 if (bin_count != dma_bs->secondary_bin_count) {
690 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
691 "to %u.\n", dma_bs->secondary_bin_count, bin_count);
693 dma_bs->secondary_bin_count = bin_count;
696 dev_priv->dma_access = 0;
697 dev_priv->wagp_enable = 0;
699 dma_bs->agp_mode = 0;
701 DRM_INFO("Initialized card for PCI DMA.\n");
706 static int mga_do_dma_bootstrap(struct drm_device *dev,
707 drm_mga_dma_bootstrap_t *dma_bs)
709 const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
711 drm_mga_private_t *const dev_priv =
712 (drm_mga_private_t *) dev->dev_private;
715 dev_priv->used_new_dma_init = 1;
717 /* The first steps are the same for both PCI and AGP based DMA. Map
718 * the cards MMIO registers and map a status page.
720 err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
721 _DRM_REGISTERS, _DRM_READ_ONLY, & dev_priv->mmio);
723 DRM_ERROR("Unable to map MMIO region: %d\n", err);
728 err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
729 _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
732 DRM_ERROR("Unable to map status region: %d\n", err);
737 /* The DMA initialization procedure is slightly different for PCI and
738 * AGP cards. AGP cards just allocate a large block of AGP memory and
739 * carve off portions of it for internal uses. The remaining memory
740 * is returned to user-mode to be used for AGP textures.
744 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
747 /* If we attempted to initialize the card for AGP DMA but failed,
748 * clean-up any mess that may have been created.
752 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
756 /* Not only do we want to try and initialized PCI cards for PCI DMA,
757 * but we also try to initialized AGP cards that could not be
758 * initialized for AGP DMA. This covers the case where we have an AGP
759 * card in a system with an unsupported AGP chipset. In that case the
760 * card will be detected as AGP, but we won't be able to allocate any
764 if (!is_agp || err) {
765 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
772 int mga_dma_bootstrap(struct drm_device *dev, void *data,
773 struct drm_file *file_priv)
775 drm_mga_dma_bootstrap_t *bootstrap = data;
777 static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
778 const drm_mga_private_t *const dev_priv =
779 (drm_mga_private_t *) dev->dev_private;
782 err = mga_do_dma_bootstrap(dev, bootstrap);
784 mga_do_cleanup_dma(dev, FULL_CLEANUP);
788 if (dev_priv->agp_textures != NULL) {
789 bootstrap->texture_handle = dev_priv->agp_textures->offset;
790 bootstrap->texture_size = dev_priv->agp_textures->size;
792 bootstrap->texture_handle = 0;
793 bootstrap->texture_size = 0;
796 bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
802 static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
804 drm_mga_private_t *dev_priv;
809 dev_priv = dev->dev_private;
812 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
814 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
816 dev_priv->maccess = init->maccess;
818 dev_priv->fb_cpp = init->fb_cpp;
819 dev_priv->front_offset = init->front_offset;
820 dev_priv->front_pitch = init->front_pitch;
821 dev_priv->back_offset = init->back_offset;
822 dev_priv->back_pitch = init->back_pitch;
824 dev_priv->depth_cpp = init->depth_cpp;
825 dev_priv->depth_offset = init->depth_offset;
826 dev_priv->depth_pitch = init->depth_pitch;
828 /* FIXME: Need to support AGP textures...
830 dev_priv->texture_offset = init->texture_offset[0];
831 dev_priv->texture_size = init->texture_size[0];
833 dev_priv->sarea = drm_getsarea(dev);
834 if (!dev_priv->sarea) {
835 DRM_ERROR("failed to find sarea!\n");
839 if (!dev_priv->used_new_dma_init) {
841 dev_priv->dma_access = MGA_PAGPXFER;
842 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
844 dev_priv->status = drm_core_findmap(dev, init->status_offset);
845 if (!dev_priv->status) {
846 DRM_ERROR("failed to find status page!\n");
849 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
850 if (!dev_priv->mmio) {
851 DRM_ERROR("failed to find mmio region!\n");
854 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
855 if (!dev_priv->warp) {
856 DRM_ERROR("failed to find warp microcode region!\n");
859 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
860 if (!dev_priv->primary) {
861 DRM_ERROR("failed to find primary dma region!\n");
864 dev->agp_buffer_token = init->buffers_offset;
865 dev->agp_buffer_map =
866 drm_core_findmap(dev, init->buffers_offset);
867 if (!dev->agp_buffer_map) {
868 DRM_ERROR("failed to find dma buffer region!\n");
872 drm_core_ioremap(dev_priv->warp, dev);
873 drm_core_ioremap(dev_priv->primary, dev);
874 drm_core_ioremap(dev->agp_buffer_map, dev);
877 dev_priv->sarea_priv =
878 (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
879 init->sarea_priv_offset);
881 if (!dev_priv->warp->handle ||
882 !dev_priv->primary->handle ||
883 ((dev_priv->dma_access != 0) &&
884 ((dev->agp_buffer_map == NULL) ||
885 (dev->agp_buffer_map->handle == NULL)))) {
886 DRM_ERROR("failed to ioremap agp regions!\n");
890 ret = mga_warp_install_microcode(dev_priv);
892 DRM_ERROR("failed to install WARP ucode: %d!\n", ret);
896 ret = mga_warp_init(dev_priv);
898 DRM_ERROR("failed to init WARP engine: %d!\n", ret);
902 dev_priv->prim.status = (u32 *) dev_priv->status->handle;
904 mga_do_wait_for_idle(dev_priv);
906 /* Init the primary DMA registers.
908 MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
910 dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
911 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
912 + dev_priv->primary->size);
913 dev_priv->prim.size = dev_priv->primary->size;
915 dev_priv->prim.tail = 0;
916 dev_priv->prim.space = dev_priv->prim.size;
917 dev_priv->prim.wrapped = 0;
919 dev_priv->prim.last_flush = 0;
920 dev_priv->prim.last_wrap = 0;
922 dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
924 dev_priv->prim.status[0] = dev_priv->primary->offset;
925 dev_priv->prim.status[1] = 0;
927 dev_priv->sarea_priv->last_wrap = 0;
928 dev_priv->sarea_priv->last_frame.head = 0;
929 dev_priv->sarea_priv->last_frame.wrap = 0;
931 if (mga_freelist_init(dev, dev_priv) < 0) {
932 DRM_ERROR("could not initialize freelist\n");
939 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
944 /* Make sure interrupts are disabled here because the uninstall ioctl
945 * may not have been called from userspace and after dev_private
946 * is freed, it's too late.
948 if (dev->irq_enabled)
949 drm_irq_uninstall(dev);
951 if (dev->dev_private) {
952 drm_mga_private_t *dev_priv = dev->dev_private;
954 if ((dev_priv->warp != NULL)
955 && (dev_priv->warp->type != _DRM_CONSISTENT))
956 drm_core_ioremapfree(dev_priv->warp, dev);
958 if ((dev_priv->primary != NULL)
959 && (dev_priv->primary->type != _DRM_CONSISTENT))
960 drm_core_ioremapfree(dev_priv->primary, dev);
962 if (dev->agp_buffer_map != NULL)
963 drm_core_ioremapfree(dev->agp_buffer_map, dev);
965 if (dev_priv->used_new_dma_init) {
966 if (dev_priv->agp_handle != 0) {
967 struct drm_agp_binding unbind_req;
968 struct drm_agp_buffer free_req;
970 unbind_req.handle = dev_priv->agp_handle;
971 drm_agp_unbind(dev, &unbind_req);
973 free_req.handle = dev_priv->agp_handle;
974 drm_agp_free(dev, &free_req);
976 dev_priv->agp_textures = NULL;
977 dev_priv->agp_size = 0;
978 dev_priv->agp_handle = 0;
981 if ((dev->agp != NULL) && dev->agp->acquired) {
982 err = drm_agp_release(dev);
986 dev_priv->warp = NULL;
987 dev_priv->primary = NULL;
988 dev_priv->sarea = NULL;
989 dev_priv->sarea_priv = NULL;
990 dev->agp_buffer_map = NULL;
993 dev_priv->mmio = NULL;
994 dev_priv->status = NULL;
995 dev_priv->used_new_dma_init = 0;
998 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
999 dev_priv->warp_pipe = 0;
1000 memset(dev_priv->warp_pipe_phys, 0,
1001 sizeof(dev_priv->warp_pipe_phys));
1003 if (dev_priv->head != NULL) {
1004 mga_freelist_cleanup(dev);
1011 int mga_dma_init(struct drm_device *dev, void *data,
1012 struct drm_file *file_priv)
1014 drm_mga_init_t *init = data;
1017 LOCK_TEST_WITH_RETURN(dev, file_priv);
1019 switch (init->func) {
1021 err = mga_do_init_dma(dev, init);
1023 (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1026 case MGA_CLEANUP_DMA:
1027 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1033 /* ================================================================
1034 * Primary DMA stream management
1037 int mga_dma_flush(struct drm_device *dev, void *data,
1038 struct drm_file *file_priv)
1040 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1041 struct drm_lock *lock = data;
1043 LOCK_TEST_WITH_RETURN(dev, file_priv);
1045 DRM_DEBUG("%s%s%s\n",
1046 (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1047 (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1048 (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1050 WRAP_WAIT_WITH_RETURN(dev_priv);
1052 if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1053 mga_do_dma_flush(dev_priv);
1056 if (lock->flags & _DRM_LOCK_QUIESCENT) {
1058 int ret = mga_do_wait_for_idle(dev_priv);
1060 DRM_INFO("-EBUSY\n");
1063 return mga_do_wait_for_idle(dev_priv);
1070 int mga_dma_reset(struct drm_device *dev, void *data,
1071 struct drm_file *file_priv)
1073 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1075 LOCK_TEST_WITH_RETURN(dev, file_priv);
1077 return mga_do_dma_reset(dev_priv);
1080 /* ================================================================
1081 * DMA buffer management
1084 static int mga_dma_get_buffers(struct drm_device * dev,
1085 struct drm_file *file_priv, struct drm_dma * d)
1087 struct drm_buf *buf;
1090 for (i = d->granted_count; i < d->request_count; i++) {
1091 buf = mga_freelist_get(dev);
1095 buf->file_priv = file_priv;
1097 if (DRM_COPY_TO_USER(&d->request_indices[i],
1098 &buf->idx, sizeof(buf->idx)))
1100 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1101 &buf->total, sizeof(buf->total)))
1109 int mga_dma_buffers(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1112 struct drm_device_dma *dma = dev->dma;
1113 drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1114 struct drm_dma *d = data;
1117 LOCK_TEST_WITH_RETURN(dev, file_priv);
1119 /* Please don't send us buffers.
1121 if (d->send_count != 0) {
1122 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1123 DRM_CURRENTPID, d->send_count);
1127 /* We'll send you buffers.
1129 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1130 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1131 DRM_CURRENTPID, d->request_count, dma->buf_count);
1135 WRAP_TEST_WITH_RETURN(dev_priv);
1137 d->granted_count = 0;
1139 if (d->request_count) {
1140 ret = mga_dma_get_buffers(dev, file_priv, d);
1147 * Called just before the module is unloaded.
1149 int mga_driver_unload(struct drm_device * dev)
1151 drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1152 dev->dev_private = NULL;
1158 * Called when the last opener of the device is closed.
1160 void mga_driver_lastclose(struct drm_device * dev)
1162 mga_do_cleanup_dma(dev, FULL_CLEANUP);
1165 int mga_driver_dma_quiescent(struct drm_device * dev)
1167 drm_mga_private_t *dev_priv = dev->dev_private;
1168 return mga_do_wait_for_idle(dev_priv);