1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
34 typedef struct drm_mga_primary_buffer {
41 volatile long wrapped;
49 } drm_mga_primary_buffer_t;
51 typedef struct drm_mga_freelist {
52 struct drm_mga_freelist *next;
53 struct drm_mga_freelist *prev;
59 drm_mga_freelist_t *list_entry;
64 typedef struct drm_mga_private {
65 drm_mga_primary_buffer_t prim;
66 drm_mga_sarea_t *sarea_priv;
68 drm_mga_freelist_t *head;
69 drm_mga_freelist_t *tail;
71 unsigned int warp_pipe;
72 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
81 unsigned int front_offset;
82 unsigned int front_pitch;
83 unsigned int back_offset;
84 unsigned int back_pitch;
86 unsigned int depth_cpp;
87 unsigned int depth_offset;
88 unsigned int depth_pitch;
90 unsigned int texture_offset;
91 unsigned int texture_size;
100 drm_map_t *agp_textures;
104 extern int mga_dma_init( DRM_IOCTL_ARGS );
105 extern int mga_dma_flush( DRM_IOCTL_ARGS );
106 extern int mga_dma_reset( DRM_IOCTL_ARGS );
107 extern int mga_dma_buffers( DRM_IOCTL_ARGS );
109 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
110 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
111 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
112 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
113 extern int mga_do_cleanup_dma( drm_device_t *dev );
115 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
116 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
117 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
119 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
122 extern int mga_dma_clear( DRM_IOCTL_ARGS );
123 extern int mga_dma_swap( DRM_IOCTL_ARGS );
124 extern int mga_dma_vertex( DRM_IOCTL_ARGS );
125 extern int mga_dma_indices( DRM_IOCTL_ARGS );
126 extern int mga_dma_iload( DRM_IOCTL_ARGS );
127 extern int mga_dma_blit( DRM_IOCTL_ARGS );
130 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
131 extern int mga_warp_init( drm_mga_private_t *dev_priv );
133 #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
136 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
137 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
139 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
140 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
143 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
144 #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
145 #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
147 static inline u32 _MGA_READ(u32 *addr)
149 DRM_READMEMORYBARRIER();
150 return *(volatile u32 *)addr;
154 #define MGA_READ( reg ) MGA_DEREF( reg )
155 #define MGA_WRITE( reg, val ) do { MGA_DEREF( reg ) = val; } while (0)
156 #define MGA_WRITE8( reg, val ) do { MGA_DEREF8( reg ) = val; } while (0)
159 #define DWGREG0 0x1c00
160 #define DWGREG0_END 0x1dff
161 #define DWGREG1 0x2c00
162 #define DWGREG1_END 0x2dff
164 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
165 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
166 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
167 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
171 /* ================================================================
175 #define MGA_EMIT_STATE( dev_priv, dirty ) \
177 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
178 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \
179 mga_g400_emit_state( dev_priv ); \
181 mga_g200_emit_state( dev_priv ); \
186 #define LOCK_TEST_WITH_RETURN( dev ) \
188 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
189 dev->lock.pid != DRM_CURRENTPID ) { \
190 DRM_ERROR( "%s called without lock held\n", \
192 return DRM_ERR(EINVAL); \
196 #define WRAP_TEST_WITH_RETURN( dev_priv ) \
198 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
199 if ( mga_is_idle( dev_priv ) ) { \
200 mga_do_dma_wrap_end( dev_priv ); \
201 } else if ( dev_priv->prim.space < \
202 dev_priv->prim.high_mark ) { \
203 if ( MGA_DMA_DEBUG ) \
204 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
205 return DRM_ERR(EBUSY); \
210 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \
212 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
213 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
214 if ( MGA_DMA_DEBUG ) \
215 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
216 return DRM_ERR(EBUSY); \
218 mga_do_dma_wrap_end( dev_priv ); \
223 /* ================================================================
224 * Primary DMA command stream
227 #define MGA_VERBOSE 0
229 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
231 #define DMA_BLOCK_SIZE (5 * sizeof(u32))
233 #define BEGIN_DMA( n ) \
235 if ( MGA_VERBOSE ) { \
236 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
237 (n), __FUNCTION__ ); \
238 DRM_INFO( " space=0x%x req=0x%x\n", \
239 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
241 prim = dev_priv->prim.start; \
242 write = dev_priv->prim.tail; \
245 #define BEGIN_DMA_WRAP() \
247 if ( MGA_VERBOSE ) { \
248 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
249 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
251 prim = dev_priv->prim.start; \
252 write = dev_priv->prim.tail; \
255 #define ADVANCE_DMA() \
257 dev_priv->prim.tail = write; \
258 if ( MGA_VERBOSE ) { \
259 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
260 write, dev_priv->prim.space ); \
264 #define FLUSH_DMA() \
267 DRM_INFO( "%s:\n", __FUNCTION__ ); \
268 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
269 dev_priv->prim.tail, \
270 MGA_READ( MGA_PRIMADDRESS ) - \
271 dev_priv->primary->offset ); \
273 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
274 if ( dev_priv->prim.space < \
275 dev_priv->prim.high_mark ) { \
276 mga_do_dma_wrap_start( dev_priv ); \
278 mga_do_dma_flush( dev_priv ); \
283 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
285 #define DMA_WRITE( offset, val ) \
287 if ( MGA_VERBOSE ) { \
288 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04x\n", \
289 (u32)(val), write + (offset) * sizeof(u32) ); \
291 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
294 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
296 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
297 (DMAREG( reg1 ) << 8) | \
298 (DMAREG( reg2 ) << 16) | \
299 (DMAREG( reg3 ) << 24)) ); \
300 DMA_WRITE( 1, val0 ); \
301 DMA_WRITE( 2, val1 ); \
302 DMA_WRITE( 3, val2 ); \
303 DMA_WRITE( 4, val3 ); \
304 write += DMA_BLOCK_SIZE; \
308 /* Buffer aging via primary DMA stream head pointer.
311 #define SET_AGE( age, h, w ) \
317 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
318 ( (age)->wrap == w && \
321 #define AGE_BUFFER( buf_priv ) \
323 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
324 if ( (buf_priv)->dispatched ) { \
325 entry->age.head = (dev_priv->prim.tail + \
326 dev_priv->primary->offset); \
327 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
329 entry->age.head = 0; \
330 entry->age.wrap = 0; \
335 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
338 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
341 #define MGA_DMA_DEBUG 0
345 /* A reduced set of the mga registers.
347 #define MGA_CRTC_INDEX 0x1fd4
349 #define MGA_ALPHACTRL 0x2c7c
350 #define MGA_AR0 0x1c60
351 #define MGA_AR1 0x1c64
352 #define MGA_AR2 0x1c68
353 #define MGA_AR3 0x1c6c
354 #define MGA_AR4 0x1c70
355 #define MGA_AR5 0x1c74
356 #define MGA_AR6 0x1c78
358 #define MGA_CXBNDRY 0x1c80
359 #define MGA_CXLEFT 0x1ca0
360 #define MGA_CXRIGHT 0x1ca4
362 #define MGA_DMAPAD 0x1c54
363 #define MGA_DSTORG 0x2cb8
364 #define MGA_DWGCTL 0x1c00
365 # define MGA_OPCOD_MASK (15 << 0)
366 # define MGA_OPCOD_TRAP (4 << 0)
367 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
368 # define MGA_OPCOD_BITBLT (8 << 0)
369 # define MGA_OPCOD_ILOAD (9 << 0)
370 # define MGA_ATYPE_MASK (7 << 4)
371 # define MGA_ATYPE_RPL (0 << 4)
372 # define MGA_ATYPE_RSTR (1 << 4)
373 # define MGA_ATYPE_ZI (3 << 4)
374 # define MGA_ATYPE_BLK (4 << 4)
375 # define MGA_ATYPE_I (7 << 4)
376 # define MGA_LINEAR (1 << 7)
377 # define MGA_ZMODE_MASK (7 << 8)
378 # define MGA_ZMODE_NOZCMP (0 << 8)
379 # define MGA_ZMODE_ZE (2 << 8)
380 # define MGA_ZMODE_ZNE (3 << 8)
381 # define MGA_ZMODE_ZLT (4 << 8)
382 # define MGA_ZMODE_ZLTE (5 << 8)
383 # define MGA_ZMODE_ZGT (6 << 8)
384 # define MGA_ZMODE_ZGTE (7 << 8)
385 # define MGA_SOLID (1 << 11)
386 # define MGA_ARZERO (1 << 12)
387 # define MGA_SGNZERO (1 << 13)
388 # define MGA_SHIFTZERO (1 << 14)
389 # define MGA_BOP_MASK (15 << 16)
390 # define MGA_BOP_ZERO (0 << 16)
391 # define MGA_BOP_DST (10 << 16)
392 # define MGA_BOP_SRC (12 << 16)
393 # define MGA_BOP_ONE (15 << 16)
394 # define MGA_TRANS_SHIFT 20
395 # define MGA_TRANS_MASK (15 << 20)
396 # define MGA_BLTMOD_MASK (15 << 25)
397 # define MGA_BLTMOD_BMONOLEF (0 << 25)
398 # define MGA_BLTMOD_BMONOWF (4 << 25)
399 # define MGA_BLTMOD_PLAN (1 << 25)
400 # define MGA_BLTMOD_BFCOL (2 << 25)
401 # define MGA_BLTMOD_BU32BGR (3 << 25)
402 # define MGA_BLTMOD_BU32RGB (7 << 25)
403 # define MGA_BLTMOD_BU24BGR (11 << 25)
404 # define MGA_BLTMOD_BU24RGB (15 << 25)
405 # define MGA_PATTERN (1 << 29)
406 # define MGA_TRANSC (1 << 30)
407 # define MGA_CLIPDIS (1 << 31)
408 #define MGA_DWGSYNC 0x2c4c
410 #define MGA_FCOL 0x1c24
411 #define MGA_FIFOSTATUS 0x1e10
412 #define MGA_FOGCOL 0x1cf4
413 #define MGA_FXBNDRY 0x1c84
414 #define MGA_FXLEFT 0x1ca8
415 #define MGA_FXRIGHT 0x1cac
417 #define MGA_ICLEAR 0x1e18
418 # define MGA_SOFTRAPICLR (1 << 0)
419 #define MGA_IEN 0x1e1c
420 # define MGA_SOFTRAPIEN (1 << 0)
422 #define MGA_LEN 0x1c5c
424 #define MGA_MACCESS 0x1c04
426 #define MGA_PITCH 0x1c8c
427 #define MGA_PLNWT 0x1c1c
428 #define MGA_PRIMADDRESS 0x1e58
429 # define MGA_DMA_GENERAL (0 << 0)
430 # define MGA_DMA_BLIT (1 << 0)
431 # define MGA_DMA_VECTOR (2 << 0)
432 # define MGA_DMA_VERTEX (3 << 0)
433 #define MGA_PRIMEND 0x1e5c
434 # define MGA_PRIMNOSTART (1 << 0)
435 # define MGA_PAGPXFER (1 << 1)
436 #define MGA_PRIMPTR 0x1e50
437 # define MGA_PRIMPTREN0 (1 << 0)
438 # define MGA_PRIMPTREN1 (1 << 1)
440 #define MGA_RST 0x1e40
441 # define MGA_SOFTRESET (1 << 0)
442 # define MGA_SOFTEXTRST (1 << 1)
444 #define MGA_SECADDRESS 0x2c40
445 #define MGA_SECEND 0x2c44
446 #define MGA_SETUPADDRESS 0x2cd0
447 #define MGA_SETUPEND 0x2cd4
448 #define MGA_SGN 0x1c58
449 #define MGA_SOFTRAP 0x2c48
450 #define MGA_SRCORG 0x2cb4
451 # define MGA_SRMMAP_MASK (1 << 0)
452 # define MGA_SRCMAP_FB (0 << 0)
453 # define MGA_SRCMAP_SYSMEM (1 << 0)
454 # define MGA_SRCACC_MASK (1 << 1)
455 # define MGA_SRCACC_PCI (0 << 1)
456 # define MGA_SRCACC_AGP (1 << 1)
457 #define MGA_STATUS 0x1e14
458 # define MGA_SOFTRAPEN (1 << 0)
459 # define MGA_DWGENGSTS (1 << 16)
460 # define MGA_ENDPRDMASTS (1 << 17)
461 #define MGA_STENCIL 0x2cc8
462 #define MGA_STENCILCTL 0x2ccc
464 #define MGA_TDUALSTAGE0 0x2cf8
465 #define MGA_TDUALSTAGE1 0x2cfc
466 #define MGA_TEXBORDERCOL 0x2c5c
467 #define MGA_TEXCTL 0x2c30
468 #define MGA_TEXCTL2 0x2c3c
469 # define MGA_DUALTEX (1 << 7)
470 # define MGA_G400_TC2_MAGIC (1 << 15)
471 # define MGA_MAP1_ENABLE (1 << 31)
472 #define MGA_TEXFILTER 0x2c58
473 #define MGA_TEXHEIGHT 0x2c2c
474 #define MGA_TEXORG 0x2c24
475 # define MGA_TEXORGMAP_MASK (1 << 0)
476 # define MGA_TEXORGMAP_FB (0 << 0)
477 # define MGA_TEXORGMAP_SYSMEM (1 << 0)
478 # define MGA_TEXORGACC_MASK (1 << 1)
479 # define MGA_TEXORGACC_PCI (0 << 1)
480 # define MGA_TEXORGACC_AGP (1 << 1)
481 #define MGA_TEXORG1 0x2ca4
482 #define MGA_TEXORG2 0x2ca8
483 #define MGA_TEXORG3 0x2cac
484 #define MGA_TEXORG4 0x2cb0
485 #define MGA_TEXTRANS 0x2c34
486 #define MGA_TEXTRANSHIGH 0x2c38
487 #define MGA_TEXWIDTH 0x2c28
489 #define MGA_WACCEPTSEQ 0x1dd4
490 #define MGA_WCODEADDR 0x1e6c
491 #define MGA_WFLAG 0x1dc4
492 #define MGA_WFLAG1 0x1de0
493 #define MGA_WFLAGNB 0x1e64
494 #define MGA_WFLAGNB1 0x1e08
495 #define MGA_WGETMSB 0x1dc8
496 #define MGA_WIADDR 0x1dc0
497 #define MGA_WIADDR2 0x1dd8
498 # define MGA_WMODE_SUSPEND (0 << 0)
499 # define MGA_WMODE_RESUME (1 << 0)
500 # define MGA_WMODE_JUMP (2 << 0)
501 # define MGA_WMODE_START (3 << 0)
502 # define MGA_WAGP_ENABLE (1 << 2)
503 #define MGA_WMISC 0x1e70
504 # define MGA_WUCODECACHE_ENABLE (1 << 0)
505 # define MGA_WMASTER_ENABLE (1 << 1)
506 # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
507 #define MGA_WVRTXSZ 0x1dcc
509 #define MGA_YBOT 0x1c9c
510 #define MGA_YDST 0x1c90
511 #define MGA_YDSTLEN 0x1c88
512 #define MGA_YDSTORG 0x1c94
513 #define MGA_YTOP 0x1c98
515 #define MGA_ZORG 0x1c0c
517 /* This finishes the current batch of commands
519 #define MGA_EXEC 0x0100
523 #define MGA_WR0 0x2d00
524 #define MGA_WR1 0x2d04
525 #define MGA_WR2 0x2d08
526 #define MGA_WR3 0x2d0c
527 #define MGA_WR4 0x2d10
528 #define MGA_WR5 0x2d14
529 #define MGA_WR6 0x2d18
530 #define MGA_WR7 0x2d1c
531 #define MGA_WR8 0x2d20
532 #define MGA_WR9 0x2d24
533 #define MGA_WR10 0x2d28
534 #define MGA_WR11 0x2d2c
535 #define MGA_WR12 0x2d30
536 #define MGA_WR13 0x2d34
537 #define MGA_WR14 0x2d38
538 #define MGA_WR15 0x2d3c
539 #define MGA_WR16 0x2d40
540 #define MGA_WR17 0x2d44
541 #define MGA_WR18 0x2d48
542 #define MGA_WR19 0x2d4c
543 #define MGA_WR20 0x2d50
544 #define MGA_WR21 0x2d54
545 #define MGA_WR22 0x2d58
546 #define MGA_WR23 0x2d5c
547 #define MGA_WR24 0x2d60
548 #define MGA_WR25 0x2d64
549 #define MGA_WR26 0x2d68
550 #define MGA_WR27 0x2d6c
551 #define MGA_WR28 0x2d70
552 #define MGA_WR29 0x2d74
553 #define MGA_WR30 0x2d78
554 #define MGA_WR31 0x2d7c
555 #define MGA_WR32 0x2d80
556 #define MGA_WR33 0x2d84
557 #define MGA_WR34 0x2d88
558 #define MGA_WR35 0x2d8c
559 #define MGA_WR36 0x2d90
560 #define MGA_WR37 0x2d94
561 #define MGA_WR38 0x2d98
562 #define MGA_WR39 0x2d9c
563 #define MGA_WR40 0x2da0
564 #define MGA_WR41 0x2da4
565 #define MGA_WR42 0x2da8
566 #define MGA_WR43 0x2dac
567 #define MGA_WR44 0x2db0
568 #define MGA_WR45 0x2db4
569 #define MGA_WR46 0x2db8
570 #define MGA_WR47 0x2dbc
571 #define MGA_WR48 0x2dc0
572 #define MGA_WR49 0x2dc4
573 #define MGA_WR50 0x2dc8
574 #define MGA_WR51 0x2dcc
575 #define MGA_WR52 0x2dd0
576 #define MGA_WR53 0x2dd4
577 #define MGA_WR54 0x2dd8
578 #define MGA_WR55 0x2ddc
579 #define MGA_WR56 0x2de0
580 #define MGA_WR57 0x2de4
581 #define MGA_WR58 0x2de8
582 #define MGA_WR59 0x2dec
583 #define MGA_WR60 0x2df0
584 #define MGA_WR61 0x2df4
585 #define MGA_WR62 0x2df8
586 #define MGA_WR63 0x2dfc
587 # define MGA_G400_WR_MAGIC (1 << 6)
588 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
591 #define MGA_ILOAD_ALIGN 64
592 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
594 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
600 (15 << MGA_TRANS_SHIFT))
602 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
609 (0 << MGA_TRANS_SHIFT) | \
610 MGA_BLTMOD_BMONOLEF | \
614 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
619 (0 << MGA_TRANS_SHIFT) | \
625 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
627 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
628 return ( status == MGA_ENDPRDMASTS );