shared-core/nouveau_fifo.c

   1 /*
   2  * Copyright 2005-2006 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drv.h"
  28 #include "nouveau_drm.h"
  29
  30
  31 /* returns the number of hw fifos */
  32 int nouveau_fifo_number(drm_device_t* dev)
  33 {
  34         drm_nouveau_private_t *dev_priv=dev->dev_private;
  35         switch(dev_priv->card_type)
  36         {
  37                 case NV_03:
  38                         return 8;
  39                 case NV_04:
  40                 case NV_05:
  41                         return 16;
  42                 default:
  43                         return 32;
  44         }
  45 }
  46
  47 /* returns the size of fifo context */
  48 static int nouveau_fifo_ctx_size(drm_device_t* dev)
  49 {
  50         drm_nouveau_private_t *dev_priv=dev->dev_private;
  51
  52         if (dev_priv->card_type >= NV_40)
  53                 return 128;
  54         else if (dev_priv->card_type >= NV_10)
  55                 return 64;
  56         else
  57                 return 32;
  58 }
  59
  60 /***********************************
  61  * functions doing the actual work
  62  ***********************************/
  63
  64 /* voir nv_xaa.c : NVResetGraphics
  65  * mémoire mappée par nv_driver.c : NVMapMem
  66  * voir nv_driver.c : NVPreInit
  67  */
  68
  69 static int nouveau_fifo_instmem_configure(drm_device_t *dev)
  70 {
  71         drm_nouveau_private_t *dev_priv = dev->dev_private;
  72         int i;
  73
  74         /* Clear start of RAMIN, enough to cover RAMFC/HT/RO basically */
  75         for (i=0x00710000; i<0x00730000; i++)
  76                 NV_WRITE(i, 0x00000000);
  77
  78         /* FIFO hash table (RAMHT)
  79          *   use 4k hash table at RAMIN+0x10000
  80          *   TODO: extend the hash table
  81          */
  82         dev_priv->ramht_offset = 0x10000;
  83         dev_priv->ramht_bits   = 9;
  84         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
  85         NV_WRITE(NV03_PFIFO_RAMHT,
  86                         (0x03 << 24) /* search 128 */ |
  87                         ((dev_priv->ramht_bits - 9) << 16) |
  88                         (dev_priv->ramht_offset >> 8)
  89                         );
  90         DRM_DEBUG("RAMHT offset=0x%x, size=%d\n",
  91                         dev_priv->ramht_offset,
  92                         dev_priv->ramht_size);
  93
  94         /* FIFO runout table (RAMRO) - 512k at 0x11200 */
  95         dev_priv->ramro_offset = 0x11200;
  96         dev_priv->ramro_size   = 512;
  97         NV_WRITE(NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
  98         DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
  99                         dev_priv->ramro_offset,
 100                         dev_priv->ramro_size);
 101
 102         /* FIFO context table (RAMFC)
 103          *   NV40  : Not sure exactly how to position RAMFC on some cards,
 104          *           0x30002 seems to position it at RAMIN+0x20000 on these
 105          *           cards.  RAMFC is 4kb (32 fifos, 128byte entries).
 106          *   Others: Position RAMFC at RAMIN+0x11400
 107          */
 108         switch(dev_priv->card_type)
 109         {
 110                 case NV_50:
 111                 case NV_40:
 112                         dev_priv->ramfc_offset = 0x20000;
 113                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 114                         NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
 115                         break;
 116                 case NV_44:
 117                         dev_priv->ramfc_offset = 0x20000;
 118                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 119                         NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
 120                                         (2 << 16));
 121                         break;
 122                 case NV_30:
 123                 case NV_20:
 124                 case NV_10:
 125                         dev_priv->ramfc_offset = 0x11400;
 126                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 127                         NV_WRITE(NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
 128                                         (1 << 16) /* 64 Bytes entry*/);
 129                         break;
 130                 case NV_04:
 131                 case NV_03:
 132                         dev_priv->ramfc_offset = 0x11400;
 133                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 134                         NV_WRITE(NV03_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
 135                         break;
 136         }
 137         DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
 138                         dev_priv->ramfc_offset,
 139                         dev_priv->ramfc_size);
 140
 141         if (nouveau_instmem_init(dev, dev_priv->ramfc_offset +
 142                                       dev_priv->ramfc_size))
 143                 return 1;
 144
 145         return 0;
 146 }
 147
 148 int nouveau_fifo_init(drm_device_t *dev)
 149 {
 150         drm_nouveau_private_t *dev_priv = dev->dev_private;
 151         int ret;
 152
 153         NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
 154
 155         ret = nouveau_fifo_instmem_configure(dev);
 156         if (ret) {
 157                 DRM_ERROR("Failed to configure instance memory\n");
 158                 return ret;
 159         }
 160
 161         /* FIXME remove all the stuff that's done in nouveau_fifo_alloc */
 162
 163         DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
 164
 165         /* All channels into PIO mode */
 166         NV_WRITE(NV04_PFIFO_MODE, 0x00000000);
 167
 168         NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
 169         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 170         /* Channel 0 active, PIO mode */
 171         NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000000);
 172         /* PUT and GET to 0 */
 173         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0x00000000);
 174         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0x00000000);
 175         /* No cmdbuf object */
 176         NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, 0x00000000);
 177         NV_WRITE(NV03_PFIFO_CACHE0_PUSH0, 0x00000000);
 178         NV_WRITE(NV03_PFIFO_CACHE0_PULL0, 0x00000000);
 179         NV_WRITE(NV04_PFIFO_SIZE, 0x0000FFFF);
 180         NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
 181         NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
 182         NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
 183         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
 184         NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
 185
 186         NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
 187                                       NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 188                                       NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
 189 #ifdef __BIG_ENDIAN
 190                                       NV_PFIFO_CACHE1_BIG_ENDIAN |
 191 #endif
 192                                       0x00000000);
 193
 194         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
 195         NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
 196         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
 197         NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
 198
 199         /* FIXME on NV04 */
 200         if (dev_priv->card_type >= NV_10) {
 201                 NV_WRITE(NV10_PGRAPH_CTX_USER, 0x0);
 202                 NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
 203                 if (dev_priv->card_type >= NV_40)
 204                         NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x00002001);
 205                 else
 206                         NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10110000);
 207         } else {
 208                 NV_WRITE(NV04_PGRAPH_CTX_USER, 0x0);
 209                 NV_WRITE(NV04_PFIFO_DELAY_0, 0xff /* retrycount*/ );
 210                 NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10110000);
 211         }
 212
 213         NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x001fffff);
 214         NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
 215         return 0;
 216 }
 217
 218 static int
 219 nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
 220 {
 221         drm_nouveau_private_t *dev_priv = dev->dev_private;
 222         struct nouveau_config *config = &dev_priv->config;
 223         struct mem_block *cb;
 224         struct nouveau_object *cb_dma = NULL;
 225         int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);
 226
 227         /* Defaults for unconfigured values */
 228         if (!config->cmdbuf.location)
 229                 config->cmdbuf.location = NOUVEAU_MEM_FB;
 230         if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size)
 231                 config->cmdbuf.size = cb_min_size;
 232
 233         cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
 234                         config->cmdbuf.location | NOUVEAU_MEM_MAPPED,
 235                         (DRMFILE)-2);
 236         if (!cb) {
 237                 DRM_ERROR("Couldn't allocate DMA command buffer.\n");
 238                 return DRM_ERR(ENOMEM);
 239         }
 240
 241         if (cb->flags & NOUVEAU_MEM_AGP) {
 242                 cb_dma = nouveau_dma_object_create(dev, NV_CLASS_DMA_IN_MEMORY,
 243                                 cb->start - dev_priv->agp_phys,
 244                                 cb->size,
 245                                 NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP);
 246         } else if (dev_priv->card_type != NV_04) {
 247                 cb_dma = nouveau_dma_object_create(dev, NV_CLASS_DMA_IN_MEMORY,
 248                                 cb->start - drm_get_resource_start(dev, 1),
 249                                 cb->size,
 250                                 NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM);
 251         } else {
 252                 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
 253                  * exact reason for existing :)  PCI access to cmdbuf in
 254                  * VRAM.
 255                  */
 256                 cb_dma = nouveau_dma_object_create(dev, NV_CLASS_DMA_IN_MEMORY,
 257                                 cb->start, cb->size,
 258                                 NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI);
 259         }
 260
 261         if (!cb_dma) {
 262                 nouveau_mem_free(dev, cb);
 263                 DRM_ERROR("Failed to alloc DMA object for command buffer\n");
 264                 return DRM_ERR(ENOMEM);
 265         }
 266
 267         dev_priv->fifos[channel].cmdbuf_mem = cb;
 268         dev_priv->fifos[channel].cmdbuf_obj = cb_dma;
 269         return 0;
 270 }
 271
 272 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val))
 273 static void nouveau_nv04_context_init(drm_device_t *dev,
 274                 drm_nouveau_fifo_alloc_t *init)
 275 {
 276         drm_nouveau_private_t *dev_priv = dev->dev_private;
 277         struct nouveau_object *cb_obj;
 278         uint32_t fifoctx, ctx_size = 32;
 279         int i;
 280
 281         cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
 282
 283         fifoctx=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
 284
 285         // clear the fifo context
 286         for(i=0;i<ctx_size/4;i++)
 287                 NV_WRITE(fifoctx+4*i,0x0);
 288
 289         RAMFC_WR(DMA_PUT        , init->put_base);
 290         RAMFC_WR(DMA_GET        , init->put_base);
 291         RAMFC_WR(DMA_INSTANCE   , nouveau_chip_instance_get(dev, cb_obj->instance));
 292
 293         RAMFC_WR(DMA_FETCH,     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
 294                                 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 295                                 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4     |
 296 #ifdef __BIG_ENDIAN
 297                                 NV_PFIFO_CACHE1_BIG_ENDIAN |
 298 #endif
 299                                 0x00000000);
 300 }
 301 #undef RAMFC_WR
 302
 303 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val))
 304 static void nouveau_nv10_context_init(drm_device_t *dev,
 305                 drm_nouveau_fifo_alloc_t *init)
 306 {
 307         drm_nouveau_private_t *dev_priv = dev->dev_private;
 308         struct nouveau_object *cb_obj;
 309         uint32_t fifoctx;
 310         int i;
 311         cb_obj  = dev_priv->fifos[init->channel].cmdbuf_obj;
 312         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*64;
 313
 314         for (i=0;i<64;i+=4)
 315                 NV_WRITE(fifoctx + i, 0);
 316
 317         /* Fill entries that are seen filled in dumps of nvidia driver just
 318          * after channel's is put into DMA mode
 319          */
 320
 321         RAMFC_WR(DMA_PUT       , init->put_base);
 322         RAMFC_WR(DMA_GET       , init->put_base);
 323         RAMFC_WR(DMA_INSTANCE  , nouveau_chip_instance_get(dev,
 324                                 cb_obj->instance));
 325
 326         RAMFC_WR(DMA_FETCH, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
 327                         NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 328                         NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4     |
 329 #ifdef __BIG_ENDIAN
 330                         NV_PFIFO_CACHE1_BIG_ENDIAN |
 331 #endif
 332                         0x00000000);
 333 }
 334
 335 static void nouveau_nv30_context_init(drm_device_t *dev,
 336                                       drm_nouveau_fifo_alloc_t *init)
 337 {
 338         drm_nouveau_private_t *dev_priv = dev->dev_private;
 339         struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
 340         struct nouveau_object *cb_obj;
 341         uint32_t fifoctx, grctx_inst, cb_inst, ctx_size = 64;
 342         int i;
 343
 344         cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
 345         cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
 346         grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
 347         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel * ctx_size;
 348
 349         for (i = 0; i < ctx_size; i += 4)
 350                 NV_WRITE(fifoctx + i, 0);
 351
 352         RAMFC_WR(DMA_PUT,       init->put_base);
 353         RAMFC_WR(DMA_GET,       init->put_base);
 354         RAMFC_WR(REF_CNT,       NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
 355         RAMFC_WR(DMA_INSTANCE,  cb_inst);
 356         RAMFC_WR(DMA_STATE,     NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 357         RAMFC_WR(DMA_FETCH,     NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 358                                 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 359                                 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 360 #ifdef __BIG_ENDIAN
 361                                 NV_PFIFO_CACHE1_BIG_ENDIAN |
 362 #endif
 363                                 0x00000000);
 364
 365         RAMFC_WR(ENGINE,                NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 366         RAMFC_WR(PULL1_ENGINE,          NV_READ(NV04_PFIFO_CACHE1_PULL1));
 367         RAMFC_WR(ACQUIRE_VALUE,         NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 368         RAMFC_WR(ACQUIRE_TIMESTAMP,     NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
 369         RAMFC_WR(ACQUIRE_TIMEOUT,       NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 370         RAMFC_WR(SEMAPHORE,             NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 371
 372         RAMFC_WR(DMA_SUBROUTINE,        init->put_base);
 373 }
 374
 375 static void nouveau_nv10_context_save(drm_device_t *dev)
 376 {
 377         drm_nouveau_private_t *dev_priv = dev->dev_private;
 378         uint32_t fifoctx;
 379         int channel;
 380
 381         channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
 382         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
 383
 384         RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
 385         RAMFC_WR(DMA_GET          , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 386         RAMFC_WR(REF_CNT          , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
 387         RAMFC_WR(DMA_INSTANCE     , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
 388         RAMFC_WR(DMA_STATE        , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 389         RAMFC_WR(DMA_FETCH        , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
 390         RAMFC_WR(ENGINE           , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 391         RAMFC_WR(PULL1_ENGINE     , NV_READ(NV04_PFIFO_CACHE1_PULL1));
 392         RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 393         RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
 394         RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 395         RAMFC_WR(SEMAPHORE        , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 396         RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV10_PFIFO_CACHE1_DMA_SUBROUTINE));
 397 }
 398 #undef RAMFC_WR
 399
 400 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
 401 static void nouveau_nv40_context_init(drm_device_t *dev,
 402                                       drm_nouveau_fifo_alloc_t *init)
 403 {
 404         drm_nouveau_private_t *dev_priv = dev->dev_private;
 405         struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
 406         uint32_t fifoctx, cb_inst, grctx_inst;
 407         int i;
 408
 409         cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
 410         grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
 411         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128;
 412         for (i=0;i<128;i+=4)
 413                 NV_WRITE(fifoctx + i, 0);
 414
 415         /* Fill entries that are seen filled in dumps of nvidia driver just
 416          * after channel's is put into DMA mode
 417          */
 418         RAMFC_WR(DMA_PUT       , init->put_base);
 419         RAMFC_WR(DMA_GET       , init->put_base);
 420         RAMFC_WR(DMA_INSTANCE  , cb_inst);
 421         RAMFC_WR(DMA_FETCH     , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
 422                                  NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 423                                  NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
 424 #ifdef __BIG_ENDIAN
 425                                  NV_PFIFO_CACHE1_BIG_ENDIAN |
 426 #endif
 427                                  0x30000000 /* no idea.. */);
 428         RAMFC_WR(DMA_SUBROUTINE, init->put_base);
 429         RAMFC_WR(GRCTX_INSTANCE, grctx_inst);
 430         RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
 431 }
 432
 433 static void nouveau_nv40_context_save(drm_device_t *dev)
 434 {
 435         drm_nouveau_private_t *dev_priv = dev->dev_private;
 436         uint32_t fifoctx;
 437         int channel;
 438
 439         channel = NV_READ(NV03_PFIFO_CACHE1_PUSH1) & (nouveau_fifo_number(dev)-1);
 440         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;
 441
 442         RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
 443         RAMFC_WR(DMA_GET          , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 444         RAMFC_WR(REF_CNT          , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
 445         RAMFC_WR(DMA_INSTANCE     , NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE));
 446         RAMFC_WR(DMA_DCOUNT       , NV_READ(NV10_PFIFO_CACHE1_DMA_DCOUNT));
 447         RAMFC_WR(DMA_STATE        , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 448         RAMFC_WR(DMA_FETCH        , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
 449         RAMFC_WR(ENGINE           , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 450         RAMFC_WR(PULL1_ENGINE     , NV_READ(NV04_PFIFO_CACHE1_PULL1));
 451         RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 452         RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
 453         RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 454         RAMFC_WR(SEMAPHORE        , NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 455         RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 456         RAMFC_WR(GRCTX_INSTANCE   , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
 457         RAMFC_WR(DMA_TIMESLICE    , NV_READ(NV04_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
 458         RAMFC_WR(UNK_40           , NV_READ(NV40_PFIFO_UNK32E4));
 459 }
 460 #undef RAMFC_WR
 461
 462 /* This function should load values from RAMFC into PFIFO, but for now
 463  * it just clobbers PFIFO with what nouveau_fifo_alloc used to setup
 464  * unconditionally.
 465  */
 466 static void
 467 nouveau_fifo_context_restore(drm_device_t *dev, int channel)
 468 {
 469         drm_nouveau_private_t *dev_priv = dev->dev_private;
 470         struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 471         uint32_t cb_inst;
 472
 473         cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
 474
 475         // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);
 476
 477         if (dev_priv->card_type >= NV_40)
 478                 NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00010000|channel);
 479         else
 480                 NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, 0x00000100|channel);
 481
 482         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, 0 /*RAMFC_DMA_PUT*/);
 483         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, 0 /*RAMFC_DMA_GET*/);
 484         NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, cb_inst);
 485         NV_WRITE(NV04_PFIFO_SIZE , 0x0000FFFF);
 486         NV_WRITE(NV04_PFIFO_CACHE1_HASH, 0x0000FFFF);
 487
 488         NV_WRITE(NV04_PFIFO_CACHE0_PULL1, 0x00000001);
 489         NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, 0x00000000);
 490         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
 491         NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, 0x00000000);
 492
 493         NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH,   NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES |
 494                                         NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
 495                                         NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4 |
 496 #ifdef __BIG_ENDIAN
 497                                         NV_PFIFO_CACHE1_BIG_ENDIAN |
 498 #endif
 499                                         0x00000000);
 500 }
 501
 502 /* allocates and initializes a fifo for user space consumption */
 503 static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp)
 504 {
 505         int i;
 506         int ret;
 507         drm_nouveau_private_t *dev_priv = dev->dev_private;
 508         struct nouveau_object *cb_obj;
 509
 510         /*
 511          * Alright, here is the full story
 512          * Nvidia cards have multiple hw fifo contexts (praise them for that,
 513          * no complicated crash-prone context switches)
 514          * We allocate a new context for each app and let it write to it directly
 515          * (woo, full userspace command submission !)
 516          * When there are no more contexts, you lost
 517          */
 518         for(i=0;i<nouveau_fifo_number(dev);i++)
 519                 if (dev_priv->fifos[i].used==0)
 520                         break;
 521
 522         DRM_INFO("Allocating FIFO number %d\n", i);
 523         /* no more fifos. you lost. */
 524         if (i==nouveau_fifo_number(dev))
 525                 return DRM_ERR(EINVAL);
 526
 527         /* allocate a command buffer, and create a dma object for the gpu */
 528         ret = nouveau_fifo_cmdbuf_alloc(dev, i);
 529         if (ret) return ret;
 530         cb_obj = dev_priv->fifos[i].cmdbuf_obj;
 531
 532         /* that fifo is used */
 533         dev_priv->fifos[i].used=1;
 534         dev_priv->fifos[i].filp=filp;
 535
 536         init->channel  = i;
 537         init->put_base = 0;
 538         dev_priv->cur_fifo = init->channel;
 539
 540         nouveau_wait_for_idle(dev);
 541
 542         /* disable the fifo caches */
 543         NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
 544         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, NV_READ(NV04_PFIFO_CACHE1_DMA_PUSH)&(~0x1));
 545         NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000000);
 546         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000000);
 547
 548         /* Construct inital RAMFC for new channel */
 549         switch(dev_priv->card_type)
 550         {
 551                 case NV_04:
 552                 case NV_05:
 553                         nv04_graph_context_create(dev, init->channel);
 554                         nouveau_nv04_context_init(dev, init);
 555                         break;
 556                 case NV_10:
 557                         nv10_graph_context_create(dev, init->channel);
 558                         nouveau_nv10_context_init(dev, init);
 559                         break;
 560                 case NV_20:
 561                         ret = nv20_graph_context_create(dev, init->channel);
 562                         if (ret) {
 563                                 nouveau_fifo_free(dev, init->channel);
 564                                 return ret;
 565                         }
 566                         nouveau_nv10_context_init(dev, init);
 567                         break;
 568                 case NV_30:
 569                         ret = nv30_graph_context_create(dev, init->channel);
 570                         if (ret) {
 571                                 nouveau_fifo_free(dev, init->channel);
 572                                 return ret;
 573                         }
 574                         nouveau_nv30_context_init(dev, init);
 575                         break;
 576                 case NV_40:
 577                 case NV_44:
 578                 case NV_50:
 579                         ret = nv40_graph_context_create(dev, init->channel);
 580                         if (ret) {
 581                                 nouveau_fifo_free(dev, init->channel);
 582                                 return ret;
 583                         }
 584                         nouveau_nv40_context_init(dev, init);
 585                         break;
 586         }
 587
 588         /* enable the fifo dma operation */
 589         NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<init->channel));
 590
 591         /* setup channel's default get/put values */
 592         NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
 593         NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);
 594
 595         /* If this is the first channel, setup PFIFO ourselves.  For any
 596          * other case, the GPU will handle this when it switches contexts.
 597          */
 598         if (dev_priv->fifo_alloc_count == 0) {
 599                 nouveau_fifo_context_restore(dev, init->channel);
 600                 if (dev_priv->card_type >= NV_30) {
 601                         struct nouveau_fifo *chan;
 602                         uint32_t inst;
 603
 604                         chan = &dev_priv->fifos[init->channel];
 605                         inst = nouveau_chip_instance_get(dev,
 606                                                          chan->ramin_grctx);
 607
 608                         /* see comments in nv40_graph_context_restore() */
 609                         NV_WRITE(NV10_PGRAPH_CHANNEL_CTX_SIZE, inst);
 610                         if (dev_priv->card_type >= NV_40) {
 611                                 NV_WRITE(0x40032C, inst | 0x01000000);
 612                                 NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
 613                         }
 614                 }
 615         }
 616
 617         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUSH, 0x00000001);
 618         NV_WRITE(NV03_PFIFO_CACHE1_PUSH0, 0x00000001);
 619         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x00000001);
 620         NV_WRITE(NV04_PFIFO_CACHE1_PULL1, 0x00000001);
 621
 622         /* reenable the fifo caches */
 623         NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
 624
 625         /* make the fifo available to user space */
 626         /* first, the fifo control regs */
 627         init->ctrl      = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel);
 628         init->ctrl_size = NV03_FIFO_REGS_SIZE;
 629         ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
 630                          0, &dev_priv->fifos[init->channel].regs);
 631         if (ret != 0)
 632                 return ret;
 633
 634         /* pass back FIFO map info to the caller */
 635         init->cmdbuf       = dev_priv->fifos[init->channel].cmdbuf_mem->start;
 636         init->cmdbuf_size  = dev_priv->fifos[init->channel].cmdbuf_mem->size;
 637
 638         /* FIFO has no objects yet */
 639         dev_priv->fifos[init->channel].objs = NULL;
 640         dev_priv->fifo_alloc_count++;
 641
 642         DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel);
 643         return 0;
 644 }
 645
 646 /* stops a fifo */
 647 void nouveau_fifo_free(drm_device_t* dev,int n)
 648 {
 649         drm_nouveau_private_t *dev_priv = dev->dev_private;
 650         int i;
 651         int ctx_size = nouveau_fifo_ctx_size(dev);
 652
 653         dev_priv->fifos[n].used=0;
 654         DRM_INFO("%s: freeing fifo %d\n", __func__, n);
 655
 656         /* disable the fifo caches */
 657         NV_WRITE(NV03_PFIFO_CACHES, 0x00000000);
 658
 659         NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)&~(1<<n));
 660         // FIXME XXX needs more code
 661
 662         /* Clean RAMFC */
 663         for (i=0;i<ctx_size;i+=4) {
 664                 DRM_DEBUG("RAMFC +%02x: 0x%08x\n", i, NV_READ(NV_RAMIN +
 665                                         dev_priv->ramfc_offset + n*ctx_size + i));
 666                 NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + n*ctx_size + i, 0);
 667         }
 668
 669         if (dev_priv->card_type >= NV_40)
 670                 nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
 671         else if (dev_priv->card_type >= NV_30) {
 672         }
 673         else if (dev_priv->card_type >= NV_20) {
 674                 /* clear ctx table */
 675                 INSTANCE_WR(dev_priv->ctx_table, n, 0);
 676                 nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
 677         }
 678
 679         /* reenable the fifo caches */
 680         NV_WRITE(NV03_PFIFO_CACHES, 0x00000001);
 681
 682         /* Deallocate command buffer, and dma object */
 683         nouveau_mem_free(dev, dev_priv->fifos[n].cmdbuf_mem);
 684
 685         dev_priv->fifo_alloc_count--;
 686 }
 687
 688 /* cleanups all the fifos from filp */
 689 void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp)
 690 {
 691         int i;
 692         drm_nouveau_private_t *dev_priv = dev->dev_private;
 693
 694         DRM_DEBUG("clearing FIFO enables from filp\n");
 695         for(i=0;i<nouveau_fifo_number(dev);i++)
 696                 if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp==filp)
 697                         nouveau_fifo_free(dev,i);
 698
 699         /* check we still point at an active channel */
 700         if (dev_priv->fifos[dev_priv->cur_fifo].used == 0) {
 701                 DRM_DEBUG("%s: cur_fifo is no longer owned.\n", __func__);
 702                 for (i=0;i<nouveau_fifo_number(dev);i++)
 703                         if (dev_priv->fifos[i].used) break;
 704                 if (i==nouveau_fifo_number(dev))
 705                         i=0;
 706                 DRM_DEBUG("%s: new cur_fifo is %d\n", __func__, i);
 707                 dev_priv->cur_fifo = i;
 708         }
 709
 710 /*      if (dev_priv->cmdbuf_alloc)
 711                 nouveau_fifo_init(dev);*/
 712 }
 713
 714 int nouveau_fifo_id_get(drm_device_t* dev, DRMFILE filp)
 715 {
 716         drm_nouveau_private_t *dev_priv=dev->dev_private;
 717         int i;
 718
 719         for(i=0;i<nouveau_fifo_number(dev);i++)
 720                 if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp == filp)
 721                         return i;
 722         return -1;
 723 }
 724
 725 /***********************************
 726  * ioctls wrapping the functions
 727  ***********************************/
 728
 729 static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS)
 730 {
 731         DRM_DEVICE;
 732         drm_nouveau_fifo_alloc_t init;
 733         int res;
 734         DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init));
 735
 736         res=nouveau_fifo_alloc(dev,&init,filp);
 737         if (!res)
 738                 DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init));
 739
 740         return res;
 741 }
 742
 743 /***********************************
 744  * finally, the ioctl table
 745  ***********************************/
 746
 747 drm_ioctl_desc_t nouveau_ioctls[] = {
 748         [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH},
 749         [DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH},
 750         [DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH},
 751         [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH},
 752         [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH},
 753         [DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH},
 754         [DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 755 };
 756
 757 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);