shared-core/nouveau_fifo.c

   1 /*
   2  * Copyright 2005-2006 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drv.h"
  28 #include "nouveau_drm.h"
  29
  30
  31 /* returns the number of hw fifos */
  32 int nouveau_fifo_number(drm_device_t* dev)
  33 {
  34         drm_nouveau_private_t *dev_priv=dev->dev_private;
  35         switch(dev_priv->card_type)
  36         {
  37                 case NV_03:
  38                         return 8;
  39                 case NV_04:
  40                 case NV_05:
  41                         return 16;
  42                 default:
  43                         return 32;
  44         }
  45 }
  46
  47 /* returns the size of fifo context */
  48 static int nouveau_fifo_ctx_size(drm_device_t* dev)
  49 {
  50         drm_nouveau_private_t *dev_priv=dev->dev_private;
  51
  52         if (dev_priv->card_type >= NV_40)
  53                 return 128;
  54         else if (dev_priv->card_type >= NV_10)
  55                 return 64;
  56         else
  57                 return 32;
  58 }
  59
  60 /***********************************
  61  * functions doing the actual work
  62  ***********************************/
  63
  64 /* voir nv_xaa.c : NVResetGraphics
  65  * mémoire mappée par nv_driver.c : NVMapMem
  66  * voir nv_driver.c : NVPreInit
  67  */
  68
  69 static int nouveau_fifo_instmem_configure(drm_device_t *dev)
  70 {
  71         drm_nouveau_private_t *dev_priv = dev->dev_private;
  72         int i;
  73
  74         /* Clear start of RAMIN, enough to cover RAMFC/HT/RO basically */
  75         for (i=0x00710000; i<0x00730000; i++)
  76                 NV_WRITE(i, 0x00000000);
  77
  78         /* FIFO hash table (RAMHT)
  79          *   use 4k hash table at RAMIN+0x10000
  80          *   TODO: extend the hash table
  81          */
  82         dev_priv->ramht_offset = 0x10000;
  83         dev_priv->ramht_bits   = 9;
  84         dev_priv->ramht_size   = (1 << dev_priv->ramht_bits);
  85         NV_WRITE(NV_PFIFO_RAMHT,
  86                         (0x03 << 24) /* search 128 */ |
  87                         ((dev_priv->ramht_bits - 9) << 16) |
  88                         (dev_priv->ramht_offset >> 8)
  89                         );
  90         DRM_DEBUG("RAMHT offset=0x%x, size=%d\n",
  91                         dev_priv->ramht_offset,
  92                         dev_priv->ramht_size);
  93
  94         /* FIFO runout table (RAMRO) - 512k at 0x11200 */
  95         dev_priv->ramro_offset = 0x11200;
  96         dev_priv->ramro_size   = 512;
  97         NV_WRITE(NV_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
  98         DRM_DEBUG("RAMRO offset=0x%x, size=%d\n",
  99                         dev_priv->ramro_offset,
 100                         dev_priv->ramro_size);
 101
 102         /* FIFO context table (RAMFC)
 103          *   NV40  : Not sure exactly how to position RAMFC on some cards,
 104          *           0x30002 seems to position it at RAMIN+0x20000 on these
 105          *           cards.  RAMFC is 4kb (32 fifos, 128byte entries).
 106          *   Others: Position RAMFC at RAMIN+0x11400
 107          */
 108         switch(dev_priv->card_type)
 109         {
 110                 case NV_50:
 111                 case NV_40:
 112                         dev_priv->ramfc_offset = 0x20000;
 113                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 114                         NV_WRITE(NV40_PFIFO_RAMFC, 0x30002);
 115                         break;
 116                 case NV_44:
 117                         dev_priv->ramfc_offset = 0x20000;
 118                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 119                         NV_WRITE(NV40_PFIFO_RAMFC, ((nouveau_mem_fb_amount(dev)-512*1024+dev_priv->ramfc_offset)>>16) |
 120                                         (2 << 16));
 121                         break;
 122                 case NV_30:
 123                 case NV_20:
 124                 case NV_10:
 125                         dev_priv->ramfc_offset = 0x11400;
 126                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 127                         NV_WRITE(NV_PFIFO_RAMFC, (dev_priv->ramfc_offset>>8) |
 128                                         (1 << 16) /* 64 Bytes entry*/);
 129                         break;
 130                 case NV_04:
 131                 case NV_03:
 132                         dev_priv->ramfc_offset = 0x11400;
 133                         dev_priv->ramfc_size   = nouveau_fifo_number(dev) * nouveau_fifo_ctx_size(dev);
 134                         NV_WRITE(NV_PFIFO_RAMFC, dev_priv->ramfc_offset>>8);
 135                         break;
 136         }
 137         DRM_DEBUG("RAMFC offset=0x%x, size=%d\n",
 138                         dev_priv->ramfc_offset,
 139                         dev_priv->ramfc_size);
 140
 141         if (nouveau_instmem_init(dev, dev_priv->ramfc_offset +
 142                                       dev_priv->ramfc_size))
 143                 return 1;
 144
 145         return 0;
 146 }
 147
 148 int nouveau_fifo_init(drm_device_t *dev)
 149 {
 150         drm_nouveau_private_t *dev_priv = dev->dev_private;
 151         int ret;
 152
 153         NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
 154
 155         ret = nouveau_fifo_instmem_configure(dev);
 156         if (ret) {
 157                 DRM_ERROR("Failed to configure instance memory\n");
 158                 return ret;
 159         }
 160
 161         /* FIXME remove all the stuff that's done in nouveau_fifo_alloc */
 162
 163         DRM_DEBUG("Setting defaults for remaining PFIFO regs\n");
 164
 165         /* All channels into PIO mode */
 166         NV_WRITE(NV_PFIFO_MODE, 0x00000000);
 167
 168         NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
 169         NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
 170         /* Channel 0 active, PIO mode */
 171         NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000000);
 172         /* PUT and GET to 0 */
 173         NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
 174         NV_WRITE(NV_PFIFO_CACH1_DMAP, 0x00000000);
 175         /* No cmdbuf object */
 176         NV_WRITE(NV_PFIFO_CACH1_DMAI, 0x00000000);
 177         NV_WRITE(NV_PFIFO_CACH0_PSH0, 0x00000000);
 178         NV_WRITE(NV_PFIFO_CACH0_PUL0, 0x00000000);
 179         NV_WRITE(NV_PFIFO_SIZE, 0x0000FFFF);
 180         NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
 181         NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
 182         NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
 183         NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
 184         NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
 185 #ifdef __BIG_ENDIAN
 186         NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 187                                       NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 188                                       NV_PFIFO_CACH1_DMAF_MAX_REQS_4 |
 189                                       NV_PFIFO_CACH1_BIG_ENDIAN);
 190 #else
 191         NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 192                                       NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 193                                       NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
 194 #endif
 195         NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
 196         NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
 197         NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
 198         NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
 199
 200         NV_WRITE(NV_PGRAPH_CTX_USER, 0x0);
 201         NV_WRITE(NV_PFIFO_DELAY_0, 0xff /* retrycount*/ );
 202         if (dev_priv->card_type >= NV_40)
 203                 NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x00002001);
 204         else
 205                 NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10110000);
 206
 207         NV_WRITE(NV_PFIFO_DMA_TIMESLICE, 0x001fffff);
 208         NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
 209
 210         return 0;
 211 }
 212
 213 static int
 214 nouveau_fifo_cmdbuf_alloc(struct drm_device *dev, int channel)
 215 {
 216         drm_nouveau_private_t *dev_priv = dev->dev_private;
 217         struct nouveau_config *config = &dev_priv->config;
 218         struct mem_block *cb;
 219         struct nouveau_object *cb_dma = NULL;
 220         int cb_min_size = max(NV03_FIFO_SIZE,PAGE_SIZE);
 221
 222         /* Defaults for unconfigured values */
 223         if (!config->cmdbuf.location)
 224                 config->cmdbuf.location = NOUVEAU_MEM_FB;
 225         if (!config->cmdbuf.size || config->cmdbuf.size < cb_min_size)
 226                 config->cmdbuf.size = cb_min_size;
 227
 228         cb = nouveau_mem_alloc(dev, 0, config->cmdbuf.size,
 229                         config->cmdbuf.location | NOUVEAU_MEM_MAPPED,
 230                         (DRMFILE)-2);
 231         if (!cb) {
 232                 DRM_ERROR("Couldn't allocate DMA command buffer.\n");
 233                 return DRM_ERR(ENOMEM);
 234         }
 235
 236         if (cb->flags & NOUVEAU_MEM_AGP) {
 237                 cb_dma = nouveau_dma_object_create(dev,
 238                                 cb->start, cb->size,
 239                                 NV_DMA_ACCESS_RO, NV_DMA_TARGET_AGP);
 240         } else if (dev_priv->card_type != NV_04) {
 241                 cb_dma = nouveau_dma_object_create(dev,
 242                                 cb->start - drm_get_resource_start(dev, 1),
 243                                 cb->size,
 244                                 NV_DMA_ACCESS_RO, NV_DMA_TARGET_VIDMEM);
 245         } else {
 246                 /* NV04 cmdbuf hack, from original ddx.. not sure of it's
 247                  * exact reason for existing :)  PCI access to cmdbuf in
 248                  * VRAM.
 249                  */
 250                 cb_dma = nouveau_dma_object_create(dev,
 251                                 cb->start, cb->size,
 252                                 NV_DMA_ACCESS_RO, NV_DMA_TARGET_PCI);
 253         }
 254
 255         if (!cb_dma) {
 256                 nouveau_mem_free(dev, cb);
 257                 DRM_ERROR("Failed to alloc DMA object for command buffer\n");
 258                 return DRM_ERR(ENOMEM);
 259         }
 260
 261         dev_priv->fifos[channel].cmdbuf_mem = cb;
 262         dev_priv->fifos[channel].cmdbuf_obj = cb_dma;
 263         return 0;
 264 }
 265
 266 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV04_RAMFC_##offset, (val))
 267 static void nouveau_nv04_context_init(drm_device_t *dev,
 268                 drm_nouveau_fifo_alloc_t *init)
 269 {
 270         drm_nouveau_private_t *dev_priv = dev->dev_private;
 271         struct nouveau_object *cb_obj;
 272         uint32_t fifoctx, ctx_size = 32;
 273         int i;
 274
 275         cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
 276
 277         fifoctx=NV_RAMIN+dev_priv->ramfc_offset+init->channel*ctx_size;
 278
 279         // clear the fifo context
 280         for(i=0;i<ctx_size/4;i++)
 281                 NV_WRITE(fifoctx+4*i,0x0);
 282
 283         RAMFC_WR(DMA_PUT        , init->put_base);
 284         RAMFC_WR(DMA_GET        , init->put_base);
 285         RAMFC_WR(DMA_INSTANCE   , nouveau_chip_instance_get(dev, cb_obj->instance));
 286 #ifdef __BIG_ENDIAN
 287         RAMFC_WR(DMA_FETCH,     NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 288                                 NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 289                                 NV_PFIFO_CACH1_DMAF_MAX_REQS_4     |
 290                                 NV_PFIFO_CACH1_BIG_ENDIAN);
 291 #else
 292         RAMFC_WR(DMA_FETCH,     NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 293                                 NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 294                                 NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
 295 #endif
 296 }
 297 #undef RAMFC_WR
 298
 299 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV10_RAMFC_##offset, (val))
 300 static void nouveau_nv10_context_init(drm_device_t *dev,
 301                 drm_nouveau_fifo_alloc_t *init)
 302 {
 303         drm_nouveau_private_t *dev_priv = dev->dev_private;
 304         struct nouveau_object *cb_obj;
 305         uint32_t fifoctx;
 306         int i;
 307         cb_obj  = dev_priv->fifos[init->channel].cmdbuf_obj;
 308         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*64;
 309
 310         for (i=0;i<64;i+=4)
 311                 NV_WRITE(fifoctx + i, 0);
 312
 313         /* Fill entries that are seen filled in dumps of nvidia driver just
 314          * after channel's is put into DMA mode
 315          */
 316
 317         RAMFC_WR(DMA_PUT       , init->put_base);
 318         RAMFC_WR(DMA_GET       , init->put_base);
 319         RAMFC_WR(DMA_INSTANCE  , nouveau_chip_instance_get(dev,
 320                                 cb_obj->instance));
 321 #ifdef __BIG_ENDIAN
 322         RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 323                         NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 324                         NV_PFIFO_CACH1_DMAF_MAX_REQS_4     |
 325                         NV_PFIFO_CACH1_BIG_ENDIAN);
 326 #else
 327
 328         RAMFC_WR(DMA_FETCH, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES |
 329                         NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 330                         NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
 331 #endif
 332 }
 333
 334 static void nouveau_nv30_context_init(drm_device_t *dev,
 335                                       drm_nouveau_fifo_alloc_t *init)
 336 {
 337         drm_nouveau_private_t *dev_priv = dev->dev_private;
 338         struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
 339         struct nouveau_object *cb_obj;
 340         uint32_t fifoctx, grctx_inst, cb_inst, ctx_size = 64;
 341         int i;
 342
 343         cb_obj = dev_priv->fifos[init->channel].cmdbuf_obj;
 344         cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
 345         grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
 346         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel * ctx_size;
 347
 348         for (i = 0; i < ctx_size; i += 4)
 349                 NV_WRITE(fifoctx + i, 0);
 350
 351         RAMFC_WR(DMA_PUT,       init->put_base);
 352         RAMFC_WR(DMA_GET,       init->put_base);
 353         RAMFC_WR(REF_CNT,       NV_READ(NV_PFIFO_CACH1_REF_CNT));
 354         RAMFC_WR(DMA_INSTANCE,  cb_inst);
 355         RAMFC_WR(DMA_STATE,     NV_READ(NV_PFIFO_CACH1_DMAS));
 356         RAMFC_WR(DMA_FETCH,     NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
 357                                 NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 358                                 NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
 359 #ifdef __BIG_ENDIAN
 360                                 NV_PFIFO_CACH1_BIG_ENDIAN |
 361 #else
 362                                 0x00000000);
 363 #endif
 364
 365         RAMFC_WR(ENGINE,                NV_READ(NV_PFIFO_CACH1_ENG));
 366         RAMFC_WR(PULL1_ENGINE,          NV_READ(NV_PFIFO_CACH1_PUL1));
 367         RAMFC_WR(ACQUIRE_VALUE,         NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
 368         RAMFC_WR(ACQUIRE_TIMESTAMP,     NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
 369         RAMFC_WR(ACQUIRE_TIMEOUT,       NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
 370         RAMFC_WR(SEMAPHORE,             NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
 371         NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, grctx_inst); /* Misnomer.  Really a ptr to the grctx */
 372
 373         /*
 374          * TODO: We need to put this somewhere...
 375          */
 376         /* INSTANCE_WR(dev_priv->ctx_table, init->channel, grctx_inst); */
 377         RAMFC_WR(DMA_SUBROUTINE,        init->put_base);
 378 }
 379
 380 static void nouveau_nv10_context_save(drm_device_t *dev)
 381 {
 382         drm_nouveau_private_t *dev_priv = dev->dev_private;
 383         uint32_t fifoctx;
 384         int channel;
 385
 386         channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
 387         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*64;
 388
 389         RAMFC_WR(DMA_PUT          , NV_READ(NV_PFIFO_CACH1_DMAP));
 390         RAMFC_WR(DMA_GET          , NV_READ(NV_PFIFO_CACH1_DMAG));
 391         RAMFC_WR(REF_CNT          , NV_READ(NV_PFIFO_CACH1_REF_CNT));
 392         RAMFC_WR(DMA_INSTANCE     , NV_READ(NV_PFIFO_CACH1_DMAI));
 393         RAMFC_WR(DMA_STATE        , NV_READ(NV_PFIFO_CACH1_DMAS));
 394         RAMFC_WR(DMA_FETCH        , NV_READ(NV_PFIFO_CACH1_DMAF));
 395         RAMFC_WR(ENGINE           , NV_READ(NV_PFIFO_CACH1_ENG));
 396         RAMFC_WR(PULL1_ENGINE     , NV_READ(NV_PFIFO_CACH1_PUL1));
 397         RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
 398         RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
 399         RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
 400         RAMFC_WR(SEMAPHORE        , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
 401         RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV_PFIFO_CACH1_DMASR));
 402 }
 403 #undef RAMFC_WR
 404
 405 #define RAMFC_WR(offset, val) NV_WRITE(fifoctx + NV40_RAMFC_##offset, (val))
 406 static void nouveau_nv40_context_init(drm_device_t *dev,
 407                                       drm_nouveau_fifo_alloc_t *init)
 408 {
 409         drm_nouveau_private_t *dev_priv = dev->dev_private;
 410         struct nouveau_fifo *chan = &dev_priv->fifos[init->channel];
 411         uint32_t fifoctx, cb_inst, grctx_inst;
 412         int i;
 413
 414         cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
 415         grctx_inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
 416         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + init->channel*128;
 417         for (i=0;i<128;i+=4)
 418                 NV_WRITE(fifoctx + i, 0);
 419
 420         /* Fill entries that are seen filled in dumps of nvidia driver just
 421          * after channel's is put into DMA mode
 422          */
 423         RAMFC_WR(DMA_PUT       , init->put_base);
 424         RAMFC_WR(DMA_GET       , init->put_base);
 425         RAMFC_WR(DMA_INSTANCE  , cb_inst);
 426         RAMFC_WR(DMA_FETCH     , NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES |
 427                                  NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES |
 428                                  NV_PFIFO_CACH1_DMAF_MAX_REQS_8 |
 429 #ifdef __BIG_ENDIAN
 430                                  NV_PFIFO_CACH1_BIG_ENDIAN |
 431 #endif
 432                                  0x30000000 /* no idea.. */);
 433         RAMFC_WR(DMA_SUBROUTINE, init->put_base);
 434         RAMFC_WR(GRCTX_INSTANCE, grctx_inst);
 435         RAMFC_WR(DMA_TIMESLICE , 0x0001FFFF);
 436 }
 437
 438 static void nouveau_nv40_context_save(drm_device_t *dev)
 439 {
 440         drm_nouveau_private_t *dev_priv = dev->dev_private;
 441         uint32_t fifoctx;
 442         int channel;
 443
 444         channel = NV_READ(NV_PFIFO_CACH1_PSH1) & (nouveau_fifo_number(dev)-1);
 445         fifoctx = NV_RAMIN + dev_priv->ramfc_offset + channel*128;
 446
 447         RAMFC_WR(DMA_PUT          , NV_READ(NV_PFIFO_CACH1_DMAP));
 448         RAMFC_WR(DMA_GET          , NV_READ(NV_PFIFO_CACH1_DMAG));
 449         RAMFC_WR(REF_CNT          , NV_READ(NV_PFIFO_CACH1_REF_CNT));
 450         RAMFC_WR(DMA_INSTANCE     , NV_READ(NV_PFIFO_CACH1_DMAI));
 451         RAMFC_WR(DMA_DCOUNT       , NV_READ(NV_PFIFO_CACH1_DMA_DCOUNT));
 452         RAMFC_WR(DMA_STATE        , NV_READ(NV_PFIFO_CACH1_DMAS));
 453         RAMFC_WR(DMA_FETCH        , NV_READ(NV_PFIFO_CACH1_DMAF));
 454         RAMFC_WR(ENGINE           , NV_READ(NV_PFIFO_CACH1_ENG));
 455         RAMFC_WR(PULL1_ENGINE     , NV_READ(NV_PFIFO_CACH1_PUL1));
 456         RAMFC_WR(ACQUIRE_VALUE    , NV_READ(NV_PFIFO_CACH1_ACQUIRE_VALUE));
 457         RAMFC_WR(ACQUIRE_TIMESTAMP, NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP));
 458         RAMFC_WR(ACQUIRE_TIMEOUT  , NV_READ(NV_PFIFO_CACH1_ACQUIRE_TIMEOUT));
 459         RAMFC_WR(SEMAPHORE        , NV_READ(NV_PFIFO_CACH1_SEMAPHORE));
 460         RAMFC_WR(DMA_SUBROUTINE   , NV_READ(NV_PFIFO_CACH1_DMAG));
 461         RAMFC_WR(GRCTX_INSTANCE   , NV_READ(NV40_PFIFO_GRCTX_INSTANCE));
 462         RAMFC_WR(DMA_TIMESLICE    , NV_READ(NV_PFIFO_DMA_TIMESLICE) & 0x1FFFF);
 463         RAMFC_WR(UNK_40           , NV_READ(NV40_PFIFO_UNK32E4));
 464 }
 465 #undef RAMFC_WR
 466
 467 /* This function should load values from RAMFC into PFIFO, but for now
 468  * it just clobbers PFIFO with what nouveau_fifo_alloc used to setup
 469  * unconditionally.
 470  */
 471 static void
 472 nouveau_fifo_context_restore(drm_device_t *dev, int channel)
 473 {
 474         drm_nouveau_private_t *dev_priv = dev->dev_private;
 475         struct nouveau_fifo *chan = &dev_priv->fifos[channel];
 476         uint32_t cb_inst;
 477
 478         cb_inst = nouveau_chip_instance_get(dev, chan->cmdbuf_obj->instance);
 479
 480         // FIXME check if we need to refill the time quota with something like NV_WRITE(0x204C, 0x0003FFFF);
 481
 482         if (dev_priv->card_type >= NV_40)
 483                 NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00010000|channel);
 484         else
 485                 NV_WRITE(NV_PFIFO_CACH1_PSH1, 0x00000100|channel);
 486
 487         NV_WRITE(NV_PFIFO_CACH1_DMAP, 0 /*RAMFC_DMA_PUT*/);
 488         NV_WRITE(NV_PFIFO_CACH1_DMAG, 0 /*RAMFC_DMA_GET*/);
 489         NV_WRITE(NV_PFIFO_CACH1_DMAI, cb_inst);
 490         NV_WRITE(NV_PFIFO_SIZE , 0x0000FFFF);
 491         NV_WRITE(NV_PFIFO_CACH1_HASH, 0x0000FFFF);
 492
 493         NV_WRITE(NV_PFIFO_CACH0_PUL1, 0x00000001);
 494         NV_WRITE(NV_PFIFO_CACH1_DMAC, 0x00000000);
 495         NV_WRITE(NV_PFIFO_CACH1_DMAS, 0x00000000);
 496         NV_WRITE(NV_PFIFO_CACH1_ENG, 0x00000000);
 497 #ifdef __BIG_ENDIAN
 498                 NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4|NV_PFIFO_CACH1_BIG_ENDIAN);
 499 #else
 500                 NV_WRITE(NV_PFIFO_CACH1_DMAF, NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES|NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES|NV_PFIFO_CACH1_DMAF_MAX_REQS_4);
 501 #endif
 502 }
 503
 504 /* allocates and initializes a fifo for user space consumption */
 505 static int nouveau_fifo_alloc(drm_device_t* dev,drm_nouveau_fifo_alloc_t* init, DRMFILE filp)
 506 {
 507         int i;
 508         int ret;
 509         drm_nouveau_private_t *dev_priv = dev->dev_private;
 510         struct nouveau_object *cb_obj;
 511
 512         /*
 513          * Alright, here is the full story
 514          * Nvidia cards have multiple hw fifo contexts (praise them for that,
 515          * no complicated crash-prone context switches)
 516          * We allocate a new context for each app and let it write to it directly
 517          * (woo, full userspace command submission !)
 518          * When there are no more contexts, you lost
 519          */
 520         for(i=0;i<nouveau_fifo_number(dev);i++)
 521                 if (dev_priv->fifos[i].used==0)
 522                         break;
 523
 524         DRM_INFO("Allocating FIFO number %d\n", i);
 525         /* no more fifos. you lost. */
 526         if (i==nouveau_fifo_number(dev))
 527                 return DRM_ERR(EINVAL);
 528
 529         /* allocate a command buffer, and create a dma object for the gpu */
 530         ret = nouveau_fifo_cmdbuf_alloc(dev, i);
 531         if (ret) return ret;
 532         cb_obj = dev_priv->fifos[i].cmdbuf_obj;
 533
 534         /* that fifo is used */
 535         dev_priv->fifos[i].used=1;
 536         dev_priv->fifos[i].filp=filp;
 537
 538         init->channel  = i;
 539         init->put_base = 0;
 540         dev_priv->cur_fifo = init->channel;
 541
 542         nouveau_wait_for_idle(dev);
 543
 544         /* disable the fifo caches */
 545         NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
 546         NV_WRITE(NV_PFIFO_CACH1_DMAPSH, NV_READ(NV_PFIFO_CACH1_DMAPSH)&(~0x1));
 547         NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000000);
 548         NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
 549
 550         /* Construct inital RAMFC for new channel */
 551         if (dev_priv->card_type < NV_10) {
 552                 nouveau_nv04_context_init(dev, init);
 553         } else if (dev_priv->card_type < NV_20) {
 554                 nv10_graph_context_create(dev, init->channel);
 555                 nouveau_nv10_context_init(dev, init);
 556         } else if (dev_priv->card_type < NV_30) {
 557                 ret = nv20_graph_context_create(dev, init->channel);
 558                 if (ret) {
 559                         nouveau_fifo_free(dev, init->channel);
 560                         return ret;
 561                 }
 562                 nouveau_nv10_context_init(dev, init);
 563         } else if (dev_priv->card_type < NV_40) {
 564                 ret = nv30_graph_context_create(dev, init->channel);
 565                 if (ret) {
 566                         nouveau_fifo_free(dev, init->channel);
 567                         return ret;
 568                 }
 569                 nouveau_nv30_context_init(dev, init);
 570         } else {
 571                 ret = nv40_graph_context_create(dev, init->channel);
 572                 if (ret) {
 573                         nouveau_fifo_free(dev, init->channel);
 574                         return ret;
 575                 }
 576                 nouveau_nv40_context_init(dev, init);
 577         }
 578
 579         /* enable the fifo dma operation */
 580         NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)|(1<<init->channel));
 581
 582         /* setup channel's default get/put values */
 583         NV_WRITE(NV03_FIFO_REGS_DMAPUT(init->channel), init->put_base);
 584         NV_WRITE(NV03_FIFO_REGS_DMAGET(init->channel), init->put_base);
 585
 586         /* If this is the first channel, setup PFIFO ourselves.  For any
 587          * other case, the GPU will handle this when it switches contexts.
 588          */
 589         if (dev_priv->fifo_alloc_count == 0) {
 590                 nouveau_fifo_context_restore(dev, init->channel);
 591                 if (dev_priv->card_type >= NV_30) {
 592                         struct nouveau_fifo *chan;
 593                         uint32_t inst;
 594
 595                         chan = &dev_priv->fifos[init->channel];
 596                         inst = nouveau_chip_instance_get(dev,
 597                                                          chan->ramin_grctx);
 598
 599                         /* see comments in nv40_graph_context_restore() */
 600                         NV_WRITE(NV_PGRAPH_CHANNEL_CTX_SIZE, inst);
 601                         if (dev_priv->card_type >= NV_40) {
 602                                 NV_WRITE(0x40032C, inst | 0x01000000);
 603                                 NV_WRITE(NV40_PFIFO_GRCTX_INSTANCE, inst);
 604                         }
 605                 }
 606         }
 607
 608         NV_WRITE(NV_PFIFO_CACH1_DMAPSH, 0x00000001);
 609         NV_WRITE(NV_PFIFO_CACH1_PSH0, 0x00000001);
 610         NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
 611         NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
 612
 613         /* reenable the fifo caches */
 614         NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
 615
 616         /* make the fifo available to user space */
 617         /* first, the fifo control regs */
 618         init->ctrl      = dev_priv->mmio->offset + NV03_FIFO_REGS(init->channel);
 619         init->ctrl_size = NV03_FIFO_REGS_SIZE;
 620         ret = drm_addmap(dev, init->ctrl, init->ctrl_size, _DRM_REGISTERS,
 621                          0, &dev_priv->fifos[init->channel].regs);
 622         if (ret != 0)
 623                 return ret;
 624
 625         /* pass back FIFO map info to the caller */
 626         init->cmdbuf       = dev_priv->fifos[init->channel].cmdbuf_mem->start;
 627         init->cmdbuf_size  = dev_priv->fifos[init->channel].cmdbuf_mem->size;
 628
 629         /* FIFO has no objects yet */
 630         dev_priv->fifos[init->channel].objs = NULL;
 631         dev_priv->fifo_alloc_count++;
 632
 633         DRM_INFO("%s: initialised FIFO %d\n", __func__, init->channel);
 634         return 0;
 635 }
 636
 637 /* stops a fifo */
 638 void nouveau_fifo_free(drm_device_t* dev,int n)
 639 {
 640         drm_nouveau_private_t *dev_priv = dev->dev_private;
 641         int i;
 642         int ctx_size = nouveau_fifo_ctx_size(dev);
 643
 644         dev_priv->fifos[n].used=0;
 645         DRM_INFO("%s: freeing fifo %d\n", __func__, n);
 646
 647         /* disable the fifo caches */
 648         NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
 649
 650         NV_WRITE(NV_PFIFO_MODE,NV_READ(NV_PFIFO_MODE)&~(1<<n));
 651         // FIXME XXX needs more code
 652
 653         /* Clean RAMFC */
 654         for (i=0;i<ctx_size;i+=4) {
 655                 DRM_DEBUG("RAMFC +%02x: 0x%08x\n", i, NV_READ(NV_RAMIN +
 656                                         dev_priv->ramfc_offset + n*ctx_size + i));
 657                 NV_WRITE(NV_RAMIN + dev_priv->ramfc_offset + n*ctx_size + i, 0);
 658         }
 659
 660         if (dev_priv->card_type >= NV_40)
 661                 nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
 662         else if (dev_priv->card_type >= NV_30) {
 663         }
 664         else if (dev_priv->card_type >= NV_20) {
 665                 /* clear ctx table */
 666                 INSTANCE_WR(dev_priv->ctx_table, n, 0);
 667                 nouveau_instmem_free(dev, dev_priv->fifos[n].ramin_grctx);
 668         }
 669
 670         /* reenable the fifo caches */
 671         NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
 672
 673         /* Deallocate command buffer, and dma object */
 674         nouveau_mem_free(dev, dev_priv->fifos[n].cmdbuf_mem);
 675
 676         dev_priv->fifo_alloc_count--;
 677 }
 678
 679 /* cleanups all the fifos from filp */
 680 void nouveau_fifo_cleanup(drm_device_t* dev, DRMFILE filp)
 681 {
 682         int i;
 683         drm_nouveau_private_t *dev_priv = dev->dev_private;
 684
 685         DRM_DEBUG("clearing FIFO enables from filp\n");
 686         for(i=0;i<nouveau_fifo_number(dev);i++)
 687                 if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp==filp)
 688                         nouveau_fifo_free(dev,i);
 689
 690         /* check we still point at an active channel */
 691         if (dev_priv->fifos[dev_priv->cur_fifo].used == 0) {
 692                 DRM_DEBUG("%s: cur_fifo is no longer owned.\n", __func__);
 693                 for (i=0;i<nouveau_fifo_number(dev);i++)
 694                         if (dev_priv->fifos[i].used) break;
 695                 if (i==nouveau_fifo_number(dev))
 696                         i=0;
 697                 DRM_DEBUG("%s: new cur_fifo is %d\n", __func__, i);
 698                 dev_priv->cur_fifo = i;
 699         }
 700
 701 /*      if (dev_priv->cmdbuf_alloc)
 702                 nouveau_fifo_init(dev);*/
 703 }
 704
 705 int nouveau_fifo_id_get(drm_device_t* dev, DRMFILE filp)
 706 {
 707         drm_nouveau_private_t *dev_priv=dev->dev_private;
 708         int i;
 709
 710         for(i=0;i<nouveau_fifo_number(dev);i++)
 711                 if (dev_priv->fifos[i].used && dev_priv->fifos[i].filp == filp)
 712                         return i;
 713         return -1;
 714 }
 715
 716 /***********************************
 717  * ioctls wrapping the functions
 718  ***********************************/
 719
 720 static int nouveau_ioctl_fifo_alloc(DRM_IOCTL_ARGS)
 721 {
 722         DRM_DEVICE;
 723         drm_nouveau_fifo_alloc_t init;
 724         int res;
 725         DRM_COPY_FROM_USER_IOCTL(init, (drm_nouveau_fifo_alloc_t __user *) data, sizeof(init));
 726
 727         res=nouveau_fifo_alloc(dev,&init,filp);
 728         if (!res)
 729                 DRM_COPY_TO_USER_IOCTL((drm_nouveau_fifo_alloc_t __user *)data, init, sizeof(init));
 730
 731         return res;
 732 }
 733
 734 /***********************************
 735  * finally, the ioctl table
 736  ***********************************/
 737
 738 drm_ioctl_desc_t nouveau_ioctls[] = {
 739         [DRM_IOCTL_NR(DRM_NOUVEAU_FIFO_ALLOC)] = {nouveau_ioctl_fifo_alloc, DRM_AUTH},
 740         [DRM_IOCTL_NR(DRM_NOUVEAU_OBJECT_INIT)] = {nouveau_ioctl_object_init, DRM_AUTH},
 741         [DRM_IOCTL_NR(DRM_NOUVEAU_DMA_OBJECT_INIT)] = {nouveau_ioctl_dma_object_init, DRM_AUTH},
 742         [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_ALLOC)] = {nouveau_ioctl_mem_alloc, DRM_AUTH},
 743         [DRM_IOCTL_NR(DRM_NOUVEAU_MEM_FREE)] = {nouveau_ioctl_mem_free, DRM_AUTH},
 744         [DRM_IOCTL_NR(DRM_NOUVEAU_GETPARAM)] = {nouveau_ioctl_getparam, DRM_AUTH},
 745         [DRM_IOCTL_NR(DRM_NOUVEAU_SETPARAM)] = {nouveau_ioctl_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
 746 };
 747
 748 int nouveau_max_ioctl = DRM_ARRAY_SIZE(nouveau_ioctls);
 749
 750