shared-core/nouveau_irq.c

   1 /*
   2  * Copyright (C) 2006 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Ben Skeggs <darktama@iinet.net.au>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "nouveau_drm.h"
  36 #include "nouveau_drv.h"
  37 #include "nouveau_reg.h"
  38 #include "nouveau_swmthd.h"
  39
  40 void
  41 nouveau_irq_preinstall(struct drm_device *dev)
  42 {
  43         struct drm_nouveau_private *dev_priv = dev->dev_private;
  44
  45         /* Master disable */
  46         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
  47 }
  48
  49 int
  50 nouveau_irq_postinstall(struct drm_device *dev)
  51 {
  52         struct drm_nouveau_private *dev_priv = dev->dev_private;
  53
  54         /* Master enable */
  55         NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
  56
  57         return 0;
  58 }
  59
  60 void
  61 nouveau_irq_uninstall(struct drm_device *dev)
  62 {
  63         struct drm_nouveau_private *dev_priv = dev->dev_private;
  64
  65         /* Master disable */
  66         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
  67 }
  68
  69 static void
  70 nouveau_fifo_irq_handler(struct drm_device *dev)
  71 {
  72         struct drm_nouveau_private *dev_priv = dev->dev_private;
  73         struct nouveau_engine *engine = &dev_priv->Engine;
  74         uint32_t status, reassign;
  75
  76         reassign = NV_READ(NV03_PFIFO_CACHES) & 1;
  77         while ((status = NV_READ(NV03_PFIFO_INTR_0))) {
  78                 uint32_t chid, get;
  79
  80                 NV_WRITE(NV03_PFIFO_CACHES, 0);
  81
  82                 chid = engine->fifo.channel_id(dev);
  83                 get  = NV_READ(NV03_PFIFO_CACHE1_GET);
  84
  85                 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
  86                         uint32_t mthd, data;
  87                         int ptr;
  88
  89                         ptr = get >> 2;
  90                         if (dev_priv->card_type < NV_40) {
  91                                 mthd = NV_READ(NV04_PFIFO_CACHE1_METHOD(ptr));
  92                                 data = NV_READ(NV04_PFIFO_CACHE1_DATA(ptr));
  93                         } else {
  94                                 mthd = NV_READ(NV40_PFIFO_CACHE1_METHOD(ptr));
  95                                 data = NV_READ(NV40_PFIFO_CACHE1_DATA(ptr));
  96                         }
  97
  98                         DRM_INFO("PFIFO_CACHE_ERROR - "
  99                                  "Ch %d/%d Mthd 0x%04x Data 0x%08x\n",
 100                                  chid, (mthd >> 13) & 7, mthd & 0x1ffc, data);
 101
 102                         NV_WRITE(NV03_PFIFO_CACHE1_GET, get + 4);
 103                         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 1);
 104
 105                         status &= ~NV_PFIFO_INTR_CACHE_ERROR;
 106                         NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
 107                 }
 108
 109                 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 110                         DRM_INFO("PFIFO_DMA_PUSHER - Ch %d\n", chid);
 111
 112                         status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 113                         NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
 114
 115                         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
 116                         if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT) != get)
 117                                 NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, get + 4);
 118                 }
 119
 120                 if (status) {
 121                         DRM_INFO("Unhandled PFIFO_INTR - 0x%08x\n", status);
 122                         NV_WRITE(NV03_PFIFO_INTR_0, status);
 123                         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
 124                 }
 125
 126                 NV_WRITE(NV03_PFIFO_CACHES, reassign);
 127         }
 128
 129         NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
 130 }
 131
 132 struct nouveau_bitfield_names {
 133         uint32_t mask;
 134         const char * name;
 135 };
 136
 137 static struct nouveau_bitfield_names nouveau_nstatus_names[] =
 138 {
 139         { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 140         { NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 141         { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 142         { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
 143 };
 144
 145 static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] =
 146 {
 147         { NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 148         { NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 149         { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 150         { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
 151 };
 152
 153 static struct nouveau_bitfield_names nouveau_nsource_names[] =
 154 {
 155         { NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
 156         { NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
 157         { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
 158         { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
 159         { NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
 160         { NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
 161         { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
 162         { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
 163         { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
 164         { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
 165         { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
 166         { NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
 167         { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
 168         { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
 169         { NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
 170         { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
 171         { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
 172         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
 173         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
 174 };
 175
 176 static void
 177 nouveau_print_bitfield_names(uint32_t value,
 178                              const struct nouveau_bitfield_names *namelist,
 179                              const int namelist_len)
 180 {
 181         int i;
 182         for(i=0; i<namelist_len; ++i) {
 183                 uint32_t mask = namelist[i].mask;
 184                 if(value & mask) {
 185                         printk(" %s", namelist[i].name);
 186                         value &= ~mask;
 187                 }
 188         }
 189         if(value)
 190                 printk(" (unknown bits 0x%08x)", value);
 191 }
 192
 193 static int
 194 nouveau_graph_chid_from_grctx(struct drm_device *dev)
 195 {
 196         struct drm_nouveau_private *dev_priv = dev->dev_private;
 197         uint32_t inst;
 198         int i;
 199
 200         if (dev_priv->card_type < NV_40)
 201                 return dev_priv->Engine.fifo.channels;
 202         else
 203         if (dev_priv->card_type < NV_50)
 204                 inst = (NV_READ(0x40032c) & 0xfffff) << 4;
 205         else
 206                 inst = NV_READ(0x40032c) & 0xfffff;
 207
 208         for (i = 0; i < dev_priv->Engine.fifo.channels; i++) {
 209                 struct nouveau_channel *chan = dev_priv->fifos[i];
 210
 211                 if (!chan || !chan->ramin_grctx)
 212                         continue;
 213
 214                 if (dev_priv->card_type < NV_50) {
 215                         if (inst == chan->ramin_grctx->instance)
 216                                 break;
 217                 } else {
 218                         if (inst == INSTANCE_RD(chan->ramin_grctx->gpuobj, 0))
 219                                 break;
 220                 }
 221         }
 222
 223         return i;
 224 }
 225
 226 static int
 227 nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
 228 {
 229         struct drm_nouveau_private *dev_priv = dev->dev_private;
 230         struct nouveau_engine *engine = &dev_priv->Engine;
 231         int channel;
 232
 233         if (dev_priv->card_type < NV_10)
 234                 channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
 235         else
 236         if (dev_priv->card_type < NV_40)
 237                 channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
 238         else
 239                 channel = nouveau_graph_chid_from_grctx(dev);
 240
 241         if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) {
 242                 DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
 243                 return -EINVAL;
 244         }
 245
 246         *channel_ret = channel;
 247         return 0;
 248 }
 249
 250 struct nouveau_pgraph_trap {
 251         int channel;
 252         int class;
 253         int subc, mthd, size;
 254         uint32_t data, data2;
 255         uint32_t nsource, nstatus;
 256 };
 257
 258 static void
 259 nouveau_graph_trap_info(struct drm_device *dev,
 260                         struct nouveau_pgraph_trap *trap)
 261 {
 262         struct drm_nouveau_private *dev_priv = dev->dev_private;
 263         uint32_t address;
 264
 265         trap->nsource = trap->nstatus = 0;
 266         if (dev_priv->card_type < NV_50) {
 267                 trap->nsource = NV_READ(NV03_PGRAPH_NSOURCE);
 268                 trap->nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
 269         }
 270
 271         if (nouveau_graph_trapped_channel(dev, &trap->channel))
 272                 trap->channel = -1;
 273         address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
 274
 275         trap->mthd = address & 0x1FFC;
 276         trap->data = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
 277         if (dev_priv->card_type < NV_10) {
 278                 trap->subc  = (address >> 13) & 0x7;
 279         } else {
 280                 trap->subc  = (address >> 16) & 0x7;
 281                 trap->data2 = NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
 282         }
 283
 284         if (dev_priv->card_type < NV_10) {
 285                 trap->class = NV_READ(0x400180 + trap->subc*4) & 0xFF;
 286         } else if (dev_priv->card_type < NV_40) {
 287                 trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFF;
 288         } else if (dev_priv->card_type < NV_50) {
 289                 trap->class = NV_READ(0x400160 + trap->subc*4) & 0xFFFF;
 290         } else {
 291                 trap->class = NV_READ(0x400814);
 292         }
 293 }
 294
 295 static void
 296 nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
 297                              struct nouveau_pgraph_trap *trap)
 298 {
 299         struct drm_nouveau_private *dev_priv = dev->dev_private;
 300         uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
 301
 302         DRM_INFO("%s - nSource:", id);
 303         nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
 304                                      ARRAY_SIZE(nouveau_nsource_names));
 305         printk(", nStatus:");
 306         if (dev_priv->card_type < NV_10)
 307                 nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
 308                                      ARRAY_SIZE(nouveau_nstatus_names));
 309         else
 310                 nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10,
 311                                      ARRAY_SIZE(nouveau_nstatus_names_nv10));
 312         printk("\n");
 313
 314         DRM_INFO("%s - Ch %d/%d Class 0x%04x Mthd 0x%04x Data 0x%08x:0x%08x\n",
 315                  id, trap->channel, trap->subc, trap->class, trap->mthd,
 316                  trap->data2, trap->data);
 317 }
 318
 319 static inline void
 320 nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
 321 {
 322         struct nouveau_pgraph_trap trap;
 323         int unhandled = 0;
 324
 325         nouveau_graph_trap_info(dev, &trap);
 326
 327         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 328                 /* NV4 (nvidia TNT 1) reports software methods with
 329                  * PGRAPH NOTIFY ILLEGAL_MTHD
 330                  */
 331                 DRM_DEBUG("Got NV04 software method method %x for class %#x\n",
 332                           trap.mthd, trap.class);
 333
 334                 if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) {
 335                         DRM_ERROR("Unable to execute NV04 software method %x "
 336                                   "for object class %x. Please report.\n",
 337                                   trap.mthd, trap.class);
 338                         unhandled = 1;
 339                 }
 340         } else {
 341                 unhandled = 1;
 342         }
 343
 344         if (unhandled)
 345                 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
 346 }
 347
 348 static inline void
 349 nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
 350 {
 351         struct nouveau_pgraph_trap trap;
 352         int unhandled = 0;
 353
 354         nouveau_graph_trap_info(dev, &trap);
 355         trap.nsource = nsource;
 356
 357         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 358                 if (trap.channel >= 0 && trap.mthd == 0x0150) {
 359                         nouveau_fence_handler(dev, trap.channel);
 360                 } else
 361                 if (nouveau_sw_method_execute(dev, trap.class, trap.mthd)) {
 362                         unhandled = 1;
 363                 }
 364         } else {
 365                 unhandled = 1;
 366         }
 367
 368         if (unhandled)
 369                 nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
 370 }
 371
 372 static inline void
 373 nouveau_pgraph_intr_context_switch(struct drm_device *dev)
 374 {
 375         struct drm_nouveau_private *dev_priv = dev->dev_private;
 376         struct nouveau_engine *engine = &dev_priv->Engine;
 377         uint32_t chid;
 378
 379         chid = engine->fifo.channel_id(dev);
 380         DRM_DEBUG("PGRAPH context switch interrupt channel %x\n", chid);
 381
 382         switch(dev_priv->card_type) {
 383         case NV_04:
 384         case NV_05:
 385                 nouveau_nv04_context_switch(dev);
 386                 break;
 387         case NV_10:
 388         case NV_11:
 389         case NV_17:
 390                 nouveau_nv10_context_switch(dev);
 391                 break;
 392         default:
 393                 DRM_ERROR("Context switch not implemented\n");
 394                 break;
 395         }
 396 }
 397
 398 static void
 399 nouveau_pgraph_irq_handler(struct drm_device *dev)
 400 {
 401         struct drm_nouveau_private *dev_priv = dev->dev_private;
 402         uint32_t status;
 403
 404         while ((status = NV_READ(NV03_PGRAPH_INTR))) {
 405                 uint32_t nsource = NV_READ(NV03_PGRAPH_NSOURCE);
 406
 407                 if (status & NV_PGRAPH_INTR_NOTIFY) {
 408                         nouveau_pgraph_intr_notify(dev, nsource);
 409
 410                         status &= ~NV_PGRAPH_INTR_NOTIFY;
 411                         NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
 412                 }
 413
 414                 if (status & NV_PGRAPH_INTR_ERROR) {
 415                         nouveau_pgraph_intr_error(dev, nsource);
 416
 417                         status &= ~NV_PGRAPH_INTR_ERROR;
 418                         NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
 419                 }
 420
 421                 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
 422                         nouveau_pgraph_intr_context_switch(dev);
 423
 424                         status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
 425                         NV_WRITE(NV03_PGRAPH_INTR,
 426                                  NV_PGRAPH_INTR_CONTEXT_SWITCH);
 427                 }
 428
 429                 if (status) {
 430                         DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
 431                         NV_WRITE(NV03_PGRAPH_INTR, status);
 432                 }
 433
 434                 if ((NV_READ(NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
 435                         NV_WRITE(NV04_PGRAPH_FIFO, 1);
 436         }
 437
 438         NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 439 }
 440
 441 static void
 442 nv50_pgraph_irq_handler(struct drm_device *dev)
 443 {
 444         struct drm_nouveau_private *dev_priv = dev->dev_private;
 445         uint32_t status;
 446
 447         status = NV_READ(NV03_PGRAPH_INTR);
 448
 449         if (status & 0x00000020) {
 450                 nouveau_pgraph_intr_error(dev,
 451                                           NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD);
 452
 453                 status &= ~0x00000020;
 454                 NV_WRITE(NV03_PGRAPH_INTR, 0x00000020);
 455         }
 456
 457         if (status & 0x00100000) {
 458                 nouveau_pgraph_intr_error(dev,
 459                                           NV03_PGRAPH_NSOURCE_DATA_ERROR);
 460
 461                 status &= ~0x00100000;
 462                 NV_WRITE(NV03_PGRAPH_INTR, 0x00100000);
 463         }
 464
 465         if (status & 0x00200000) {
 466                 nouveau_pgraph_intr_error(dev,
 467                                           NV03_PGRAPH_NSOURCE_PROTECTION_ERROR);
 468
 469                 status &= ~0x00200000;
 470                 NV_WRITE(NV03_PGRAPH_INTR, 0x00200000);
 471         }
 472
 473         if (status) {
 474                 DRM_INFO("Unhandled PGRAPH_INTR - 0x%08x\n", status);
 475                 NV_WRITE(NV03_PGRAPH_INTR, status);
 476         }
 477
 478         if ((NV_READ(0x400500) & (1 << 16)) == 0)
 479                 NV_WRITE(0x400500, NV_READ(0x400500) | (1 << 16));
 480
 481         NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 482 }
 483
 484 static void
 485 nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
 486 {
 487         struct drm_nouveau_private *dev_priv = dev->dev_private;
 488
 489         if (crtc&1) {
 490                 NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
 491         }
 492
 493         if (crtc&2) {
 494                 NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
 495         }
 496 }
 497
 498 static void
 499 nouveau_nv50_display_irq_handler(struct drm_device *dev)
 500 {
 501         struct drm_nouveau_private *dev_priv = dev->dev_private;
 502         uint32_t val = NV_READ(NV50_DISPLAY_SUPERVISOR);
 503
 504         DRM_INFO("NV50_DISPLAY_INTR - 0x%08X\n", val);
 505
 506         NV_WRITE(NV50_DISPLAY_SUPERVISOR, val);
 507 }
 508
 509 static void
 510 nouveau_nv50_i2c_irq_handler(struct drm_device *dev)
 511 {
 512         struct drm_nouveau_private *dev_priv = dev->dev_private;
 513
 514         DRM_INFO("NV50_I2C_INTR - 0x%08X\n", NV_READ(NV50_I2C_CONTROLLER));
 515
 516         /* This seems to be the way to acknowledge an interrupt. */
 517         NV_WRITE(NV50_I2C_CONTROLLER, 0x7FFF7FFF);
 518 }
 519
 520 irqreturn_t
 521 nouveau_irq_handler(DRM_IRQ_ARGS)
 522 {
 523         struct drm_device *dev = (struct drm_device*)arg;
 524         struct drm_nouveau_private *dev_priv = dev->dev_private;
 525         uint32_t status;
 526
 527         status = NV_READ(NV03_PMC_INTR_0);
 528         if (!status)
 529                 return IRQ_NONE;
 530
 531         if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
 532                 nouveau_fifo_irq_handler(dev);
 533                 status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
 534         }
 535
 536         if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
 537                 if (dev_priv->card_type >= NV_50)
 538                         nv50_pgraph_irq_handler(dev);
 539                 else
 540                         nouveau_pgraph_irq_handler(dev);
 541
 542                 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
 543         }
 544
 545         if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
 546                 nouveau_crtc_irq_handler(dev, (status>>24)&3);
 547                 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
 548         }
 549
 550         if (status & NV_PMC_INTR_0_NV50_DISPLAY_PENDING) {
 551                 nouveau_nv50_display_irq_handler(dev);
 552                 status &= ~NV_PMC_INTR_0_NV50_DISPLAY_PENDING;
 553         }
 554
 555         if (status & NV_PMC_INTR_0_NV50_I2C_PENDING) {
 556                 nouveau_nv50_i2c_irq_handler(dev);
 557                 status &= ~NV_PMC_INTR_0_NV50_I2C_PENDING;
 558         }
 559
 560         if (status)
 561                 DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
 562
 563         return IRQ_HANDLED;
 564 }