shared-core/nouveau_irq.c

   1 /*
   2  * Copyright (C) 2006 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Ben Skeggs <darktama@iinet.net.au>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "nouveau_drm.h"
  36 #include "nouveau_drv.h"
  37 #include "nouveau_reg.h"
  38
  39 void nouveau_irq_preinstall(drm_device_t *dev)
  40 {
  41         drm_nouveau_private_t *dev_priv = dev->dev_private;
  42
  43         DRM_DEBUG("IRQ: preinst\n");
  44
  45         /* Disable/Clear PFIFO interrupts */
  46         NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
  47         NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
  48         /* Disable/Clear PGRAPH interrupts */
  49         if (dev_priv->card_type<NV_40)
  50                 NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
  51         else
  52                 NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
  53         NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
  54 #if 0
  55         /* Disable/Clear CRTC0/1 interrupts */
  56         NV_WRITE(NV_CRTC0_INTEN, 0);
  57         NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
  58         NV_WRITE(NV_CRTC1_INTEN, 0);
  59         NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
  60 #endif
  61         /* Master disable */
  62         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
  63 }
  64
  65 void nouveau_irq_postinstall(drm_device_t *dev)
  66 {
  67         drm_nouveau_private_t *dev_priv = dev->dev_private;
  68
  69         DRM_DEBUG("IRQ: postinst\n");
  70
  71         /* Enable PFIFO error reporting */
  72         NV_WRITE(NV03_PFIFO_INTR_EN_0 ,
  73                         NV_PFIFO_INTR_CACHE_ERROR |
  74                         NV_PFIFO_INTR_RUNOUT |
  75                         NV_PFIFO_INTR_RUNOUT_OVERFLOW |
  76                         NV_PFIFO_INTR_DMA_PUSHER |
  77                         NV_PFIFO_INTR_DMA_PT |
  78                         NV_PFIFO_INTR_SEMAPHORE |
  79                         NV_PFIFO_INTR_ACQUIRE_TIMEOUT
  80                         );
  81         NV_WRITE(NV03_PMC_INTR_0, 0xFFFFFFFF);
  82
  83         /* Enable PGRAPH interrupts */
  84         if (dev_priv->card_type<NV_40)
  85                 NV_WRITE(NV03_PGRAPH_INTR_EN,
  86                                 NV_PGRAPH_INTR_NOTIFY |
  87                                 NV_PGRAPH_INTR_MISSING_HW |
  88                                 NV_PGRAPH_INTR_CONTEXT_SWITCH |
  89                                 NV_PGRAPH_INTR_BUFFER_NOTIFY |
  90                                 NV_PGRAPH_INTR_ERROR
  91                                 );
  92         else
  93                 NV_WRITE(NV40_PGRAPH_INTR_EN,
  94                                 NV_PGRAPH_INTR_NOTIFY |
  95                                 NV_PGRAPH_INTR_MISSING_HW |
  96                                 NV_PGRAPH_INTR_CONTEXT_SWITCH |
  97                                 NV_PGRAPH_INTR_BUFFER_NOTIFY |
  98                                 NV_PGRAPH_INTR_ERROR
  99                                 );
 100         NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
 101
 102 #if 0
 103         /* Enable CRTC0/1 interrupts */
 104         NV_WRITE(NV_CRTC0_INTEN, NV_CRTC_INTR_VBLANK);
 105         NV_WRITE(NV_CRTC1_INTEN, NV_CRTC_INTR_VBLANK);
 106 #endif
 107
 108         /* Master enable */
 109         NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
 110 }
 111
 112 void nouveau_irq_uninstall(drm_device_t *dev)
 113 {
 114         drm_nouveau_private_t *dev_priv = dev->dev_private;
 115
 116         DRM_DEBUG("IRQ: uninst\n");
 117
 118         /* Disable PFIFO interrupts */
 119         NV_WRITE(NV03_PFIFO_INTR_EN_0, 0);
 120         /* Disable PGRAPH interrupts */
 121         if (dev_priv->card_type<NV_40)
 122                 NV_WRITE(NV03_PGRAPH_INTR_EN, 0);
 123         else
 124                 NV_WRITE(NV40_PGRAPH_INTR_EN, 0);
 125 #if 0
 126         /* Disable CRTC0/1 interrupts */
 127         NV_WRITE(NV_CRTC0_INTEN, 0);
 128         NV_WRITE(NV_CRTC1_INTEN, 0);
 129 #endif
 130         /* Master disable */
 131         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
 132 }
 133
 134 static void nouveau_fifo_irq_handler(drm_device_t *dev)
 135 {
 136         uint32_t status, chmode, chstat, channel;
 137         drm_nouveau_private_t *dev_priv = dev->dev_private;
 138
 139         status = NV_READ(NV03_PMC_INTR_0);
 140         if (!status)
 141                 return;
 142         chmode = NV_READ(NV04_PFIFO_MODE);
 143         chstat = NV_READ(NV04_PFIFO_DMA);
 144         channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 145
 146         DRM_DEBUG("NV: PFIFO interrupt! Channel=%d, INTSTAT=0x%08x/MODE=0x%08x/PEND=0x%08x\n", channel, status, chmode, chstat);
 147
 148         if (status & NV_PFIFO_INTR_CACHE_ERROR) {
 149                 uint32_t c1get, c1method, c1data;
 150
 151                 DRM_ERROR("NV: PFIFO error interrupt\n");
 152
 153                 c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
 154                 if (dev_priv->card_type < NV_40) {
 155                         /* Untested, so it may not work.. */
 156                         c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get));
 157                         c1data   = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get));
 158                 } else {
 159                         c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get));
 160                         c1data   = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
 161                 }
 162
 163                 DRM_ERROR("NV: Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
 164                                 channel, (c1method >> 13) & 7,
 165                                 c1method & 0x1ffc, c1data
 166                          );
 167
 168                 status &= ~NV_PFIFO_INTR_CACHE_ERROR;
 169                 NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
 170         }
 171
 172         if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 173                 DRM_INFO("NV: PFIFO DMA pusher interrupt\n");
 174
 175                 status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 176                 NV_WRITE(NV03_PMC_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
 177
 178                 NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
 179                 if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET))
 180                 {
 181                         uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4;
 182                         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval);
 183                 }
 184         }
 185
 186         if (status) {
 187                 DRM_INFO("NV: unknown PFIFO interrupt. status=0x%08x\n", status);
 188
 189                 NV_WRITE(NV03_PMC_INTR_0, status);
 190         }
 191
 192         NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
 193 }
 194
 195 #if 0
 196 static void nouveau_nv04_context_switch(drm_device_t *dev)
 197 {
 198         drm_nouveau_private_t *dev_priv = dev->dev_private;
 199         uint32_t channel,i;
 200         uint32_t max=0;
 201         NV_WRITE(NV04_PGRAPH_FIFO,0x0);
 202         channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 203         //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1));
 204         //DRM_INFO("currently on channel %d\n",channel);
 205         for (i=0;i<nouveau_fifo_number(dev);i++)
 206                 if ((dev_priv->fifos[i].used)&&(i!=channel)) {
 207                         uint32_t put,get,pending;
 208                         //put=NV_READ(dev_priv->ramfc_offset+i*32);
 209                         //get=NV_READ(dev_priv->ramfc_offset+4+i*32);
 210                         put=NV_READ(NV03_FIFO_REGS_DMAPUT(i));
 211                         get=NV_READ(NV03_FIFO_REGS_DMAGET(i));
 212                         pending=NV_READ(NV04_PFIFO_DMA);
 213                         //DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get);
 214                         /* mark all pending channels as such */
 215                         if ((put!=get)&!(pending&(1<<i)))
 216                         {
 217                                 pending|=(1<<i);
 218                                 NV_WRITE(NV04_PFIFO_DMA,pending);
 219                         }
 220                         max++;
 221                 }
 222         nouveau_wait_for_idle(dev);
 223
 224 #if 1
 225         /* 2-channel commute */
 226         //              NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100);
 227         if (channel==0)
 228                 channel=1;
 229         else
 230                 channel=0;
 231         //              dev_priv->cur_fifo=channel;
 232         NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100);
 233 #endif
 234         //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100);
 235         //NV_WRITE(0x2050,max|0x100);
 236
 237         NV_WRITE(NV04_PGRAPH_FIFO,0x1);
 238
 239 }
 240 #endif
 241
 242 static void nouveau_pgraph_irq_handler(drm_device_t *dev)
 243 {
 244         uint32_t status;
 245         drm_nouveau_private_t *dev_priv = dev->dev_private;
 246
 247         status = NV_READ(NV03_PGRAPH_INTR);
 248         if (!status)
 249                 return;
 250
 251         if (status & NV_PGRAPH_INTR_NOTIFY) {
 252                 uint32_t nsource, nstatus, instance, notify;
 253                 DRM_DEBUG("NV: PGRAPH notify interrupt\n");
 254
 255                 nstatus = NV_READ(0x00400104);
 256                 nsource = NV_READ(0x00400108);
 257                 DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
 258
 259                 instance = NV_READ(0x00400158);
 260                 notify   = NV_READ(0x00400150) >> 16;
 261                 DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", nsource, nstatus);
 262
 263                 status &= ~NV_PGRAPH_INTR_NOTIFY;
 264                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
 265         }
 266
 267         if (status & NV_PGRAPH_INTR_BUFFER_NOTIFY) {
 268                 uint32_t nsource, nstatus, instance, notify;
 269                 DRM_DEBUG("NV: PGRAPH buffer notify interrupt\n");
 270
 271                 nstatus = NV_READ(0x00400104);
 272                 nsource = NV_READ(0x00400108);
 273                 DRM_DEBUG("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
 274
 275                 instance = NV_READ(0x00400158);
 276                 notify   = NV_READ(0x00400150) >> 16;
 277                 DRM_DEBUG("instance:0x%08x\tnotify:0x%08x\n", instance, notify);
 278
 279                 status &= ~NV_PGRAPH_INTR_BUFFER_NOTIFY;
 280                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_BUFFER_NOTIFY);
 281         }
 282
 283         if (status & NV_PGRAPH_INTR_MISSING_HW) {
 284                 DRM_ERROR("NV: PGRAPH missing hw interrupt\n");
 285
 286                 status &= ~NV_PGRAPH_INTR_MISSING_HW;
 287                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_MISSING_HW);
 288         }
 289
 290         if (status & NV_PGRAPH_INTR_ERROR) {
 291                 uint32_t nsource, nstatus, instance;
 292                 uint32_t address;
 293                 uint32_t channel;
 294                 uint32_t method, subc, data;
 295
 296                 DRM_ERROR("NV: PGRAPH error interrupt\n");
 297
 298                 nstatus = NV_READ(0x00400104);
 299                 nsource = NV_READ(0x00400108);
 300                 DRM_ERROR("nsource:0x%08x\tnstatus:0x%08x\n", nsource, nstatus);
 301
 302                 instance = NV_READ(0x00400158);
 303                 DRM_ERROR("instance:0x%08x\n", instance);
 304
 305                 address = NV_READ(0x400704);
 306                 data    = NV_READ(0x400708);
 307                 channel = (address >> 20) & 0x1F;
 308                 subc    = (address >> 16) & 0x7;
 309                 method  = address & 0x1FFC;
 310                 DRM_DEBUG("NV: 0x400704 = 0x%08x\n", address);
 311                 DRM_ERROR("NV: Channel %d/%d (class 0x%04x) -"
 312                           "Method 0x%04x, Data 0x%08x\n",
 313                                 channel, subc,
 314                                 NV_READ(0x400160+subc*4) & 0xFFFF,
 315                                 method, data
 316                          );
 317
 318                 status &= ~NV_PGRAPH_INTR_ERROR;
 319                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
 320         }
 321
 322         if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
 323                 uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 324                 DRM_INFO("NV: PGRAPH context switch interrupt channel %x\n",channel);
 325                 switch(dev_priv->card_type)
 326                 {
 327                         case NV_04:
 328                         case NV_05:
 329                                 nouveau_nv04_context_switch(dev);
 330                                 break;
 331                         case NV_10:
 332                                 nouveau_nv10_context_switch(dev);
 333                                 break;
 334                         case NV_20:
 335                         case NV_30:
 336                                 nouveau_nv20_context_switch(dev);
 337                                 break;
 338                         default:
 339                                 DRM_INFO("NV: Context switch not implemented\n");
 340                                 break;
 341                 }
 342
 343                 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
 344                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
 345         }
 346
 347         if (status) {
 348                 DRM_INFO("NV: Unknown PGRAPH interrupt! STAT=0x%08x\n", status);
 349                 NV_WRITE(NV03_PGRAPH_INTR, status);
 350         }
 351
 352         NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 353 }
 354
 355 static void nouveau_crtc_irq_handler(drm_device_t *dev, int crtc)
 356 {
 357         drm_nouveau_private_t *dev_priv = dev->dev_private;
 358         if (crtc&1) {
 359                 NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
 360         }
 361
 362         if (crtc&2) {
 363                 NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
 364         }
 365 }
 366
 367 irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS)
 368 {
 369         drm_device_t          *dev = (drm_device_t*)arg;
 370         drm_nouveau_private_t *dev_priv = dev->dev_private;
 371         uint32_t status;
 372
 373         status = NV_READ(NV03_PMC_INTR_0);
 374         if (!status)
 375                 return IRQ_NONE;
 376
 377         DRM_DEBUG("PMC INTSTAT: 0x%08x\n", status);
 378
 379         if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
 380                 nouveau_fifo_irq_handler(dev);
 381                 status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
 382         }
 383         if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
 384                 nouveau_pgraph_irq_handler(dev);
 385                 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
 386         }
 387         if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
 388                 nouveau_crtc_irq_handler(dev, (status>>24)&3);
 389                 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
 390         }
 391
 392         if (status)
 393                 DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
 394
 395         return IRQ_HANDLED;
 396 }
 397