shared-core/nouveau_irq.c

   1 /*
   2  * Copyright (C) 2006 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Ben Skeggs <darktama@iinet.net.au>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "nouveau_drm.h"
  36 #include "nouveau_drv.h"
  37 #include "nouveau_reg.h"
  38 #include "nouveau_swmthd.h"
  39
  40 void nouveau_irq_preinstall(struct drm_device *dev)
  41 {
  42         struct drm_nouveau_private *dev_priv = dev->dev_private;
  43
  44         /* Master disable */
  45         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
  46 }
  47
  48 void nouveau_irq_postinstall(struct drm_device *dev)
  49 {
  50         struct drm_nouveau_private *dev_priv = dev->dev_private;
  51
  52         /* Master enable */
  53         NV_WRITE(NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
  54 }
  55
  56 void nouveau_irq_uninstall(struct drm_device *dev)
  57 {
  58         struct drm_nouveau_private *dev_priv = dev->dev_private;
  59
  60         /* Master disable */
  61         NV_WRITE(NV03_PMC_INTR_EN_0, 0);
  62 }
  63
  64 static void nouveau_fifo_irq_handler(struct drm_device *dev)
  65 {
  66         uint32_t status, chmode, chstat, channel;
  67         struct drm_nouveau_private *dev_priv = dev->dev_private;
  68
  69         status = NV_READ(NV03_PFIFO_INTR_0);
  70         if (!status)
  71                 return;
  72         chmode = NV_READ(NV04_PFIFO_MODE);
  73         chstat = NV_READ(NV04_PFIFO_DMA);
  74         channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
  75
  76         if (status & NV_PFIFO_INTR_CACHE_ERROR) {
  77                 uint32_t c1get, c1method, c1data;
  78
  79                 DRM_ERROR("PFIFO error interrupt\n");
  80
  81                 c1get = NV_READ(NV03_PFIFO_CACHE1_GET) >> 2;
  82                 if (dev_priv->card_type < NV_40) {
  83                         /* Untested, so it may not work.. */
  84                         c1method = NV_READ(NV04_PFIFO_CACHE1_METHOD(c1get));
  85                         c1data   = NV_READ(NV04_PFIFO_CACHE1_DATA(c1get));
  86                 } else {
  87                         c1method = NV_READ(NV40_PFIFO_CACHE1_METHOD(c1get));
  88                         c1data   = NV_READ(NV40_PFIFO_CACHE1_DATA(c1get));
  89                 }
  90
  91                 DRM_ERROR("Channel %d/%d - Method 0x%04x, Data 0x%08x\n",
  92                           channel, (c1method >> 13) & 7, c1method & 0x1ffc,
  93                           c1data);
  94
  95                 status &= ~NV_PFIFO_INTR_CACHE_ERROR;
  96                 NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR);
  97         }
  98
  99         if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 100                 DRM_ERROR("PFIFO DMA pusher interrupt: ch%d, 0x%08x\n",
 101                           channel, NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 102
 103                 status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 104                 NV_WRITE(NV03_PFIFO_INTR_0, NV_PFIFO_INTR_DMA_PUSHER);
 105
 106                 NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
 107                 if (NV_READ(NV04_PFIFO_CACHE1_DMA_PUT)!=NV_READ(NV04_PFIFO_CACHE1_DMA_GET))
 108                 {
 109                         uint32_t getval=NV_READ(NV04_PFIFO_CACHE1_DMA_GET)+4;
 110                         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET,getval);
 111                 }
 112         }
 113
 114         if (status) {
 115                 DRM_ERROR("Unhandled PFIFO interrupt: status=0x%08x\n", status);
 116
 117                 NV_WRITE(NV03_PFIFO_INTR_0, status);
 118         }
 119
 120         NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
 121 }
 122
 123 #if 0
 124 static void nouveau_nv04_context_switch(struct drm_device *dev)
 125 {
 126         struct drm_nouveau_private *dev_priv = dev->dev_private;
 127         uint32_t channel,i;
 128         uint32_t max=0;
 129         NV_WRITE(NV04_PGRAPH_FIFO,0x0);
 130         channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 131         //DRM_INFO("raw PFIFO_CACH1_PHS1 reg is %x\n",NV_READ(NV03_PFIFO_CACHE1_PUSH1));
 132         //DRM_INFO("currently on channel %d\n",channel);
 133         for (i=0;i<nouveau_fifo_number(dev);i++)
 134                 if ((dev_priv->fifos[i].used)&&(i!=channel)) {
 135                         uint32_t put,get,pending;
 136                         //put=NV_READ(dev_priv->ramfc_offset+i*32);
 137                         //get=NV_READ(dev_priv->ramfc_offset+4+i*32);
 138                         put=NV_READ(NV03_FIFO_REGS_DMAPUT(i));
 139                         get=NV_READ(NV03_FIFO_REGS_DMAGET(i));
 140                         pending=NV_READ(NV04_PFIFO_DMA);
 141                         //DRM_INFO("Channel %d (put/get %x/%x)\n",i,put,get);
 142                         /* mark all pending channels as such */
 143                         if ((put!=get)&!(pending&(1<<i)))
 144                         {
 145                                 pending|=(1<<i);
 146                                 NV_WRITE(NV04_PFIFO_DMA,pending);
 147                         }
 148                         max++;
 149                 }
 150         nouveau_wait_for_idle(dev);
 151
 152 #if 1
 153         /* 2-channel commute */
 154         //              NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,channel|0x100);
 155         if (channel==0)
 156                 channel=1;
 157         else
 158                 channel=0;
 159         //              dev_priv->cur_fifo=channel;
 160         NV_WRITE(NV04_PFIFO_NEXT_CHANNEL,channel|0x100);
 161 #endif
 162         //NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,max|0x100);
 163         //NV_WRITE(0x2050,max|0x100);
 164
 165         NV_WRITE(NV04_PGRAPH_FIFO,0x1);
 166
 167 }
 168 #endif
 169
 170
 171 struct nouveau_bitfield_names
 172 {
 173         uint32_t mask;
 174         const char * name;
 175 };
 176
 177 static struct nouveau_bitfield_names nouveau_nstatus_names[] =
 178 {
 179         { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 180         { NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 181         { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 182         { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
 183 };
 184
 185 static struct nouveau_bitfield_names nouveau_nstatus_names_nv10[] =
 186 {
 187         { NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 188         { NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 189         { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 190         { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
 191 };
 192
 193 static struct nouveau_bitfield_names nouveau_nsource_names[] =
 194 {
 195         { NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
 196         { NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
 197         { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
 198         { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
 199         { NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
 200         { NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
 201         { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
 202         { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
 203         { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
 204         { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
 205         { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
 206         { NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
 207         { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
 208         { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
 209         { NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
 210         { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
 211         { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
 212         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
 213         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
 214 };
 215
 216 static void
 217 nouveau_print_bitfield_names(uint32_t value,
 218                              const struct nouveau_bitfield_names *namelist,
 219                              const int namelist_len)
 220 {
 221         int i;
 222         for(i=0; i<namelist_len; ++i) {
 223                 uint32_t mask = namelist[i].mask;
 224                 if(value & mask) {
 225                         printk(" %s", namelist[i].name);
 226                         value &= ~mask;
 227                 }
 228         }
 229         if(value)
 230                 printk(" (unknown bits 0x%08x)", value);
 231 }
 232
 233 static int
 234 nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
 235 {
 236         struct drm_nouveau_private *dev_priv = dev->dev_private;
 237         int channel;
 238
 239         if (dev_priv->card_type < NV_10) {
 240                 channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
 241         } else if (dev_priv->card_type < NV_40) {
 242                 channel = (NV_READ(NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
 243         } else
 244         if (dev_priv->card_type < NV_50) {
 245                 uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 4;
 246
 247                 /* 0x400704 *sometimes* contains a sensible channel ID, but
 248                  * mostly not.. for now lookup which channel owns the active
 249                  * PGRAPH context.  Probably a better way, but this'll do
 250                  * for now.
 251                  */
 252                 for (channel = 0; channel < 32; channel++) {
 253                         if (dev_priv->fifos[channel] == NULL)
 254                                 continue;
 255                         if (cur_grctx ==
 256                             dev_priv->fifos[channel]->ramin_grctx->instance)
 257                                 break;
 258                 }
 259                 if (channel == 32) {
 260                         DRM_ERROR("AIII, unable to determine active channel "
 261                                   "from PGRAPH context 0x%08x\n", cur_grctx);
 262                         return -EINVAL;
 263                 }
 264         } else {
 265                 uint32_t cur_grctx = (NV_READ(0x40032C) & 0xfffff) << 12;
 266
 267                 for (channel = 0; channel < 128; channel++) {
 268                         if (dev_priv->fifos[channel] == NULL)
 269                                 continue;
 270                         if (cur_grctx ==
 271                             dev_priv->fifos[channel]->ramin_grctx->instance)
 272                                 break;
 273                 }
 274                 if (channel == 128) {
 275                         DRM_ERROR("AIII, unable to determine active channel "
 276                                   "from PGRAPH context 0x%08x\n", cur_grctx);
 277                         return -EINVAL;
 278                 }
 279         }
 280
 281         if (channel > nouveau_fifo_number(dev) ||
 282             dev_priv->fifos[channel] == NULL) {
 283                 DRM_ERROR("AIII, invalid/inactive channel id %d\n", channel);
 284                 return -EINVAL;
 285         }
 286
 287         *channel_ret = channel;
 288         return 0;
 289 }
 290
 291 static void
 292 nouveau_graph_dump_trap_info(struct drm_device *dev)
 293 {
 294         struct drm_nouveau_private *dev_priv = dev->dev_private;
 295         uint32_t address;
 296         uint32_t channel, class;
 297         uint32_t method, subc, data, data2;
 298         uint32_t nsource, nstatus;
 299
 300         if (nouveau_graph_trapped_channel(dev, &channel))
 301                 channel = -1;
 302
 303         data    = NV_READ(NV04_PGRAPH_TRAPPED_DATA);
 304         address = NV_READ(NV04_PGRAPH_TRAPPED_ADDR);
 305         method  = address & 0x1FFC;
 306         if (dev_priv->card_type < NV_10) {
 307                 subc = (address >> 13) & 0x7;
 308                 data2= 0;
 309         } else {
 310                 subc = (address >> 16) & 0x7;
 311                 data2= NV_READ(NV10_PGRAPH_TRAPPED_DATA_HIGH);
 312         }
 313         nsource = NV_READ(NV03_PGRAPH_NSOURCE);
 314         nstatus = NV_READ(NV03_PGRAPH_NSTATUS);
 315         if (dev_priv->card_type < NV_10) {
 316                 class = NV_READ(0x400180 + subc*4) & 0xFF;
 317         } else if (dev_priv->card_type < NV_40) {
 318                 class = NV_READ(0x400160 + subc*4) & 0xFFF;
 319         } else if (dev_priv->card_type < NV_50) {
 320                 class = NV_READ(0x400160 + subc*4) & 0xFFFF;
 321         } else {
 322                 class = NV_READ(0x400814);
 323         }
 324
 325         DRM_ERROR("nSource:");
 326         nouveau_print_bitfield_names(nsource, nouveau_nsource_names,
 327                                      ARRAY_SIZE(nouveau_nsource_names));
 328         printk(", nStatus:");
 329         if (dev_priv->card_type < NV_10)
 330                 nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names,
 331                                      ARRAY_SIZE(nouveau_nstatus_names));
 332         else
 333                 nouveau_print_bitfield_names(nstatus, nouveau_nstatus_names_nv10,
 334                                      ARRAY_SIZE(nouveau_nstatus_names_nv10));
 335         printk("\n");
 336
 337         DRM_ERROR("Channel %d/%d (class 0x%04x) - Method 0x%04x, Data 0x%08x:0x%08x\n",
 338                   channel, subc, class, method, data2, data);
 339 }
 340
 341 static void nouveau_pgraph_irq_handler(struct drm_device *dev)
 342 {
 343         struct drm_nouveau_private *dev_priv = dev->dev_private;
 344         uint32_t status, nsource, method;
 345         uint32_t obj_class;
 346
 347         while ( (status = NV_READ(NV03_PGRAPH_INTR)) ) {
 348         nsource = NV_READ(NV03_PGRAPH_NSOURCE);
 349
 350         if (status & NV_PGRAPH_INTR_NOTIFY) {
 351                 DRM_DEBUG("PGRAPH notify interrupt\n");
 352
 353                 if ( dev_priv->card_type == NV_04 && (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD ) ) {
 354                 /* NV4 (nvidia TNT 1) reports software methods with PGRAPH NOTIFY ILLEGAL_MTHD*/
 355                         method = NV_READ(NV04_PGRAPH_TRAPPED_ADDR) & 0x1FFC;
 356                         obj_class = NV_READ(NV04_PGRAPH_CTX_SWITCH1) & 0xFFF;
 357                         DRM_DEBUG("Got NV04 software method method %x for class %#x\n", method, obj_class);
 358
 359                         if ( nouveau_sw_method_execute(dev, obj_class, method) )
 360                                 DRM_ERROR("Unable to execute NV04 software method %x for object class %x. Please report.\n", method, obj_class);
 361                         }
 362                 status &= ~NV_PGRAPH_INTR_NOTIFY;
 363                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
 364                 NV_WRITE(NV04_PGRAPH_FIFO, 1);
 365         }
 366
 367         if (status & NV_PGRAPH_INTR_ERROR) {
 368                 DRM_ERROR("PGRAPH error interrupt\n");
 369
 370                 nouveau_graph_dump_trap_info(dev);
 371
 372                 status &= ~NV_PGRAPH_INTR_ERROR;
 373                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
 374         }
 375
 376         if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
 377                 uint32_t channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 378                 DRM_DEBUG("PGRAPH context switch interrupt channel %x\n",channel);
 379                 switch(dev_priv->card_type)
 380                 {
 381                         case NV_04:
 382                         case NV_05:
 383                                 nouveau_nv04_context_switch(dev);
 384                                 break;
 385                         case NV_10:
 386                         case NV_11:
 387                         case NV_17:
 388                                 nouveau_nv10_context_switch(dev);
 389                                 break;
 390                         default:
 391                                 DRM_ERROR("Context switch not implemented\n");
 392                                 break;
 393                 }
 394
 395                 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
 396                 NV_WRITE(NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
 397         }
 398
 399         if (status) {
 400                 DRM_ERROR("Unhandled PGRAPH interrupt: STAT=0x%08x\n", status);
 401                 NV_WRITE(NV03_PGRAPH_INTR, status);
 402         }
 403 NV_WRITE(NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 404         }
 405
 406 }
 407
 408 static void nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
 409 {
 410         struct drm_nouveau_private *dev_priv = dev->dev_private;
 411
 412         if (crtc&1) {
 413                 NV_WRITE(NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
 414         }
 415
 416         if (crtc&2) {
 417                 NV_WRITE(NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
 418         }
 419 }
 420
 421 irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS)
 422 {
 423         struct drm_device *dev = (struct drm_device*)arg;
 424         struct drm_nouveau_private *dev_priv = dev->dev_private;
 425         uint32_t status;
 426
 427         status = NV_READ(NV03_PMC_INTR_0);
 428         if (!status)
 429                 return IRQ_NONE;
 430
 431         if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
 432                 nouveau_fifo_irq_handler(dev);
 433                 status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
 434         }
 435
 436         if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
 437                 nouveau_pgraph_irq_handler(dev);
 438                 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
 439         }
 440
 441         if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
 442                 nouveau_crtc_irq_handler(dev, (status>>24)&3);
 443                 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
 444         }
 445
 446         if (status)
 447                 DRM_ERROR("Unhandled PMC INTR status bits 0x%08x\n", status);
 448
 449         return IRQ_HANDLED;
 450 }
 451