3 #define NV03_BOOT_0 0x00100000
4 # define NV03_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
6 # define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
7 # define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
8 # define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
9 # define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
10 # define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
11 # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
12 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
14 #define NV04_FIFO_DATA 0x0010020c
15 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
16 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
18 #define NV03_PGRAPH_STATUS 0x004006b0
19 #define NV04_PGRAPH_STATUS 0x00400700
21 #define NV_RAMIN 0x00700000
23 #define NV_RAMHT_HANDLE_OFFSET 0
24 #define NV_RAMHT_CONTEXT_OFFSET 4
25 # define NV_RAMHT_CONTEXT_VALID (1<<31)
26 # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
27 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
28 # define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
29 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
30 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
31 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
32 # define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
33 # define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
35 #define NV_DMA_ACCESS_RW 0
36 #define NV_DMA_ACCESS_RO 1
37 #define NV_DMA_ACCESS_WO 2
38 #define NV_DMA_TARGET_VIDMEM 0
39 #define NV_DMA_TARGET_AGP 3
41 #define NV03_FIFO_SIZE 0x8000UL
42 #define NV_MAX_FIFO_NUMBER 32
43 #define NV03_FIFO_REGS_SIZE 0x10000
44 #define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
45 # define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
46 # define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
48 #define NV_PMC_INTSTAT 0x00000100
49 # define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8)
50 # define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12)
51 # define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24)
52 # define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25)
53 # define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24)
54 #define NV_PMC_INTEN 0x00000140
55 # define NV_PMC_INTEN_MASTER_ENABLE (1<< 0)
57 #define NV_PGRAPH_INTSTAT 0x00400100
58 #define NV04_PGRAPH_INTEN 0x00400140
59 #define NV40_PGRAPH_INTEN 0x0040013C
60 # define NV_PGRAPH_INTR_NOTIFY (1<< 0)
61 # define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
62 # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
63 # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
64 # define NV_PGRAPH_INTR_ERROR (1<<20)
65 #define NV_PGRAPH_CTX_CONTROL 0x00400144
66 #define NV_PGRAPH_NV40_UNK220 0x00400220
67 # define NV_PGRAPH_NV40_UNK220_FB_INSTANCE
68 #define NV_PGRAPH_CTX_USER 0x00400148
69 #define NV_PGRAPH_CTX_SWITCH1 0x0040014C
70 #define NV_PGRAPH_FIFO 0x00400720
71 #define NV_PGRAPH_FFINTFC_ST2 0x00400764
73 /* It's a guess that this works on NV03. Confirmed on NV04, though */
74 #define NV_PFIFO_DELAY_0 0x00002040
75 #define NV_PFIFO_DMA_TIMESLICE 0x00002044
76 #define NV_PFIFO_INTSTAT 0x00002100
77 #define NV_PFIFO_INTEN 0x00002140
78 # define NV_PFIFO_INTR_CACHE_ERROR (1<< 0)
79 # define NV_PFIFO_INTR_RUNOUT (1<< 4)
80 # define NV_PFIFO_INTR_RUNOUT_OVERFLOW (1<< 8)
81 # define NV_PFIFO_INTR_DMA_PUSHER (1<<12)
82 # define NV_PFIFO_INTR_DMA_PT (1<<16)
83 # define NV_PFIFO_INTR_SEMAPHORE (1<<20)
84 # define NV_PFIFO_INTR_ACQUIRE_TIMEOUT (1<<24)
85 #define NV_PFIFO_RAMHT 0x00002210
86 #define NV_PFIFO_RAMFC 0x00002214
87 #define NV_PFIFO_RAMRO 0x00002218
88 #define NV40_PFIFO_RAMFC 0x00002220
89 #define NV_PFIFO_CACHES 0x00002500
90 #define NV_PFIFO_MODE 0x00002504
91 #define NV_PFIFO_DMA 0x00002508
92 #define NV_PFIFO_SIZE 0x0000250c
93 #define NV_PFIFO_CACH0_PSH0 0x00003000
94 #define NV_PFIFO_CACH0_PUL0 0x00003050
95 #define NV_PFIFO_CACH0_PUL1 0x00003054
96 #define NV_PFIFO_CACH1_PSH0 0x00003200
97 #define NV_PFIFO_CACH1_PSH1 0x00003204
98 #define NV_PFIFO_CACH1_DMAPSH 0x00003220
99 #define NV_PFIFO_CACH1_DMAF 0x00003224
100 # define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
101 # define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
102 # define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
103 # define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
104 # define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020
105 # define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028
106 # define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030
107 # define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038
108 # define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040
109 # define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048
110 # define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050
111 # define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058
112 # define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060
113 # define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068
114 # define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070
115 # define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078
116 # define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080
117 # define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088
118 # define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090
119 # define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098
120 # define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0
121 # define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8
122 # define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0
123 # define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8
124 # define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0
125 # define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8
126 # define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0
127 # define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8
128 # define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0
129 # define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8
130 # define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0
131 # define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8
132 # define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000
133 # define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000
134 # define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000
135 # define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000
136 # define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000
137 # define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000
138 # define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000
139 # define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000
140 # define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000
141 # define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000
142 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000
143 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000
144 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000
145 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000
146 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000
147 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000
148 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000
149 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000
150 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000
151 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000
152 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000
153 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000
154 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000
155 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000
156 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000
157 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000
158 # define NV_PFIFO_CACH1_ENDIAN 0x80000000
159 # define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF
160 # define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000
161 #define NV_PFIFO_CACH1_DMAS 0x00003228
162 #define NV_PFIFO_CACH1_DMAI 0x0000322c
163 #define NV_PFIFO_CACH1_DMAC 0x00003230
164 #define NV_PFIFO_CACH1_DMAP 0x00003240
165 #define NV_PFIFO_CACH1_DMAG 0x00003244
166 #define NV_PFIFO_CACH1_REF_CNT 0x00003248
167 #define NV_PFIFO_CACH1_PUL0 0x00003250
168 #define NV_PFIFO_CACH1_PUL1 0x00003254
169 #define NV_PFIFO_CACH1_HASH 0x00003258
170 #define NV_PFIFO_CACH1_ACQUIRE_TIMEOUT 0x00003260
171 #define NV_PFIFO_CACH1_ACQUIRE_TIMESTAMP 0x00003264
172 #define NV_PFIFO_CACH1_ACQUIRE_VALUE 0x00003268
173 #define NV_PFIFO_CACH1_SEMAPHORE 0x0000326C
174 #define NV_PFIFO_CACH1_GET 0x00003270
175 #define NV_PFIFO_CACH1_ENG 0x00003280
176 #define NV_PFIFO_CACH1_DMA_DCOUNT 0x000032A0
177 #define NV40_PFIFO_GRCTX_INSTANCE 0x000032E0
178 #define NV40_PFIFO_UNK32E4 0x000032E4
179 #define NV_PFIFO_CACH1_METHOD(i) (0x00003800+(i*8))
180 #define NV_PFIFO_CACH1_DATA(i) (0x00003804+(i*8))
181 #define NV40_PFIFO_CACH1_METHOD(i) (0x00090000+(i*8))
182 #define NV40_PFIFO_CACH1_DATA(i) (0x00090004+(i*8))
184 #define NV_CRTC0_INTSTAT 0x00600100
185 #define NV_CRTC0_INTEN 0x00600140
186 #define NV_CRTC1_INTSTAT 0x00602100
187 #define NV_CRTC1_INTEN 0x00602140
188 # define NV_CRTC_INTR_VBLANK (1<<0)
190 /* Fifo commands. These are not regs, neither masks */
191 #define NV03_FIFO_CMD_JUMP 0x20000000
192 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
193 #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
196 #define NV10_RAMFC_DMA_PUT 0x00
197 #define NV10_RAMFC_DMA_GET 0x04
198 #define NV10_RAMFC_REF_CNT 0x08
199 #define NV10_RAMFC_DMA_INSTANCE 0x0C
200 #define NV10_RAMFC_DMA_STATE 0x10
201 #define NV10_RAMFC_DMA_FETCH 0x14
202 #define NV10_RAMFC_ENGINE 0x18
203 #define NV10_RAMFC_PULL1_ENGINE 0x1C
204 #define NV10_RAMFC_ACQUIRE_VALUE 0x20
205 #define NV10_RAMFC_ACQUIRE_TIMESTAMP 0x24
206 #define NV10_RAMFC_ACQUIRE_TIMEOUT 0x28
207 #define NV10_RAMFC_SEMAPHORE 0x2C
208 #define NV10_RAMFC_DMA_SUBROUTINE 0x30
210 #define NV40_RAMFC_DMA_PUT 0x00
211 #define NV40_RAMFC_DMA_GET 0x04
212 #define NV40_RAMFC_REF_CNT 0x08
213 #define NV40_RAMFC_DMA_INSTANCE 0x0C
214 #define NV40_RAMFC_DMA_DCOUNT /* ? */ 0x10
215 #define NV40_RAMFC_DMA_STATE 0x14
216 #define NV40_RAMFC_DMA_FETCH 0x18
217 #define NV40_RAMFC_ENGINE 0x1C
218 #define NV40_RAMFC_PULL1_ENGINE 0x20
219 #define NV40_RAMFC_ACQUIRE_VALUE 0x24
220 #define NV40_RAMFC_ACQUIRE_TIMESTAMP 0x28
221 #define NV40_RAMFC_ACQUIRE_TIMEOUT 0x2C
222 #define NV40_RAMFC_SEMAPHORE 0x30
223 #define NV40_RAMFC_DMA_SUBROUTINE 0x34
224 #define NV40_RAMFC_GRCTX_INSTANCE /* guess */ 0x38
225 #define NV40_RAMFC_DMA_TIMESLICE 0x3C
226 #define NV40_RAMFC_UNK_40 0x40
227 #define NV40_RAMFC_UNK_44 0x44
228 #define NV40_RAMFC_UNK_48 0x48
229 #define NV40_RAMFC_2088 0x4C
230 #define NV40_RAMFC_3300 0x50
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