shared-core/nouveau_reg.h

   1
   2
   3 #define NV03_BOOT_0                                        0x00100000
   4 #    define NV03_BOOT_0_RAM_AMOUNT                         0x00000003
   5 #    define NV03_BOOT_0_RAM_AMOUNT_8MB                     0x00000000
   6 #    define NV03_BOOT_0_RAM_AMOUNT_2MB                     0x00000001
   7 #    define NV03_BOOT_0_RAM_AMOUNT_4MB                     0x00000002
   8 #    define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM               0x00000003
   9 #    define NV04_BOOT_0_RAM_AMOUNT_32MB                    0x00000000
  10 #    define NV04_BOOT_0_RAM_AMOUNT_4MB                     0x00000001
  11 #    define NV04_BOOT_0_RAM_AMOUNT_8MB                     0x00000002
  12 #    define NV04_BOOT_0_RAM_AMOUNT_16MB                    0x00000003
  13
  14 #define NV04_FIFO_DATA                                     0x0010020c
  15 #    define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK              0xfff00000
  16 #    define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT             20
  17
  18 #define NV_RAMIN                                           0x00700000
  19
  20 #define NV_RAMHT_HANDLE_OFFSET                             0
  21 #define NV_RAMHT_CONTEXT_OFFSET                            4
  22 #    define NV_RAMHT_CONTEXT_VALID                         (1<<31)
  23 #    define NV_RAMHT_CONTEXT_CHANNEL_SHIFT                 24
  24 #    define NV_RAMHT_CONTEXT_ENGINE_SHIFT                  16
  25 #        define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE           0
  26 #        define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS           1
  27 #    define NV_RAMHT_CONTEXT_INSTANCE_SHIFT                0
  28 #    define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT               23
  29 #    define NV40_RAMHT_CONTEXT_ENGINE_SHIFT                20
  30 #    define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT              0
  31
  32 /* DMA object defines */
  33 #define NV_DMA_ACCESS_RW 0
  34 #define NV_DMA_ACCESS_RO 1
  35 #define NV_DMA_ACCESS_WO 2
  36 #define NV_DMA_TARGET_VIDMEM 0
  37 #define NV_DMA_TARGET_PCI    2
  38 #define NV_DMA_TARGET_AGP    3
  39 /*The following is not a real value used by nvidia cards, it's changed by nouveau_object_dma_create*/
  40 #define NV_DMA_TARGET_PCI_NONLINEAR   8
  41
  42 /* Some object classes we care about in the drm */
  43 #define NV_CLASS_DMA_FROM_MEMORY                           0x00000002
  44 #define NV_CLASS_DMA_TO_MEMORY                             0x00000003
  45 #define NV_CLASS_NULL                                      0x00000030
  46 #define NV_CLASS_DMA_IN_MEMORY                             0x0000003D
  47
  48 #define NV03_FIFO_SIZE                                     0x8000UL
  49 #define NV_MAX_FIFO_NUMBER                                 128
  50 #define NV03_FIFO_REGS_SIZE                                0x10000
  51 #define NV03_FIFO_REGS(i)                                  (0x00800000+i*NV03_FIFO_REGS_SIZE)
  52 #    define NV03_FIFO_REGS_DMAPUT(i)                       (NV03_FIFO_REGS(i)+0x40)
  53 #    define NV03_FIFO_REGS_DMAGET(i)                       (NV03_FIFO_REGS(i)+0x44)
  54 #define NV50_FIFO_REGS_SIZE                                0x2000
  55 #define NV50_FIFO_REGS(i)                                  (0x00c00000+i*NV50_FIFO_REGS_SIZE)
  56 #    define NV50_FIFO_REGS_DMAPUT(i)                       (NV50_FIFO_REGS(i)+0x40)
  57 #    define NV50_FIFO_REGS_DMAGET(i)                       (NV50_FIFO_REGS(i)+0x44)
  58
  59 #define NV03_PMC_BOOT_0                                    0x00000000
  60 #define NV03_PMC_INTR_0                                    0x00000100
  61 #    define NV_PMC_INTR_0_PFIFO_PENDING                       (1<< 8)
  62 #    define NV_PMC_INTR_0_PGRAPH_PENDING                      (1<<12)
  63 #    define NV_PMC_INTR_0_CRTC0_PENDING                       (1<<24)
  64 #    define NV_PMC_INTR_0_CRTC1_PENDING                       (1<<25)
  65 #    define NV_PMC_INTR_0_CRTCn_PENDING                       (3<<24)
  66 #define NV03_PMC_INTR_EN_0                                 0x00000140
  67 #    define NV_PMC_INTR_EN_0_MASTER_ENABLE                    (1<< 0)
  68 #define NV03_PMC_ENABLE                                    0x00000200
  69 #    define NV_PMC_ENABLE_PFIFO                               (1<< 8)
  70 #    define NV_PMC_ENABLE_PGRAPH                              (1<<12)
  71 /* Disabling the below bit breaks newer (G7X only?) mobile chipsets,
  72  * the card will hang early on in the X init process.
  73  */
  74 #    define NV_PMC_ENABLE_UNK13                               (1<<13)
  75 #define NV40_PMC_1700                                      0x00001700
  76 #define NV40_PMC_1704                                      0x00001704
  77 #define NV40_PMC_1708                                      0x00001708
  78 #define NV40_PMC_170C                                      0x0000170C
  79
  80 /* probably PMC ? */
  81 #define NV50_PUNK_BAR0_PRAMIN                              0x00001700
  82 #define NV50_PUNK_BAR_CFG_BASE                             0x00001704
  83 #define NV50_PUNK_BAR_CFG_BASE_VALID                          (1<<30)
  84 #define NV50_PUNK_BAR1_CTXDMA                              0x00001708
  85 #define NV50_PUNK_BAR1_CTXDMA_VALID                           (1<<31)
  86 #define NV50_PUNK_BAR3_CTXDMA                              0x0000170C
  87 #define NV50_PUNK_BAR3_CTXDMA_VALID                           (1<<31)
  88 #define NV50_PUNK_UNK1710                                  0x00001710
  89
  90 #define NV04_PTIMER_INTR_0                                 0x00009100
  91 #define NV04_PTIMER_INTR_EN_0                              0x00009140
  92 #define NV04_PTIMER_NUMERATOR                              0x00009200
  93 #define NV04_PTIMER_DENOMINATOR                            0x00009210
  94 #define NV04_PTIMER_TIME_0                                 0x00009400
  95 #define NV04_PTIMER_TIME_1                                 0x00009410
  96 #define NV04_PTIMER_ALARM_0                                0x00009420
  97
  98 #define NV04_PFB_CFG0                                      0x00100200
  99 #define NV04_PFB_CFG1                                      0x00100204
 100 #define NV40_PFB_020C                                      0x0010020C
 101 #define NV10_PFB_TILE(i)                                   (0x00100240 + (i*16))
 102 #define NV10_PFB_TILE__SIZE                                8
 103 #define NV10_PFB_TLIMIT(i)                                 (0x00100244 + (i*16))
 104 #define NV10_PFB_TSIZE(i)                                  (0x00100248 + (i*16))
 105 #define NV10_PFB_TSTATUS(i)                                (0x0010024C + (i*16))
 106 #define NV10_PFB_CLOSE_PAGE2                               0x0010033C
 107 #define NV40_PFB_TILE(i)                                   (0x00100600 + (i*16))
 108 #define NV40_PFB_TILE__SIZE_0                              12
 109 #define NV40_PFB_TILE__SIZE_1                              15
 110 #define NV40_PFB_TLIMIT(i)                                 (0x00100604 + (i*16))
 111 #define NV40_PFB_TSIZE(i)                                  (0x00100608 + (i*16))
 112 #define NV40_PFB_TSTATUS(i)                                (0x0010060C + (i*16))
 113
 114 #define NV04_PGRAPH_DEBUG_0                                0x00400080
 115 #define NV04_PGRAPH_DEBUG_1                                0x00400084
 116 #define NV04_PGRAPH_DEBUG_2                                0x00400088
 117 #define NV04_PGRAPH_DEBUG_3                                0x0040008c
 118 #define NV10_PGRAPH_DEBUG_4                                0x00400090
 119 #define NV03_PGRAPH_INTR                                   0x00400100
 120 #define NV03_PGRAPH_NSTATUS                                0x00400104
 121 #    define NV03_PGRAPH_NSTATUS_STATE_IN_USE                  (1<<23)
 122 #    define NV03_PGRAPH_NSTATUS_INVALID_STATE                 (1<<24)
 123 #    define NV03_PGRAPH_NSTATUS_BAD_ARGUMENT                  (1<<25)
 124 #    define NV03_PGRAPH_NSTATUS_PROTECTION_FAULT              (1<<26)
 125 #define NV03_PGRAPH_NSOURCE                                0x00400108
 126 #    define NV03_PGRAPH_NSOURCE_NOTIFICATION                  (1<< 0)
 127 #    define NV03_PGRAPH_NSOURCE_DATA_ERROR                    (1<< 1)
 128 #    define NV03_PGRAPH_NSOURCE_PROTECTION_ERROR              (1<< 2)
 129 #    define NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION               (1<< 3)
 130 #    define NV03_PGRAPH_NSOURCE_LIMIT_COLOR                   (1<< 4)
 131 #    define NV03_PGRAPH_NSOURCE_LIMIT_ZETA                    (1<< 5)
 132 #    define NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD                  (1<< 6)
 133 #    define NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION              (1<< 7)
 134 #    define NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION              (1<< 8)
 135 #    define NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION              (1<< 9)
 136 #    define NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION               (1<<10)
 137 #    define NV03_PGRAPH_NSOURCE_STATE_INVALID                 (1<<11)
 138 #    define NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY                 (1<<12)
 139 #    define NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE                 (1<<13)
 140 #    define NV03_PGRAPH_NSOURCE_METHOD_CNT                    (1<<14)
 141 #    define NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION              (1<<15)
 142 #    define NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION            (1<<16)
 143 #    define NV03_PGRAPH_NSOURCE_DMA_WIDTH_A                   (1<<17)
 144 #    define NV03_PGRAPH_NSOURCE_DMA_WIDTH_B                   (1<<18)
 145 #define NV03_PGRAPH_INTR_EN                                0x00400140
 146 #define NV40_PGRAPH_INTR_EN                                0x0040013C
 147 #    define NV_PGRAPH_INTR_NOTIFY                             (1<< 0)
 148 #    define NV_PGRAPH_INTR_MISSING_HW                         (1<< 4)
 149 #    define NV_PGRAPH_INTR_CONTEXT_SWITCH                     (1<<12)
 150 #    define NV_PGRAPH_INTR_BUFFER_NOTIFY                      (1<<16)
 151 #    define NV_PGRAPH_INTR_ERROR                              (1<<20)
 152 #define NV10_PGRAPH_CTX_CONTROL                            0x00400144
 153 #define NV10_PGRAPH_CTX_USER                               0x00400148
 154 #define NV10_PGRAPH_CTX_SWITCH1                            0x0040014C
 155 #define NV10_PGRAPH_CTX_SWITCH2                            0x00400150
 156 #define NV10_PGRAPH_CTX_SWITCH3                            0x00400154
 157 #define NV10_PGRAPH_CTX_SWITCH4                            0x00400158
 158 #define NV10_PGRAPH_CTX_SWITCH5                            0x0040015C
 159 #define NV04_PGRAPH_CTX_SWITCH1                            0x00400160
 160 #define NV10_PGRAPH_CTX_CACHE1                             0x00400160
 161 #define NV04_PGRAPH_CTX_SWITCH2                            0x00400164
 162 #define NV04_PGRAPH_CTX_SWITCH3                            0x00400168
 163 #define NV04_PGRAPH_CTX_SWITCH4                            0x0040016C
 164 #define NV04_PGRAPH_CTX_CONTROL                            0x00400170
 165 #define NV04_PGRAPH_CTX_USER                               0x00400174
 166 #define NV04_PGRAPH_CTX_CACHE1                             0x00400180
 167 #define NV10_PGRAPH_CTX_CACHE2                             0x00400180
 168 #define NV03_PGRAPH_CTX_CONTROL                            0x00400190
 169 #define NV03_PGRAPH_CTX_USER                               0x00400194
 170 #define NV04_PGRAPH_CTX_CACHE2                             0x004001A0
 171 #define NV10_PGRAPH_CTX_CACHE3                             0x004001A0
 172 #define NV04_PGRAPH_CTX_CACHE3                             0x004001C0
 173 #define NV10_PGRAPH_CTX_CACHE4                             0x004001C0
 174 #define NV04_PGRAPH_CTX_CACHE4                             0x004001E0
 175 #define NV10_PGRAPH_CTX_CACHE5                             0x004001E0
 176 #define NV40_PGRAPH_CTXCTL_0304                            0x00400304
 177 #define NV40_PGRAPH_CTXCTL_0304_XFER_CTX                   0x00000001
 178 #define NV40_PGRAPH_CTXCTL_UCODE_STAT                      0x00400308
 179 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_MASK              0xff000000
 180 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT                     24
 181 #define NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK              0x00ffffff
 182 #define NV40_PGRAPH_CTXCTL_0310                            0x00400310
 183 #define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE                  0x00000020
 184 #define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD                  0x00000040
 185 #define NV40_PGRAPH_CTXCTL_030C                            0x0040030c
 186 #define NV40_PGRAPH_CTXCTL_UCODE_INDEX                     0x00400324
 187 #define NV40_PGRAPH_CTXCTL_UCODE_DATA                      0x00400328
 188 #define NV40_PGRAPH_CTXCTL_CUR                             0x0040032c
 189 #define NV40_PGRAPH_CTXCTL_CUR_LOADED                      0x01000000
 190 #define NV40_PGRAPH_CTXCTL_CUR_INST_MASK                   0x000FFFFF
 191 #define NV03_PGRAPH_ABS_X_RAM                              0x00400400
 192 #define NV03_PGRAPH_ABS_Y_RAM                              0x00400480
 193 #define NV03_PGRAPH_X_MISC                                 0x00400500
 194 #define NV03_PGRAPH_Y_MISC                                 0x00400504
 195 #define NV04_PGRAPH_VALID1                                 0x00400508
 196 #define NV04_PGRAPH_SOURCE_COLOR                           0x0040050C
 197 #define NV04_PGRAPH_MISC24_0                               0x00400510
 198 #define NV03_PGRAPH_XY_LOGIC_MISC0                         0x00400514
 199 #define NV03_PGRAPH_XY_LOGIC_MISC1                         0x00400518
 200 #define NV03_PGRAPH_XY_LOGIC_MISC2                         0x0040051C
 201 #define NV03_PGRAPH_XY_LOGIC_MISC3                         0x00400520
 202 #define NV03_PGRAPH_CLIPX_0                                0x00400524
 203 #define NV03_PGRAPH_CLIPX_1                                0x00400528
 204 #define NV03_PGRAPH_CLIPY_0                                0x0040052C
 205 #define NV03_PGRAPH_CLIPY_1                                0x00400530
 206 #define NV03_PGRAPH_ABS_ICLIP_XMAX                         0x00400534
 207 #define NV03_PGRAPH_ABS_ICLIP_YMAX                         0x00400538
 208 #define NV03_PGRAPH_ABS_UCLIP_XMIN                         0x0040053C
 209 #define NV03_PGRAPH_ABS_UCLIP_YMIN                         0x00400540
 210 #define NV03_PGRAPH_ABS_UCLIP_XMAX                         0x00400544
 211 #define NV03_PGRAPH_ABS_UCLIP_YMAX                         0x00400548
 212 #define NV03_PGRAPH_ABS_UCLIPA_XMIN                        0x00400560
 213 #define NV03_PGRAPH_ABS_UCLIPA_YMIN                        0x00400564
 214 #define NV03_PGRAPH_ABS_UCLIPA_XMAX                        0x00400568
 215 #define NV03_PGRAPH_ABS_UCLIPA_YMAX                        0x0040056C
 216 #define NV04_PGRAPH_MISC24_1                               0x00400570
 217 #define NV04_PGRAPH_MISC24_2                               0x00400574
 218 #define NV04_PGRAPH_VALID2                                 0x00400578
 219 #define NV04_PGRAPH_PASSTHRU_0                             0x0040057C
 220 #define NV04_PGRAPH_PASSTHRU_1                             0x00400580
 221 #define NV04_PGRAPH_PASSTHRU_2                             0x00400584
 222 #define NV10_PGRAPH_DIMX_TEXTURE                           0x00400588
 223 #define NV10_PGRAPH_WDIMX_TEXTURE                          0x0040058C
 224 #define NV04_PGRAPH_COMBINE_0_ALPHA                        0x00400590
 225 #define NV04_PGRAPH_COMBINE_0_COLOR                        0x00400594
 226 #define NV04_PGRAPH_COMBINE_1_ALPHA                        0x00400598
 227 #define NV04_PGRAPH_COMBINE_1_COLOR                        0x0040059C
 228 #define NV04_PGRAPH_FORMAT_0                               0x004005A8
 229 #define NV04_PGRAPH_FORMAT_1                               0x004005AC
 230 #define NV04_PGRAPH_FILTER_0                               0x004005B0
 231 #define NV04_PGRAPH_FILTER_1                               0x004005B4
 232 #define NV03_PGRAPH_MONO_COLOR0                            0x00400600
 233 #define NV04_PGRAPH_ROP3                                   0x00400604
 234 #define NV04_PGRAPH_BETA_AND                               0x00400608
 235 #define NV04_PGRAPH_BETA_PREMULT                           0x0040060C
 236 #define NV04_PGRAPH_LIMIT_VIOL_PIX                         0x00400610
 237 #define NV04_PGRAPH_FORMATS                                0x00400618
 238 #define NV10_PGRAPH_DEBUG_2                                0x00400620
 239 #define NV04_PGRAPH_BOFFSET0                               0x00400640
 240 #define NV04_PGRAPH_BOFFSET1                               0x00400644
 241 #define NV04_PGRAPH_BOFFSET2                               0x00400648
 242 #define NV04_PGRAPH_BOFFSET3                               0x0040064C
 243 #define NV04_PGRAPH_BOFFSET4                               0x00400650
 244 #define NV04_PGRAPH_BOFFSET5                               0x00400654
 245 #define NV04_PGRAPH_BBASE0                                 0x00400658
 246 #define NV04_PGRAPH_BBASE1                                 0x0040065C
 247 #define NV04_PGRAPH_BBASE2                                 0x00400660
 248 #define NV04_PGRAPH_BBASE3                                 0x00400664
 249 #define NV04_PGRAPH_BBASE4                                 0x00400668
 250 #define NV04_PGRAPH_BBASE5                                 0x0040066C
 251 #define NV04_PGRAPH_BPITCH0                                0x00400670
 252 #define NV04_PGRAPH_BPITCH1                                0x00400674
 253 #define NV04_PGRAPH_BPITCH2                                0x00400678
 254 #define NV04_PGRAPH_BPITCH3                                0x0040067C
 255 #define NV04_PGRAPH_BPITCH4                                0x00400680
 256 #define NV04_PGRAPH_BLIMIT0                                0x00400684
 257 #define NV04_PGRAPH_BLIMIT1                                0x00400688
 258 #define NV04_PGRAPH_BLIMIT2                                0x0040068C
 259 #define NV04_PGRAPH_BLIMIT3                                0x00400690
 260 #define NV04_PGRAPH_BLIMIT4                                0x00400694
 261 #define NV04_PGRAPH_BLIMIT5                                0x00400698
 262 #define NV04_PGRAPH_BSWIZZLE2                              0x0040069C
 263 #define NV04_PGRAPH_BSWIZZLE5                              0x004006A0
 264 #define NV03_PGRAPH_STATUS                                 0x004006B0
 265 #define NV04_PGRAPH_STATUS                                 0x00400700
 266 #define NV04_PGRAPH_TRAPPED_ADDR                           0x00400704
 267 #define NV04_PGRAPH_TRAPPED_DATA                           0x00400708
 268 #define NV04_PGRAPH_SURFACE                                0x0040070C
 269 #define NV10_PGRAPH_TRAPPED_DATA_HIGH                      0x0040070C
 270 #define NV04_PGRAPH_STATE                                  0x00400710
 271 #define NV10_PGRAPH_SURFACE                                0x00400710
 272 #define NV04_PGRAPH_NOTIFY                                 0x00400714
 273 #define NV10_PGRAPH_STATE                                  0x00400714
 274 #define NV10_PGRAPH_NOTIFY                                 0x00400718
 275
 276 #define NV04_PGRAPH_FIFO                                   0x00400720
 277
 278 #define NV04_PGRAPH_BPIXEL                                 0x00400724
 279 #define NV10_PGRAPH_RDI_INDEX                              0x00400750
 280 #define NV04_PGRAPH_FFINTFC_ST2                            0x00400754
 281 #define NV10_PGRAPH_RDI_DATA                               0x00400754
 282 #define NV04_PGRAPH_DMA_PITCH                              0x00400760
 283 #define NV10_PGRAPH_FFINTFC_ST2                            0x00400764
 284 #define NV04_PGRAPH_DVD_COLORFMT                           0x00400764
 285 #define NV04_PGRAPH_SCALED_FORMAT                          0x00400768
 286 #define NV10_PGRAPH_DMA_PITCH                              0x00400770
 287 #define NV10_PGRAPH_DVD_COLORFMT                           0x00400774
 288 #define NV10_PGRAPH_SCALED_FORMAT                          0x00400778
 289 #define NV10_PGRAPH_CHANNEL_CTX_TABLE                      0x00400780
 290 #define NV10_PGRAPH_CHANNEL_CTX_SIZE                       0x00400784
 291 #define NV20_PGRAPH_CHANNEL_CTX_POINTER                    0x00400784
 292 #define NV10_PGRAPH_CHANNEL_CTX_POINTER                    0x00400788
 293 #define NV20_PGRAPH_CHANNEL_CTX_XFER                       0x00400788
 294 #define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD                  0x00000001
 295 #define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE                  0x00000002
 296 #define NV04_PGRAPH_PATT_COLOR0                            0x00400800
 297 #define NV04_PGRAPH_PATT_COLOR1                            0x00400804
 298 #define NV04_PGRAPH_PATTERN                                0x00400808
 299 #define NV04_PGRAPH_PATTERN_SHAPE                          0x00400810
 300 #define NV04_PGRAPH_CHROMA                                 0x00400814
 301 #define NV04_PGRAPH_CONTROL0                               0x00400818
 302 #define NV04_PGRAPH_CONTROL1                               0x0040081C
 303 #define NV04_PGRAPH_CONTROL2                               0x00400820
 304 #define NV04_PGRAPH_BLEND                                  0x00400824
 305 #define NV04_PGRAPH_STORED_FMT                             0x00400830
 306 #define NV04_PGRAPH_PATT_COLORRAM                          0x00400900
 307 #define NV40_PGRAPH_TILE0(i)                               0x00400900
 308 #define NV40_PGRAPH_TLIMIT0(i)                             0x00400904
 309 #define NV40_PGRAPH_TSIZE0(i)                              0x00400908
 310 #define NV40_PGRAPH_TSTATUS0(i)                            0x0040090C
 311 #define NV10_PGRAPH_TILE(i)                                (0x00400B00 + (i*16))
 312 #define NV10_PGRAPH_TLIMIT(i)                              (0x00400B04 + (i*16))
 313 #define NV10_PGRAPH_TSIZE(i)                               (0x00400B08 + (i*16))
 314 #define NV10_PGRAPH_TSTATUS(i)                             (0x00400B0C + (i*16))
 315 #define NV04_PGRAPH_U_RAM                                  0x00400D00
 316 #define NV47_PGRAPH_TILE0(i)                               0x00400D00
 317 #define NV47_PGRAPH_TLIMIT0(i)                             0x00400D04
 318 #define NV47_PGRAPH_TSIZE0(i)                              0x00400D08
 319 #define NV47_PGRAPH_TSTATUS0(i)                            0x00400D0C
 320 #define NV04_PGRAPH_V_RAM                                  0x00400D40
 321 #define NV04_PGRAPH_W_RAM                                  0x00400D80
 322 #define NV10_PGRAPH_WINDOWCLIP_HORIZONTAL                  0x00400F00
 323 #define NV10_PGRAPH_WINDOWCLIP_VERTICAL                    0x00400F20
 324 #define NV10_PGRAPH_XFMODE0                                0x00400F40
 325 #define NV10_PGRAPH_XFMODE1                                0x00400F44
 326 #define NV10_PGRAPH_GLOBALSTATE0                           0x00400F48
 327 #define NV10_PGRAPH_GLOBALSTATE1                           0x00400F4C
 328 #define NV10_PGRAPH_PIPE_ADDRESS                           0x00400F50
 329 #define NV10_PGRAPH_PIPE_DATA                              0x00400F54
 330 #define NV04_PGRAPH_DMA_START_0                            0x00401000
 331 #define NV04_PGRAPH_DMA_START_1                            0x00401004
 332 #define NV04_PGRAPH_DMA_LENGTH                             0x00401008
 333 #define NV04_PGRAPH_DMA_MISC                               0x0040100C
 334 #define NV04_PGRAPH_DMA_DATA_0                             0x00401020
 335 #define NV04_PGRAPH_DMA_DATA_1                             0x00401024
 336 #define NV04_PGRAPH_DMA_RM                                 0x00401030
 337 #define NV04_PGRAPH_DMA_A_XLATE_INST                       0x00401040
 338 #define NV04_PGRAPH_DMA_A_CONTROL                          0x00401044
 339 #define NV04_PGRAPH_DMA_A_LIMIT                            0x00401048
 340 #define NV04_PGRAPH_DMA_A_TLB_PTE                          0x0040104C
 341 #define NV04_PGRAPH_DMA_A_TLB_TAG                          0x00401050
 342 #define NV04_PGRAPH_DMA_A_ADJ_OFFSET                       0x00401054
 343 #define NV04_PGRAPH_DMA_A_OFFSET                           0x00401058
 344 #define NV04_PGRAPH_DMA_A_SIZE                             0x0040105C
 345 #define NV04_PGRAPH_DMA_A_Y_SIZE                           0x00401060
 346 #define NV04_PGRAPH_DMA_B_XLATE_INST                       0x00401080
 347 #define NV04_PGRAPH_DMA_B_CONTROL                          0x00401084
 348 #define NV04_PGRAPH_DMA_B_LIMIT                            0x00401088
 349 #define NV04_PGRAPH_DMA_B_TLB_PTE                          0x0040108C
 350 #define NV04_PGRAPH_DMA_B_TLB_TAG                          0x00401090
 351 #define NV04_PGRAPH_DMA_B_ADJ_OFFSET                       0x00401094
 352 #define NV04_PGRAPH_DMA_B_OFFSET                           0x00401098
 353 #define NV04_PGRAPH_DMA_B_SIZE                             0x0040109C
 354 #define NV04_PGRAPH_DMA_B_Y_SIZE                           0x004010A0
 355 #define NV40_PGRAPH_TILE1(i)                               0x00406900
 356 #define NV40_PGRAPH_TLIMIT1(i)                             0x00406904
 357 #define NV40_PGRAPH_TSIZE1(i)                              0x00406908
 358 #define NV40_PGRAPH_TSTATUS1(i)                            0x0040690C
 359
 360
 361 /* It's a guess that this works on NV03. Confirmed on NV04, though */
 362 #define NV04_PFIFO_DELAY_0                                 0x00002040
 363 #define NV04_PFIFO_DMA_TIMESLICE                           0x00002044
 364 #define NV04_PFIFO_NEXT_CHANNEL                            0x00002050
 365 #define NV03_PFIFO_INTR_0                                  0x00002100
 366 #define NV03_PFIFO_INTR_EN_0                               0x00002140
 367 #    define NV_PFIFO_INTR_CACHE_ERROR                         (1<< 0)
 368 #    define NV_PFIFO_INTR_RUNOUT                              (1<< 4)
 369 #    define NV_PFIFO_INTR_RUNOUT_OVERFLOW                     (1<< 8)
 370 #    define NV_PFIFO_INTR_DMA_PUSHER                          (1<<12)
 371 #    define NV_PFIFO_INTR_DMA_PT                              (1<<16)
 372 #    define NV_PFIFO_INTR_SEMAPHORE                           (1<<20)
 373 #    define NV_PFIFO_INTR_ACQUIRE_TIMEOUT                     (1<<24)
 374 #define NV03_PFIFO_RAMHT                                   0x00002210
 375 #define NV03_PFIFO_RAMFC                                   0x00002214
 376 #define NV03_PFIFO_RAMRO                                   0x00002218
 377 #define NV40_PFIFO_RAMFC                                   0x00002220
 378 #define NV03_PFIFO_CACHES                                  0x00002500
 379 #define NV04_PFIFO_MODE                                    0x00002504
 380 #define NV04_PFIFO_DMA                                     0x00002508
 381 #define NV04_PFIFO_SIZE                                    0x0000250c
 382 #define NV50_PFIFO_CTX_TABLE(c)                        (0x2600+(c)*4)
 383 #define NV50_PFIFO_CTX_TABLE__SIZE                                128
 384 #define NV50_PFIFO_CTX_TABLE_CHANNEL_ENABLED                  (1<<31)
 385 #define NV50_PFIFO_CTX_TABLE_UNK30_BAD                        (1<<30)
 386 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G80             0x0FFFFFFF
 387 #define NV50_PFIFO_CTX_TABLE_INSTANCE_MASK_G84             0x00FFFFFF
 388 #define NV03_PFIFO_CACHE0_PUSH0                            0x00003000
 389 #define NV03_PFIFO_CACHE0_PULL0                            0x00003040
 390 #define NV04_PFIFO_CACHE0_PULL0                            0x00003050
 391 #define NV04_PFIFO_CACHE0_PULL1                            0x00003054
 392 #define NV03_PFIFO_CACHE1_PUSH0                            0x00003200
 393 #define NV03_PFIFO_CACHE1_PUSH1                            0x00003204
 394 #define NV04_PFIFO_CACHE1_DMA_PUSH                         0x00003220
 395 #define NV04_PFIFO_CACHE1_DMA_FETCH                        0x00003224
 396 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_8_BYTES         0x00000000
 397 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_16_BYTES        0x00000008
 398 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_24_BYTES        0x00000010
 399 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_32_BYTES        0x00000018
 400 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_40_BYTES        0x00000020
 401 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_48_BYTES        0x00000028
 402 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_56_BYTES        0x00000030
 403 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_64_BYTES        0x00000038
 404 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_72_BYTES        0x00000040
 405 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_80_BYTES        0x00000048
 406 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_88_BYTES        0x00000050
 407 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_96_BYTES        0x00000058
 408 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_104_BYTES       0x00000060
 409 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_112_BYTES       0x00000068
 410 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_120_BYTES       0x00000070
 411 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES       0x00000078
 412 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_136_BYTES       0x00000080
 413 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_144_BYTES       0x00000088
 414 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_152_BYTES       0x00000090
 415 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_160_BYTES       0x00000098
 416 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_168_BYTES       0x000000A0
 417 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_176_BYTES       0x000000A8
 418 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_184_BYTES       0x000000B0
 419 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_192_BYTES       0x000000B8
 420 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_200_BYTES       0x000000C0
 421 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_208_BYTES       0x000000C8
 422 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_216_BYTES       0x000000D0
 423 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_224_BYTES       0x000000D8
 424 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_232_BYTES       0x000000E0
 425 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_240_BYTES       0x000000E8
 426 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_248_BYTES       0x000000F0
 427 #    define NV_PFIFO_CACHE1_DMA_FETCH_TRIG_256_BYTES       0x000000F8
 428 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE                 0x0000E000
 429 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_32_BYTES        0x00000000
 430 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_64_BYTES        0x00002000
 431 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_96_BYTES        0x00004000
 432 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES       0x00006000
 433 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_160_BYTES       0x00008000
 434 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_192_BYTES       0x0000A000
 435 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_224_BYTES       0x0000C000
 436 #    define NV_PFIFO_CACHE1_DMA_FETCH_SIZE_256_BYTES       0x0000E000
 437 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS             0x001F0000
 438 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_0           0x00000000
 439 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_1           0x00010000
 440 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_2           0x00020000
 441 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_3           0x00030000
 442 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_4           0x00040000
 443 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_5           0x00050000
 444 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_6           0x00060000
 445 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_7           0x00070000
 446 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8           0x00080000
 447 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_9           0x00090000
 448 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_10          0x000A0000
 449 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_11          0x000B0000
 450 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_12          0x000C0000
 451 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_13          0x000D0000
 452 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_14          0x000E0000
 453 #    define NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_15          0x000F0000
 454 #    define NV_PFIFO_CACHE1_ENDIAN                         0x80000000
 455 #    define NV_PFIFO_CACHE1_LITTLE_ENDIAN                  0x7FFFFFFF
 456 #    define NV_PFIFO_CACHE1_BIG_ENDIAN                     0x80000000
 457 #define NV04_PFIFO_CACHE1_DMA_STATE                        0x00003228
 458 #define NV04_PFIFO_CACHE1_DMA_INSTANCE                     0x0000322c
 459 #define NV04_PFIFO_CACHE1_DMA_CTL                          0x00003230
 460 #define NV04_PFIFO_CACHE1_DMA_PUT                          0x00003240
 461 #define NV04_PFIFO_CACHE1_DMA_GET                          0x00003244
 462 #define NV10_PFIFO_CACHE1_REF_CNT                          0x00003248
 463 #define NV10_PFIFO_CACHE1_DMA_SUBROUTINE                   0x0000324C
 464 #define NV03_PFIFO_CACHE1_PULL0                            0x00003240
 465 #define NV04_PFIFO_CACHE1_PULL0                            0x00003250
 466 #define NV03_PFIFO_CACHE1_PULL1                            0x00003250
 467 #define NV04_PFIFO_CACHE1_PULL1                            0x00003254
 468 #define NV04_PFIFO_CACHE1_HASH                             0x00003258
 469 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT                  0x00003260
 470 #define NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP                0x00003264
 471 #define NV10_PFIFO_CACHE1_ACQUIRE_VALUE                    0x00003268
 472 #define NV10_PFIFO_CACHE1_SEMAPHORE                        0x0000326C
 473 #define NV03_PFIFO_CACHE1_GET                              0x00003270
 474 #define NV04_PFIFO_CACHE1_ENGINE                           0x00003280
 475 #define NV04_PFIFO_CACHE1_DMA_DCOUNT                       0x000032A0
 476 #define NV40_PFIFO_GRCTX_INSTANCE                          0x000032E0
 477 #define NV40_PFIFO_UNK32E4                                 0x000032E4
 478 #define NV04_PFIFO_CACHE1_METHOD(i)                (0x00003800+(i*8))
 479 #define NV04_PFIFO_CACHE1_DATA(i)                  (0x00003804+(i*8))
 480 #define NV40_PFIFO_CACHE1_METHOD(i)                (0x00090000+(i*8))
 481 #define NV40_PFIFO_CACHE1_DATA(i)                  (0x00090004+(i*8))
 482
 483 #define NV_CRTC0_INTSTAT                                   0x00600100
 484 #define NV_CRTC0_INTEN                                     0x00600140
 485 #define NV_CRTC1_INTSTAT                                   0x00602100
 486 #define NV_CRTC1_INTEN                                     0x00602140
 487 #    define NV_CRTC_INTR_VBLANK                                (1<<0)
 488
 489 /* Fifo commands. These are not regs, neither masks */
 490 #define NV03_FIFO_CMD_JUMP                                 0x20000000
 491 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK                     0x1ffffffc
 492 #define NV03_FIFO_CMD_REWIND                               (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
 493
 494 /* RAMFC offsets */
 495 #define NV04_RAMFC_DMA_PUT                                       0x00
 496 #define NV04_RAMFC_DMA_GET                                       0x04
 497 #define NV04_RAMFC_DMA_INSTANCE                                  0x08
 498 #define NV04_RAMFC_DMA_STATE                                     0x0C
 499 #define NV04_RAMFC_DMA_FETCH                                     0x10
 500 #define NV04_RAMFC_ENGINE                                        0x14
 501 #define NV04_RAMFC_PULL1_ENGINE                                  0x18
 502
 503 #define NV10_RAMFC_DMA_PUT                                       0x00
 504 #define NV10_RAMFC_DMA_GET                                       0x04
 505 #define NV10_RAMFC_REF_CNT                                       0x08
 506 #define NV10_RAMFC_DMA_INSTANCE                                  0x0C
 507 #define NV10_RAMFC_DMA_STATE                                     0x10
 508 #define NV10_RAMFC_DMA_FETCH                                     0x14
 509 #define NV10_RAMFC_ENGINE                                        0x18
 510 #define NV10_RAMFC_PULL1_ENGINE                                  0x1C
 511 #define NV10_RAMFC_ACQUIRE_VALUE                                 0x20
 512 #define NV10_RAMFC_ACQUIRE_TIMESTAMP                             0x24
 513 #define NV10_RAMFC_ACQUIRE_TIMEOUT                               0x28
 514 #define NV10_RAMFC_SEMAPHORE                                     0x2C
 515 #define NV10_RAMFC_DMA_SUBROUTINE                                0x30
 516
 517 #define NV40_RAMFC_DMA_PUT                                       0x00
 518 #define NV40_RAMFC_DMA_GET                                       0x04
 519 #define NV40_RAMFC_REF_CNT                                       0x08
 520 #define NV40_RAMFC_DMA_INSTANCE                                  0x0C
 521 #define NV40_RAMFC_DMA_DCOUNT /* ? */                            0x10
 522 #define NV40_RAMFC_DMA_STATE                                     0x14
 523 #define NV40_RAMFC_DMA_FETCH                                     0x18
 524 #define NV40_RAMFC_ENGINE                                        0x1C
 525 #define NV40_RAMFC_PULL1_ENGINE                                  0x20
 526 #define NV40_RAMFC_ACQUIRE_VALUE                                 0x24
 527 #define NV40_RAMFC_ACQUIRE_TIMESTAMP                             0x28
 528 #define NV40_RAMFC_ACQUIRE_TIMEOUT                               0x2C
 529 #define NV40_RAMFC_SEMAPHORE                                     0x30
 530 #define NV40_RAMFC_DMA_SUBROUTINE                                0x34
 531 #define NV40_RAMFC_GRCTX_INSTANCE /* guess */                    0x38
 532 #define NV40_RAMFC_DMA_TIMESLICE                                 0x3C
 533 #define NV40_RAMFC_UNK_40                                        0x40
 534 #define NV40_RAMFC_UNK_44                                        0x44
 535 #define NV40_RAMFC_UNK_48                                        0x48
 536 #define NV40_RAMFC_UNK_4C                                        0x4C
 537 #define NV40_RAMFC_UNK_50                                        0x50
 538