3 #define NV03_BOOT_0 0x00100000
4 # define NV03_BOOT_0_RAM_AMOUNT 0x00000003
5 # define NV03_BOOT_0_RAM_AMOUNT_8MB 0x00000000
6 # define NV03_BOOT_0_RAM_AMOUNT_2MB 0x00000001
7 # define NV03_BOOT_0_RAM_AMOUNT_4MB 0x00000002
8 # define NV03_BOOT_0_RAM_AMOUNT_8MB_SDRAM 0x00000003
9 # define NV04_BOOT_0_RAM_AMOUNT_32MB 0x00000000
10 # define NV04_BOOT_0_RAM_AMOUNT_4MB 0x00000001
11 # define NV04_BOOT_0_RAM_AMOUNT_8MB 0x00000002
12 # define NV04_BOOT_0_RAM_AMOUNT_16MB 0x00000003
14 #define NV04_FIFO_DATA 0x0010020c
15 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK 0xfff00000
16 # define NV10_FIFO_DATA_RAM_AMOUNT_MB_SHIFT 20
18 #define NV03_PGRAPH_STATUS 0x004006b0
19 #define NV04_PGRAPH_STATUS 0x00400700
21 #define NV_RAMIN 0x00700000
23 #define NV_RAMHT_HANDLE_OFFSET 0
24 #define NV_RAMHT_CONTEXT_OFFSET 4
25 # define NV_RAMHT_CONTEXT_VALID (1<<31)
26 # define NV_RAMHT_CONTEXT_CHANNEL_SHIFT 24
27 # define NV_RAMHT_CONTEXT_ENGINE_SHIFT 16
28 # define NV_RAMHT_CONTEXT_ENGINE_SOFTWARE 0
29 # define NV_RAMHT_CONTEXT_ENGINE_GRAPHICS 1
30 # define NV_RAMHT_CONTEXT_INSTANCE_SHIFT 0
31 # define NV40_RAMHT_CONTEXT_CHANNEL_SHIFT 23
32 # define NV40_RAMHT_CONTEXT_ENGINE_SHIFT 20
33 # define NV40_RAMHT_CONTEXT_INSTANCE_SHIFT 0
35 #define NV_DMA_ACCESS_RW 0
36 #define NV_DMA_ACCESS_RO 1
37 #define NV_DMA_ACCESS_WO 2
38 #define NV_DMA_TARGET_VIDMEM 0
39 #define NV_DMA_TARGET_AGP 3
41 #define NV03_FIFO_SIZE 0x8000
42 #define NV_MAX_FIFO_NUMBER 32
43 #define NV03_FIFO_REGS_SIZE 0x10000
44 #define NV03_FIFO_REGS(i) (0x00800000+i*NV03_FIFO_REGS_SIZE)
45 # define NV03_FIFO_REGS_DMAPUT(i) (NV03_FIFO_REGS(i)+0x40)
46 # define NV03_FIFO_REGS_DMAGET(i) (NV03_FIFO_REGS(i)+0x44)
48 #define NV_PMC_INTSTAT 0x00000100
49 # define NV_PMC_INTSTAT_PFIFO_PENDING (1<< 8)
50 # define NV_PMC_INTSTAT_PGRAPH_PENDING (1<<12)
51 # define NV_PMC_INTSTAT_CRTC0_PENDING (1<<24)
52 # define NV_PMC_INTSTAT_CRTC1_PENDING (1<<25)
53 # define NV_PMC_INTSTAT_CRTCn_PENDING (3<<24)
54 #define NV_PMC_INTEN 0x00000140
55 # define NV_PMC_INTEN_MASTER_ENABLE (1<< 0)
57 #define NV_PGRAPH_INTSTAT 0x00400100
58 #define NV04_PGRAPH_INTEN 0x00400140
59 #define NV40_PGRAPH_INTEN 0x0040013C
60 # define NV_PGRAPH_INTR_NOTIFY (1<< 0)
61 # define NV_PGRAPH_INTR_MISSING_HW (1<< 4)
62 # define NV_PGRAPH_INTR_CONTEXT_SWITCH (1<<12)
63 # define NV_PGRAPH_INTR_BUFFER_NOTIFY (1<<16)
64 # define NV_PGRAPH_INTR_ERROR (1<<20)
65 #define NV_PGRAPH_CTX_CONTROL 0x00400144
66 #define NV_PGRAPH_NV40_UNK220 0x00400220
67 # define NV_PGRAPH_NV40_UNK220_FB_INSTANCE
68 #define NV_PGRAPH_CTX_USER 0x00400148
69 #define NV_PGRAPH_CTX_SWITCH1 0x0040014C
70 #define NV_PGRAPH_FIFO 0x00400720
71 #define NV_PGRAPH_FFINTFC_ST2 0x00400764
73 /* It's a guess that this works on NV03. Confirmed on NV04, though */
74 #define NV_PFIFO_DELAY_0 0x00002040
75 #define NV_PFIFO_DMA_TIMESLICE 0x00002044
76 #define NV_PFIFO_INTSTAT 0x00002100
77 #define NV_PFIFO_INTEN 0x00002140
78 # define NV_PFIFO_INTR_ERROR (1<<0)
79 #define NV_PFIFO_RAMHT 0x00002210
80 #define NV_PFIFO_RAMFC 0x00002214
81 #define NV_PFIFO_RAMRO 0x00002218
82 #define NV_PFIFO_CACHES 0x00002500
83 #define NV_PFIFO_MODE 0x00002504
84 #define NV_PFIFO_DMA 0x00002508
85 #define NV_PFIFO_SIZE 0x0000250c
86 #define NV_PFIFO_CACH0_PSH0 0x00003000
87 #define NV_PFIFO_CACH0_PUL0 0x00003050
88 #define NV_PFIFO_CACH0_PUL1 0x00003054
89 #define NV_PFIFO_CACH1_PSH0 0x00003200
90 #define NV_PFIFO_CACH1_PSH1 0x00003204
91 #define NV_PFIFO_CACH1_DMAPSH 0x00003220
92 #define NV_PFIFO_CACH1_DMAF 0x00003224
93 # define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
94 # define NV_PFIFO_CACH1_DMAF_TRIG_8_BYTES 0x00000000
95 # define NV_PFIFO_CACH1_DMAF_TRIG_16_BYTES 0x00000008
96 # define NV_PFIFO_CACH1_DMAF_TRIG_24_BYTES 0x00000010
97 # define NV_PFIFO_CACH1_DMAF_TRIG_32_BYTES 0x00000018
98 # define NV_PFIFO_CACH1_DMAF_TRIG_40_BYTES 0x00000020
99 # define NV_PFIFO_CACH1_DMAF_TRIG_48_BYTES 0x00000028
100 # define NV_PFIFO_CACH1_DMAF_TRIG_56_BYTES 0x00000030
101 # define NV_PFIFO_CACH1_DMAF_TRIG_64_BYTES 0x00000038
102 # define NV_PFIFO_CACH1_DMAF_TRIG_72_BYTES 0x00000040
103 # define NV_PFIFO_CACH1_DMAF_TRIG_80_BYTES 0x00000048
104 # define NV_PFIFO_CACH1_DMAF_TRIG_88_BYTES 0x00000050
105 # define NV_PFIFO_CACH1_DMAF_TRIG_96_BYTES 0x00000058
106 # define NV_PFIFO_CACH1_DMAF_TRIG_104_BYTES 0x00000060
107 # define NV_PFIFO_CACH1_DMAF_TRIG_112_BYTES 0x00000068
108 # define NV_PFIFO_CACH1_DMAF_TRIG_120_BYTES 0x00000070
109 # define NV_PFIFO_CACH1_DMAF_TRIG_128_BYTES 0x00000078
110 # define NV_PFIFO_CACH1_DMAF_TRIG_136_BYTES 0x00000080
111 # define NV_PFIFO_CACH1_DMAF_TRIG_144_BYTES 0x00000088
112 # define NV_PFIFO_CACH1_DMAF_TRIG_152_BYTES 0x00000090
113 # define NV_PFIFO_CACH1_DMAF_TRIG_160_BYTES 0x00000098
114 # define NV_PFIFO_CACH1_DMAF_TRIG_168_BYTES 0x000000A0
115 # define NV_PFIFO_CACH1_DMAF_TRIG_176_BYTES 0x000000A8
116 # define NV_PFIFO_CACH1_DMAF_TRIG_184_BYTES 0x000000B0
117 # define NV_PFIFO_CACH1_DMAF_TRIG_192_BYTES 0x000000B8
118 # define NV_PFIFO_CACH1_DMAF_TRIG_200_BYTES 0x000000C0
119 # define NV_PFIFO_CACH1_DMAF_TRIG_208_BYTES 0x000000C8
120 # define NV_PFIFO_CACH1_DMAF_TRIG_216_BYTES 0x000000D0
121 # define NV_PFIFO_CACH1_DMAF_TRIG_224_BYTES 0x000000D8
122 # define NV_PFIFO_CACH1_DMAF_TRIG_232_BYTES 0x000000E0
123 # define NV_PFIFO_CACH1_DMAF_TRIG_240_BYTES 0x000000E8
124 # define NV_PFIFO_CACH1_DMAF_TRIG_248_BYTES 0x000000F0
125 # define NV_PFIFO_CACH1_DMAF_TRIG_256_BYTES 0x000000F8
126 # define NV_PFIFO_CACH1_DMAF_SIZE 0x0000E000
127 # define NV_PFIFO_CACH1_DMAF_SIZE_32_BYTES 0x00000000
128 # define NV_PFIFO_CACH1_DMAF_SIZE_64_BYTES 0x00002000
129 # define NV_PFIFO_CACH1_DMAF_SIZE_96_BYTES 0x00004000
130 # define NV_PFIFO_CACH1_DMAF_SIZE_128_BYTES 0x00006000
131 # define NV_PFIFO_CACH1_DMAF_SIZE_160_BYTES 0x00008000
132 # define NV_PFIFO_CACH1_DMAF_SIZE_192_BYTES 0x0000A000
133 # define NV_PFIFO_CACH1_DMAF_SIZE_224_BYTES 0x0000C000
134 # define NV_PFIFO_CACH1_DMAF_SIZE_256_BYTES 0x0000E000
135 # define NV_PFIFO_CACH1_DMAF_MAX_REQS 0x001F0000
136 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_0 0x00000000
137 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_1 0x00010000
138 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_2 0x00020000
139 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_3 0x00030000
140 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_4 0x00040000
141 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_5 0x00050000
142 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_6 0x00060000
143 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_7 0x00070000
144 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_8 0x00080000
145 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_9 0x00090000
146 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_10 0x000A0000
147 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_11 0x000B0000
148 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_12 0x000C0000
149 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_13 0x000D0000
150 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_14 0x000E0000
151 # define NV_PFIFO_CACH1_DMAF_MAX_REQS_15 0x000F0000
152 # define NV_PFIFO_CACH1_ENDIAN 0x80000000
153 # define NV_PFIFO_CACH1_LITTLE_ENDIAN 0x7FFFFFFF
154 # define NV_PFIFO_CACH1_BIG_ENDIAN 0x80000000
155 #define NV_PFIFO_CACH1_DMAS 0x00003228
156 #define NV_PFIFO_CACH1_DMAI 0x0000322c
157 #define NV_PFIFO_CACH1_DMAC 0x00003230
158 #define NV_PFIFO_CACH1_DMAP 0x00003240
159 #define NV_PFIFO_CACH1_DMAG 0x00003244
160 #define NV_PFIFO_CACH1_PUL0 0x00003250
161 #define NV_PFIFO_CACH1_PUL1 0x00003254
162 #define NV_PFIFO_CACH1_HASH 0x00003258
163 #define NV_PFIFO_CACH1_ENG 0x00003280
165 #define NV_CRTC0_INTSTAT 0x00600100
166 #define NV_CRTC0_INTEN 0x00600140
167 #define NV_CRTC1_INTSTAT 0x00602100
168 #define NV_CRTC1_INTEN 0x00602140
169 # define NV_CRTC_INTR_VBLANK (1<<0)
171 /* Fifo commands. These are not regs, neither masks */
172 #define NV03_FIFO_CMD_JUMP 0x20000000
173 #define NV03_FIFO_CMD_JUMP_OFFSET_MASK 0x1ffffffc
174 #define NV03_FIFO_CMD_REWIND (NV03_FIFO_CMD_JUMP | (0 & NV03_FIFO_CMD_JUMP_OFFSET_MASK))
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