2 * Copyright 2005 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "drm_sarea.h"
28 #include "nouveau_drv.h"
29 #include "nouveau_drm.h"
31 static int nouveau_init_card_mappings(struct drm_device *dev)
33 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 /* resource 0 is mmio regs */
37 /* resource 1 is linear FB */
38 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
39 /* resource 6 is bios */
41 /* map the mmio regs */
42 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
43 drm_get_resource_len(dev, 0),
44 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
46 DRM_ERROR("Unable to initialize the mmio mapping (%d). "
47 "Please report your setup to " DRIVER_EMAIL "\n",
51 DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);
53 /* map larger RAMIN aperture on NV40 cards */
54 dev_priv->ramin = NULL;
55 if (dev_priv->card_type >= NV_40) {
56 int ramin_resource = 2;
57 if (drm_get_resource_len(dev, ramin_resource) == 0)
61 drm_get_resource_start(dev, ramin_resource),
62 drm_get_resource_len(dev, ramin_resource),
63 _DRM_REGISTERS, _DRM_READ_ONLY,
66 DRM_ERROR("Failed to init RAMIN mapping, "
67 "limited instance memory available\n");
68 dev_priv->ramin = NULL;
72 /* On older cards (or if the above failed), create a map covering
73 * the BAR0 PRAMIN aperture */
74 if (!dev_priv->ramin) {
76 drm_get_resource_start(dev, 0) + NV_RAMIN,
78 _DRM_REGISTERS, _DRM_READ_ONLY,
81 DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
89 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
90 static void nouveau_stub_takedown(struct drm_device *dev) {}
91 static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; }
93 static int nouveau_init_engine_ptrs(struct drm_device *dev)
95 struct drm_nouveau_private *dev_priv = dev->dev_private;
96 struct nouveau_engine *engine = &dev_priv->Engine;
98 switch (dev_priv->chipset & 0xf0) {
100 engine->instmem.init = nv04_instmem_init;
101 engine->instmem.takedown= nv04_instmem_takedown;
102 engine->instmem.populate = nv04_instmem_populate;
103 engine->instmem.clear = nv04_instmem_clear;
104 engine->instmem.bind = nv04_instmem_bind;
105 engine->instmem.unbind = nv04_instmem_unbind;
106 engine->mc.init = nv04_mc_init;
107 engine->mc.takedown = nv04_mc_takedown;
108 engine->timer.init = nv04_timer_init;
109 engine->timer.read = nv04_timer_read;
110 engine->timer.takedown = nv04_timer_takedown;
111 engine->fb.init = nv04_fb_init;
112 engine->fb.takedown = nv04_fb_takedown;
113 engine->graph.init = nv04_graph_init;
114 engine->graph.takedown = nv04_graph_takedown;
115 engine->graph.create_context = nv04_graph_create_context;
116 engine->graph.destroy_context = nv04_graph_destroy_context;
117 engine->graph.load_context = nv04_graph_load_context;
118 engine->graph.save_context = nv04_graph_save_context;
119 engine->fifo.init = nouveau_fifo_init;
120 engine->fifo.takedown = nouveau_stub_takedown;
121 engine->fifo.create_context = nv04_fifo_create_context;
122 engine->fifo.destroy_context = nv04_fifo_destroy_context;
123 engine->fifo.load_context = nv04_fifo_load_context;
124 engine->fifo.save_context = nv04_fifo_save_context;
127 engine->instmem.init = nv04_instmem_init;
128 engine->instmem.takedown= nv04_instmem_takedown;
129 engine->instmem.populate = nv04_instmem_populate;
130 engine->instmem.clear = nv04_instmem_clear;
131 engine->instmem.bind = nv04_instmem_bind;
132 engine->instmem.unbind = nv04_instmem_unbind;
133 engine->mc.init = nv04_mc_init;
134 engine->mc.takedown = nv04_mc_takedown;
135 engine->timer.init = nv04_timer_init;
136 engine->timer.read = nv04_timer_read;
137 engine->timer.takedown = nv04_timer_takedown;
138 engine->fb.init = nv10_fb_init;
139 engine->fb.takedown = nv10_fb_takedown;
140 engine->graph.init = nv10_graph_init;
141 engine->graph.takedown = nv10_graph_takedown;
142 engine->graph.create_context = nv10_graph_create_context;
143 engine->graph.destroy_context = nv10_graph_destroy_context;
144 engine->graph.load_context = nv10_graph_load_context;
145 engine->graph.save_context = nv10_graph_save_context;
146 engine->fifo.init = nouveau_fifo_init;
147 engine->fifo.takedown = nouveau_stub_takedown;
148 engine->fifo.create_context = nv10_fifo_create_context;
149 engine->fifo.destroy_context = nv10_fifo_destroy_context;
150 engine->fifo.load_context = nv10_fifo_load_context;
151 engine->fifo.save_context = nv10_fifo_save_context;
154 engine->instmem.init = nv04_instmem_init;
155 engine->instmem.takedown= nv04_instmem_takedown;
156 engine->instmem.populate = nv04_instmem_populate;
157 engine->instmem.clear = nv04_instmem_clear;
158 engine->instmem.bind = nv04_instmem_bind;
159 engine->instmem.unbind = nv04_instmem_unbind;
160 engine->mc.init = nv04_mc_init;
161 engine->mc.takedown = nv04_mc_takedown;
162 engine->timer.init = nv04_timer_init;
163 engine->timer.read = nv04_timer_read;
164 engine->timer.takedown = nv04_timer_takedown;
165 engine->fb.init = nv10_fb_init;
166 engine->fb.takedown = nv10_fb_takedown;
167 engine->graph.init = nv20_graph_init;
168 engine->graph.takedown = nv20_graph_takedown;
169 engine->graph.create_context = nv20_graph_create_context;
170 engine->graph.destroy_context = nv20_graph_destroy_context;
171 engine->graph.load_context = nv20_graph_load_context;
172 engine->graph.save_context = nv20_graph_save_context;
173 engine->fifo.init = nouveau_fifo_init;
174 engine->fifo.takedown = nouveau_stub_takedown;
175 engine->fifo.create_context = nv10_fifo_create_context;
176 engine->fifo.destroy_context = nv10_fifo_destroy_context;
177 engine->fifo.load_context = nv10_fifo_load_context;
178 engine->fifo.save_context = nv10_fifo_save_context;
181 engine->instmem.init = nv04_instmem_init;
182 engine->instmem.takedown= nv04_instmem_takedown;
183 engine->instmem.populate = nv04_instmem_populate;
184 engine->instmem.clear = nv04_instmem_clear;
185 engine->instmem.bind = nv04_instmem_bind;
186 engine->instmem.unbind = nv04_instmem_unbind;
187 engine->mc.init = nv04_mc_init;
188 engine->mc.takedown = nv04_mc_takedown;
189 engine->timer.init = nv04_timer_init;
190 engine->timer.read = nv04_timer_read;
191 engine->timer.takedown = nv04_timer_takedown;
192 engine->fb.init = nv10_fb_init;
193 engine->fb.takedown = nv10_fb_takedown;
194 engine->graph.init = nv30_graph_init;
195 engine->graph.takedown = nv20_graph_takedown;
196 engine->graph.create_context = nv20_graph_create_context;
197 engine->graph.destroy_context = nv20_graph_destroy_context;
198 engine->graph.load_context = nv20_graph_load_context;
199 engine->graph.save_context = nv20_graph_save_context;
200 engine->fifo.init = nouveau_fifo_init;
201 engine->fifo.takedown = nouveau_stub_takedown;
202 engine->fifo.create_context = nv10_fifo_create_context;
203 engine->fifo.destroy_context = nv10_fifo_destroy_context;
204 engine->fifo.load_context = nv10_fifo_load_context;
205 engine->fifo.save_context = nv10_fifo_save_context;
208 engine->instmem.init = nv04_instmem_init;
209 engine->instmem.takedown= nv04_instmem_takedown;
210 engine->instmem.populate = nv04_instmem_populate;
211 engine->instmem.clear = nv04_instmem_clear;
212 engine->instmem.bind = nv04_instmem_bind;
213 engine->instmem.unbind = nv04_instmem_unbind;
214 engine->mc.init = nv40_mc_init;
215 engine->mc.takedown = nv40_mc_takedown;
216 engine->timer.init = nv04_timer_init;
217 engine->timer.read = nv04_timer_read;
218 engine->timer.takedown = nv04_timer_takedown;
219 engine->fb.init = nv40_fb_init;
220 engine->fb.takedown = nv40_fb_takedown;
221 engine->graph.init = nv40_graph_init;
222 engine->graph.takedown = nv40_graph_takedown;
223 engine->graph.create_context = nv40_graph_create_context;
224 engine->graph.destroy_context = nv40_graph_destroy_context;
225 engine->graph.load_context = nv40_graph_load_context;
226 engine->graph.save_context = nv40_graph_save_context;
227 engine->fifo.init = nv40_fifo_init;
228 engine->fifo.takedown = nouveau_stub_takedown;
229 engine->fifo.create_context = nv40_fifo_create_context;
230 engine->fifo.destroy_context = nv40_fifo_destroy_context;
231 engine->fifo.load_context = nv40_fifo_load_context;
232 engine->fifo.save_context = nv40_fifo_save_context;
235 case 0x80: /* gotta love NVIDIA's consistency.. */
236 engine->instmem.init = nv50_instmem_init;
237 engine->instmem.takedown= nv50_instmem_takedown;
238 engine->instmem.populate = nv50_instmem_populate;
239 engine->instmem.clear = nv50_instmem_clear;
240 engine->instmem.bind = nv50_instmem_bind;
241 engine->instmem.unbind = nv50_instmem_unbind;
242 engine->mc.init = nv50_mc_init;
243 engine->mc.takedown = nv50_mc_takedown;
244 engine->timer.init = nouveau_stub_init;
245 engine->timer.read = nouveau_stub_timer_read;
246 engine->timer.takedown = nouveau_stub_takedown;
247 engine->fb.init = nouveau_stub_init;
248 engine->fb.takedown = nouveau_stub_takedown;
249 engine->graph.init = nv50_graph_init;
250 engine->graph.takedown = nv50_graph_takedown;
251 engine->graph.create_context = nv50_graph_create_context;
252 engine->graph.destroy_context = nv50_graph_destroy_context;
253 engine->graph.load_context = nv50_graph_load_context;
254 engine->graph.save_context = nv50_graph_save_context;
255 engine->fifo.init = nv50_fifo_init;
256 engine->fifo.takedown = nv50_fifo_takedown;
257 engine->fifo.create_context = nv50_fifo_create_context;
258 engine->fifo.destroy_context = nv50_fifo_destroy_context;
259 engine->fifo.load_context = nv50_fifo_load_context;
260 engine->fifo.save_context = nv50_fifo_save_context;
263 DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset);
271 nouveau_card_init(struct drm_device *dev)
273 struct drm_nouveau_private *dev_priv = dev->dev_private;
274 struct nouveau_engine *engine;
277 DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
279 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
283 /* Map any PCI resources we need on the card */
284 ret = nouveau_init_card_mappings(dev);
287 #if defined(__powerpc__)
288 /* Put the card in BE mode if it's not */
289 if (NV_READ(NV03_PMC_BOOT_1))
290 NV_WRITE(NV03_PMC_BOOT_1,0x00000001);
295 /* Determine exact chipset we're running on */
296 if (dev_priv->card_type < NV_10)
297 dev_priv->chipset = dev_priv->card_type;
300 (NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
302 /* Initialise internal driver API hooks */
303 ret = nouveau_init_engine_ptrs(dev);
305 engine = &dev_priv->Engine;
306 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
308 ret = nouveau_gpuobj_early_init(dev);
311 /* Initialise instance memory, must happen before mem_init so we
312 * know exactly how much VRAM we're able to use for "normal"
315 ret = engine->instmem.init(dev);
318 /* Setup the memory manager */
320 ret = nouveau_mem_init_ttm(dev);
323 ret = nouveau_mem_init(dev);
327 ret = nouveau_gpuobj_init(dev);
330 /* Parse BIOS tables / Run init tables? */
333 ret = engine->mc.init(dev);
337 ret = engine->timer.init(dev);
341 ret = engine->fb.init(dev);
345 ret = engine->graph.init(dev);
349 ret = engine->fifo.init(dev);
352 /* this call irq_preinstall, register irq handler and
353 * call irq_postinstall
355 ret = drm_irq_install(dev);
358 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
360 ret = nouveau_dma_channel_init(dev);
363 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
367 static void nouveau_card_takedown(struct drm_device *dev)
369 struct drm_nouveau_private *dev_priv = dev->dev_private;
370 struct nouveau_engine *engine = &dev_priv->Engine;
372 DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
374 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
375 nouveau_dma_channel_takedown(dev);
377 engine->fifo.takedown(dev);
378 engine->graph.takedown(dev);
379 engine->fb.takedown(dev);
380 engine->timer.takedown(dev);
381 engine->mc.takedown(dev);
383 nouveau_sgdma_nottm_hack_takedown(dev);
384 nouveau_sgdma_takedown(dev);
386 nouveau_gpuobj_takedown(dev);
388 nouveau_mem_close(dev);
389 engine->instmem.takedown(dev);
391 drm_irq_uninstall(dev);
393 nouveau_gpuobj_late_takedown(dev);
395 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
399 /* here a client dies, release the stuff that was allocated for its
401 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
403 struct drm_nouveau_private *dev_priv = dev->dev_private;
405 nouveau_fifo_cleanup(dev, file_priv);
406 nouveau_mem_release(file_priv,dev_priv->fb_heap);
407 nouveau_mem_release(file_priv,dev_priv->agp_heap);
408 nouveau_mem_release(file_priv,dev_priv->pci_heap);
411 /* first module load, setup the mmio/fb mapping */
412 int nouveau_firstopen(struct drm_device *dev)
417 int nouveau_load(struct drm_device *dev, unsigned long flags)
419 struct drm_nouveau_private *dev_priv;
422 uint8_t architecture = 0;
424 dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
428 dev_priv->flags = flags & NOUVEAU_FLAGS;
429 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
431 DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class);
433 /* Time to determine the card architecture */
434 regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
436 DRM_ERROR("Could not ioremap to determine register\n");
440 reg0 = readl(regs+NV03_PMC_BOOT_0);
441 reg1 = readl(regs+NV03_PMC_BOOT_1);
442 #if defined(__powerpc__)
444 reg0=___swab32(reg0);
447 /* We're dealing with >=NV10 */
448 if ((reg0 & 0x0f000000) > 0 ) {
449 /* Bit 27-20 contain the architecture in hex */
450 architecture = (reg0 & 0xff00000) >> 20;
452 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
458 if (architecture >= 0x50) {
459 dev_priv->card_type = NV_50;
460 } else if (architecture >= 0x44) {
461 dev_priv->card_type = NV_44;
462 } else if (architecture >= 0x40) {
463 dev_priv->card_type = NV_40;
464 } else if (architecture >= 0x30) {
465 dev_priv->card_type = NV_30;
466 } else if (architecture >= 0x20) {
467 dev_priv->card_type = NV_20;
468 } else if (architecture >= 0x17) {
469 dev_priv->card_type = NV_17;
470 } else if (architecture >= 0x11) {
471 dev_priv->card_type = NV_11;
472 } else if (architecture >= 0x10) {
473 dev_priv->card_type = NV_10;
474 } else if (architecture >= 0x04) {
475 dev_priv->card_type = NV_04;
477 dev_priv->card_type = NV_UNKNOWN;
480 DRM_INFO("Detected an NV%d generation card (0x%08x)\n", dev_priv->card_type,reg0);
482 if (dev_priv->card_type == NV_UNKNOWN) {
487 if (dev->pci_device == 0x01a0) {
488 dev_priv->flags |= NV_NFORCE;
489 } else if (dev->pci_device == 0x01f0) {
490 dev_priv->flags |= NV_NFORCE2;
493 dev->dev_private = (void *)dev_priv;
498 void nouveau_lastclose(struct drm_device *dev)
500 struct drm_nouveau_private *dev_priv = dev->dev_private;
502 /* In the case of an error dev_priv may not be be allocated yet */
503 if (dev_priv && dev_priv->card_type) {
504 nouveau_card_takedown(dev);
506 if(dev_priv->fb_mtrr>0)
508 drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC);
514 int nouveau_unload(struct drm_device *dev)
516 drm_free(dev->dev_private, sizeof(*dev->dev_private), DRM_MEM_DRIVER);
517 dev->dev_private = NULL;
522 nouveau_ioctl_card_init(struct drm_device *dev, void *data,
523 struct drm_file *file_priv)
525 return nouveau_card_init(dev);
528 int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
530 struct drm_nouveau_private *dev_priv = dev->dev_private;
531 struct drm_nouveau_getparam *getparam = data;
533 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
535 switch (getparam->param) {
536 case NOUVEAU_GETPARAM_CHIPSET_ID:
537 getparam->value = dev_priv->chipset;
539 case NOUVEAU_GETPARAM_PCI_VENDOR:
540 getparam->value=dev->pci_vendor;
542 case NOUVEAU_GETPARAM_PCI_DEVICE:
543 getparam->value=dev->pci_device;
545 case NOUVEAU_GETPARAM_BUS_TYPE:
546 if (drm_device_is_agp(dev))
547 getparam->value=NV_AGP;
548 else if (drm_device_is_pcie(dev))
549 getparam->value=NV_PCIE;
551 getparam->value=NV_PCI;
553 case NOUVEAU_GETPARAM_FB_PHYSICAL:
554 getparam->value=dev_priv->fb_phys;
556 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
557 getparam->value=dev_priv->gart_info.aper_base;
559 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
561 getparam->value=(uint64_t) dev->sg->virtual;
564 DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n");
568 case NOUVEAU_GETPARAM_FB_SIZE:
569 getparam->value=dev_priv->fb_available_size;
571 case NOUVEAU_GETPARAM_AGP_SIZE:
572 getparam->value=dev_priv->gart_info.aper_size;
575 DRM_ERROR("unknown parameter %lld\n", getparam->param);
582 int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
584 struct drm_nouveau_private *dev_priv = dev->dev_private;
585 struct drm_nouveau_setparam *setparam = data;
587 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
589 switch (setparam->param) {
590 case NOUVEAU_SETPARAM_CMDBUF_LOCATION:
591 switch (setparam->value) {
592 case NOUVEAU_MEM_AGP:
594 case NOUVEAU_MEM_PCI:
595 case NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI_ACCEPTABLE:
598 DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n",
602 dev_priv->config.cmdbuf.location = setparam->value;
604 case NOUVEAU_SETPARAM_CMDBUF_SIZE:
605 dev_priv->config.cmdbuf.size = setparam->value;
608 DRM_ERROR("unknown parameter %lld\n", setparam->param);
616 void nouveau_wait_for_idle(struct drm_device *dev)
618 struct drm_nouveau_private *dev_priv=dev->dev_private;
619 switch(dev_priv->card_type) {
623 /* This stuff is more or less a copy of what is seen
624 * in nv28 kmmio dump.
626 uint64_t started = dev_priv->Engine.timer.read(dev);
627 uint64_t stopped = started;
630 uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE);
632 status = NV_READ(NV04_PGRAPH_STATUS);
635 stopped = dev_priv->Engine.timer.read(dev);
636 /* It'll never wrap anyway... */
637 } while (stopped - started < 1000000000ULL);
639 DRM_ERROR("timed out with status 0x%08x\n",