2 * Copyright 2005 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "drm_sarea.h"
28 #include "nouveau_drv.h"
29 #include "nouveau_drm.h"
31 static int nouveau_init_card_mappings(struct drm_device *dev)
33 struct drm_nouveau_private *dev_priv = dev->dev_private;
36 /* resource 0 is mmio regs */
37 /* resource 1 is linear FB */
38 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
39 /* resource 6 is bios */
41 /* map the mmio regs */
42 ret = drm_addmap(dev, drm_get_resource_start(dev, 0),
43 drm_get_resource_len(dev, 0),
44 _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
46 DRM_ERROR("Unable to initialize the mmio mapping (%d). "
47 "Please report your setup to " DRIVER_EMAIL "\n",
51 DRM_DEBUG("regs mapped ok at 0x%lx\n", dev_priv->mmio->offset);
53 /* map larger RAMIN aperture on NV40 cards */
54 dev_priv->ramin = NULL;
55 if (dev_priv->card_type >= NV_40) {
56 int ramin_resource = 2;
57 if (drm_get_resource_len(dev, ramin_resource) == 0)
61 drm_get_resource_start(dev, ramin_resource),
62 drm_get_resource_len(dev, ramin_resource),
63 _DRM_REGISTERS, _DRM_READ_ONLY,
66 DRM_ERROR("Failed to init RAMIN mapping, "
67 "limited instance memory available\n");
68 dev_priv->ramin = NULL;
72 /* On older cards (or if the above failed), create a map covering
73 * the BAR0 PRAMIN aperture */
74 if (!dev_priv->ramin) {
76 drm_get_resource_start(dev, 0) + NV_RAMIN,
78 _DRM_REGISTERS, _DRM_READ_ONLY,
81 DRM_ERROR("Failed to map BAR0 PRAMIN: %d\n", ret);
89 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
90 static void nouveau_stub_takedown(struct drm_device *dev) {}
91 static uint64_t nouveau_stub_timer_read(struct drm_device *dev) { return 0; }
93 static int nouveau_init_engine_ptrs(struct drm_device *dev)
95 struct drm_nouveau_private *dev_priv = dev->dev_private;
96 struct nouveau_engine *engine = &dev_priv->Engine;
98 switch (dev_priv->chipset & 0xf0) {
100 engine->instmem.init = nv04_instmem_init;
101 engine->instmem.takedown= nv04_instmem_takedown;
102 engine->instmem.populate = nv04_instmem_populate;
103 engine->instmem.clear = nv04_instmem_clear;
104 engine->instmem.bind = nv04_instmem_bind;
105 engine->instmem.unbind = nv04_instmem_unbind;
106 engine->mc.init = nv04_mc_init;
107 engine->mc.takedown = nv04_mc_takedown;
108 engine->timer.init = nv04_timer_init;
109 engine->timer.read = nv04_timer_read;
110 engine->timer.takedown = nv04_timer_takedown;
111 engine->fb.init = nv04_fb_init;
112 engine->fb.takedown = nv04_fb_takedown;
113 engine->graph.init = nv04_graph_init;
114 engine->graph.takedown = nv04_graph_takedown;
115 engine->graph.create_context = nv04_graph_create_context;
116 engine->graph.destroy_context = nv04_graph_destroy_context;
117 engine->graph.load_context = nv04_graph_load_context;
118 engine->graph.save_context = nv04_graph_save_context;
119 engine->fifo.channels = 16;
120 engine->fifo.init = nouveau_fifo_init;
121 engine->fifo.takedown = nouveau_stub_takedown;
122 engine->fifo.channel_id = nv04_fifo_channel_id;
123 engine->fifo.create_context = nv04_fifo_create_context;
124 engine->fifo.destroy_context = nv04_fifo_destroy_context;
125 engine->fifo.load_context = nv04_fifo_load_context;
126 engine->fifo.save_context = nv04_fifo_save_context;
129 engine->instmem.init = nv04_instmem_init;
130 engine->instmem.takedown= nv04_instmem_takedown;
131 engine->instmem.populate = nv04_instmem_populate;
132 engine->instmem.clear = nv04_instmem_clear;
133 engine->instmem.bind = nv04_instmem_bind;
134 engine->instmem.unbind = nv04_instmem_unbind;
135 engine->mc.init = nv04_mc_init;
136 engine->mc.takedown = nv04_mc_takedown;
137 engine->timer.init = nv04_timer_init;
138 engine->timer.read = nv04_timer_read;
139 engine->timer.takedown = nv04_timer_takedown;
140 engine->fb.init = nv10_fb_init;
141 engine->fb.takedown = nv10_fb_takedown;
142 engine->graph.init = nv10_graph_init;
143 engine->graph.takedown = nv10_graph_takedown;
144 engine->graph.create_context = nv10_graph_create_context;
145 engine->graph.destroy_context = nv10_graph_destroy_context;
146 engine->graph.load_context = nv10_graph_load_context;
147 engine->graph.save_context = nv10_graph_save_context;
148 engine->fifo.channels = 32;
149 engine->fifo.init = nouveau_fifo_init;
150 engine->fifo.takedown = nouveau_stub_takedown;
151 engine->fifo.channel_id = nv10_fifo_channel_id;
152 engine->fifo.create_context = nv10_fifo_create_context;
153 engine->fifo.destroy_context = nv10_fifo_destroy_context;
154 engine->fifo.load_context = nv10_fifo_load_context;
155 engine->fifo.save_context = nv10_fifo_save_context;
158 engine->instmem.init = nv04_instmem_init;
159 engine->instmem.takedown= nv04_instmem_takedown;
160 engine->instmem.populate = nv04_instmem_populate;
161 engine->instmem.clear = nv04_instmem_clear;
162 engine->instmem.bind = nv04_instmem_bind;
163 engine->instmem.unbind = nv04_instmem_unbind;
164 engine->mc.init = nv04_mc_init;
165 engine->mc.takedown = nv04_mc_takedown;
166 engine->timer.init = nv04_timer_init;
167 engine->timer.read = nv04_timer_read;
168 engine->timer.takedown = nv04_timer_takedown;
169 engine->fb.init = nv10_fb_init;
170 engine->fb.takedown = nv10_fb_takedown;
171 engine->graph.init = nv20_graph_init;
172 engine->graph.takedown = nv20_graph_takedown;
173 engine->graph.create_context = nv20_graph_create_context;
174 engine->graph.destroy_context = nv20_graph_destroy_context;
175 engine->graph.load_context = nv20_graph_load_context;
176 engine->graph.save_context = nv20_graph_save_context;
177 engine->fifo.channels = 32;
178 engine->fifo.init = nouveau_fifo_init;
179 engine->fifo.takedown = nouveau_stub_takedown;
180 engine->fifo.channel_id = nv10_fifo_channel_id;
181 engine->fifo.create_context = nv10_fifo_create_context;
182 engine->fifo.destroy_context = nv10_fifo_destroy_context;
183 engine->fifo.load_context = nv10_fifo_load_context;
184 engine->fifo.save_context = nv10_fifo_save_context;
187 engine->instmem.init = nv04_instmem_init;
188 engine->instmem.takedown= nv04_instmem_takedown;
189 engine->instmem.populate = nv04_instmem_populate;
190 engine->instmem.clear = nv04_instmem_clear;
191 engine->instmem.bind = nv04_instmem_bind;
192 engine->instmem.unbind = nv04_instmem_unbind;
193 engine->mc.init = nv04_mc_init;
194 engine->mc.takedown = nv04_mc_takedown;
195 engine->timer.init = nv04_timer_init;
196 engine->timer.read = nv04_timer_read;
197 engine->timer.takedown = nv04_timer_takedown;
198 engine->fb.init = nv10_fb_init;
199 engine->fb.takedown = nv10_fb_takedown;
200 engine->graph.init = nv30_graph_init;
201 engine->graph.takedown = nv20_graph_takedown;
202 engine->graph.create_context = nv20_graph_create_context;
203 engine->graph.destroy_context = nv20_graph_destroy_context;
204 engine->graph.load_context = nv20_graph_load_context;
205 engine->graph.save_context = nv20_graph_save_context;
206 engine->fifo.channels = 32;
207 engine->fifo.init = nouveau_fifo_init;
208 engine->fifo.takedown = nouveau_stub_takedown;
209 engine->fifo.channel_id = nv10_fifo_channel_id;
210 engine->fifo.create_context = nv10_fifo_create_context;
211 engine->fifo.destroy_context = nv10_fifo_destroy_context;
212 engine->fifo.load_context = nv10_fifo_load_context;
213 engine->fifo.save_context = nv10_fifo_save_context;
216 engine->instmem.init = nv04_instmem_init;
217 engine->instmem.takedown= nv04_instmem_takedown;
218 engine->instmem.populate = nv04_instmem_populate;
219 engine->instmem.clear = nv04_instmem_clear;
220 engine->instmem.bind = nv04_instmem_bind;
221 engine->instmem.unbind = nv04_instmem_unbind;
222 engine->mc.init = nv40_mc_init;
223 engine->mc.takedown = nv40_mc_takedown;
224 engine->timer.init = nv04_timer_init;
225 engine->timer.read = nv04_timer_read;
226 engine->timer.takedown = nv04_timer_takedown;
227 engine->fb.init = nv40_fb_init;
228 engine->fb.takedown = nv40_fb_takedown;
229 engine->graph.init = nv40_graph_init;
230 engine->graph.takedown = nv40_graph_takedown;
231 engine->graph.create_context = nv40_graph_create_context;
232 engine->graph.destroy_context = nv40_graph_destroy_context;
233 engine->graph.load_context = nv40_graph_load_context;
234 engine->graph.save_context = nv40_graph_save_context;
235 engine->fifo.channels = 32;
236 engine->fifo.init = nv40_fifo_init;
237 engine->fifo.takedown = nouveau_stub_takedown;
238 engine->fifo.channel_id = nv10_fifo_channel_id;
239 engine->fifo.create_context = nv40_fifo_create_context;
240 engine->fifo.destroy_context = nv40_fifo_destroy_context;
241 engine->fifo.load_context = nv40_fifo_load_context;
242 engine->fifo.save_context = nv40_fifo_save_context;
245 case 0x80: /* gotta love NVIDIA's consistency.. */
246 engine->instmem.init = nv50_instmem_init;
247 engine->instmem.takedown= nv50_instmem_takedown;
248 engine->instmem.populate = nv50_instmem_populate;
249 engine->instmem.clear = nv50_instmem_clear;
250 engine->instmem.bind = nv50_instmem_bind;
251 engine->instmem.unbind = nv50_instmem_unbind;
252 engine->mc.init = nv50_mc_init;
253 engine->mc.takedown = nv50_mc_takedown;
254 engine->timer.init = nouveau_stub_init;
255 engine->timer.read = nouveau_stub_timer_read;
256 engine->timer.takedown = nouveau_stub_takedown;
257 engine->fb.init = nouveau_stub_init;
258 engine->fb.takedown = nouveau_stub_takedown;
259 engine->graph.init = nv50_graph_init;
260 engine->graph.takedown = nv50_graph_takedown;
261 engine->graph.create_context = nv50_graph_create_context;
262 engine->graph.destroy_context = nv50_graph_destroy_context;
263 engine->graph.load_context = nv50_graph_load_context;
264 engine->graph.save_context = nv50_graph_save_context;
265 engine->fifo.channels = 128;
266 engine->fifo.init = nv50_fifo_init;
267 engine->fifo.takedown = nv50_fifo_takedown;
268 engine->fifo.channel_id = nv50_fifo_channel_id;
269 engine->fifo.create_context = nv50_fifo_create_context;
270 engine->fifo.destroy_context = nv50_fifo_destroy_context;
271 engine->fifo.load_context = nv50_fifo_load_context;
272 engine->fifo.save_context = nv50_fifo_save_context;
275 DRM_ERROR("NV%02x unsupported\n", dev_priv->chipset);
283 nouveau_card_init(struct drm_device *dev)
285 struct drm_nouveau_private *dev_priv = dev->dev_private;
286 struct nouveau_engine *engine;
288 #if defined(__powerpc__)
289 struct device_node *dn;
292 DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
294 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
298 /* Map any PCI resources we need on the card */
299 ret = nouveau_init_card_mappings(dev);
302 #if defined(__powerpc__)
303 /* Put the card in BE mode if it's not */
304 if (NV_READ(NV03_PMC_BOOT_1))
305 NV_WRITE(NV03_PMC_BOOT_1,0x00000001);
310 #if defined(__linux__) && defined(__powerpc__)
311 /* if we have an OF card, copy vbios to RAMIN */
312 dn = pci_device_to_OF_node(dev->pdev);
316 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22))
317 const uint32_t *bios = of_get_property(dn, "NVDA,BMP", &size);
319 const uint32_t *bios = get_property(dn, "NVDA,BMP", &size);
325 NV_WI32(i, bios[i/4]);
326 DRM_INFO("OF bios successfully copied\n");
329 DRM_INFO("Unable to get the OF bios\n");
332 DRM_INFO("Unable to get the OF node\n");
335 /* Determine exact chipset we're running on */
336 if (dev_priv->card_type < NV_10)
337 dev_priv->chipset = dev_priv->card_type;
340 (NV_READ(NV03_PMC_BOOT_0) & 0x0ff00000) >> 20;
342 /* Initialise internal driver API hooks */
343 ret = nouveau_init_engine_ptrs(dev);
345 engine = &dev_priv->Engine;
346 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
348 ret = nouveau_gpuobj_early_init(dev);
351 /* Initialise instance memory, must happen before mem_init so we
352 * know exactly how much VRAM we're able to use for "normal"
355 ret = engine->instmem.init(dev);
358 /* Setup the memory manager */
360 ret = nouveau_mem_init_ttm(dev);
363 ret = nouveau_mem_init(dev);
367 ret = nouveau_gpuobj_init(dev);
370 /* Parse BIOS tables / Run init tables? */
373 ret = engine->mc.init(dev);
377 ret = engine->timer.init(dev);
381 ret = engine->fb.init(dev);
385 ret = engine->graph.init(dev);
389 ret = engine->fifo.init(dev);
392 /* this call irq_preinstall, register irq handler and
393 * call irq_postinstall
395 ret = drm_irq_install(dev);
398 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
400 ret = nouveau_dma_channel_init(dev);
403 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
407 static void nouveau_card_takedown(struct drm_device *dev)
409 struct drm_nouveau_private *dev_priv = dev->dev_private;
410 struct nouveau_engine *engine = &dev_priv->Engine;
412 DRM_DEBUG("prev state = %d\n", dev_priv->init_state);
414 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
415 nouveau_dma_channel_takedown(dev);
417 engine->fifo.takedown(dev);
418 engine->graph.takedown(dev);
419 engine->fb.takedown(dev);
420 engine->timer.takedown(dev);
421 engine->mc.takedown(dev);
423 nouveau_sgdma_nottm_hack_takedown(dev);
424 nouveau_sgdma_takedown(dev);
426 nouveau_gpuobj_takedown(dev);
428 nouveau_mem_close(dev);
429 engine->instmem.takedown(dev);
431 drm_irq_uninstall(dev);
433 nouveau_gpuobj_late_takedown(dev);
435 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
439 /* here a client dies, release the stuff that was allocated for its
441 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
443 struct drm_nouveau_private *dev_priv = dev->dev_private;
445 nouveau_fifo_cleanup(dev, file_priv);
446 nouveau_mem_release(file_priv,dev_priv->fb_heap);
447 nouveau_mem_release(file_priv,dev_priv->agp_heap);
448 nouveau_mem_release(file_priv,dev_priv->pci_heap);
451 /* first module load, setup the mmio/fb mapping */
452 int nouveau_firstopen(struct drm_device *dev)
457 int nouveau_load(struct drm_device *dev, unsigned long flags)
459 struct drm_nouveau_private *dev_priv;
462 uint8_t architecture = 0;
464 dev_priv = drm_calloc(1, sizeof(*dev_priv), DRM_MEM_DRIVER);
468 dev_priv->flags = flags & NOUVEAU_FLAGS;
469 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
471 DRM_DEBUG("vendor: 0x%X device: 0x%X class: 0x%X\n", dev->pci_vendor, dev->pci_device, dev->pdev->class);
473 /* Time to determine the card architecture */
474 regs = ioremap_nocache(pci_resource_start(dev->pdev, 0), 0x8);
476 DRM_ERROR("Could not ioremap to determine register\n");
480 reg0 = readl(regs+NV03_PMC_BOOT_0);
481 reg1 = readl(regs+NV03_PMC_BOOT_1);
482 #if defined(__powerpc__)
484 reg0=___swab32(reg0);
487 /* We're dealing with >=NV10 */
488 if ((reg0 & 0x0f000000) > 0 ) {
489 /* Bit 27-20 contain the architecture in hex */
490 architecture = (reg0 & 0xff00000) >> 20;
492 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
498 if (architecture >= 0x50) {
499 dev_priv->card_type = NV_50;
500 } else if (architecture >= 0x44) {
501 dev_priv->card_type = NV_44;
502 } else if (architecture >= 0x40) {
503 dev_priv->card_type = NV_40;
504 } else if (architecture >= 0x30) {
505 dev_priv->card_type = NV_30;
506 } else if (architecture >= 0x20) {
507 dev_priv->card_type = NV_20;
508 } else if (architecture >= 0x17) {
509 dev_priv->card_type = NV_17;
510 } else if (architecture >= 0x11) {
511 dev_priv->card_type = NV_11;
512 } else if (architecture >= 0x10) {
513 dev_priv->card_type = NV_10;
514 } else if (architecture >= 0x04) {
515 dev_priv->card_type = NV_04;
517 dev_priv->card_type = NV_UNKNOWN;
520 DRM_INFO("Detected an NV%d generation card (0x%08x)\n", dev_priv->card_type,reg0);
522 if (dev_priv->card_type == NV_UNKNOWN) {
527 if (dev->pci_device == 0x01a0) {
528 dev_priv->flags |= NV_NFORCE;
529 } else if (dev->pci_device == 0x01f0) {
530 dev_priv->flags |= NV_NFORCE2;
533 dev->dev_private = (void *)dev_priv;
538 void nouveau_lastclose(struct drm_device *dev)
540 struct drm_nouveau_private *dev_priv = dev->dev_private;
542 /* In the case of an error dev_priv may not be be allocated yet */
543 if (dev_priv && dev_priv->card_type) {
544 nouveau_card_takedown(dev);
546 if(dev_priv->fb_mtrr>0)
548 drm_mtrr_del(dev_priv->fb_mtrr, drm_get_resource_start(dev, 1),nouveau_mem_fb_amount(dev), DRM_MTRR_WC);
554 int nouveau_unload(struct drm_device *dev)
556 drm_free(dev->dev_private, sizeof(*dev->dev_private), DRM_MEM_DRIVER);
557 dev->dev_private = NULL;
562 nouveau_ioctl_card_init(struct drm_device *dev, void *data,
563 struct drm_file *file_priv)
565 return nouveau_card_init(dev);
568 int nouveau_ioctl_getparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
570 struct drm_nouveau_private *dev_priv = dev->dev_private;
571 struct drm_nouveau_getparam *getparam = data;
573 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
575 switch (getparam->param) {
576 case NOUVEAU_GETPARAM_CHIPSET_ID:
577 getparam->value = dev_priv->chipset;
579 case NOUVEAU_GETPARAM_PCI_VENDOR:
580 getparam->value=dev->pci_vendor;
582 case NOUVEAU_GETPARAM_PCI_DEVICE:
583 getparam->value=dev->pci_device;
585 case NOUVEAU_GETPARAM_BUS_TYPE:
586 if (drm_device_is_agp(dev))
587 getparam->value=NV_AGP;
588 else if (drm_device_is_pcie(dev))
589 getparam->value=NV_PCIE;
591 getparam->value=NV_PCI;
593 case NOUVEAU_GETPARAM_FB_PHYSICAL:
594 getparam->value=dev_priv->fb_phys;
596 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
597 getparam->value=dev_priv->gart_info.aper_base;
599 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
601 getparam->value=(uint64_t) dev->sg->virtual;
604 DRM_ERROR("Requested PCIGART address, while no PCIGART was created\n");
608 case NOUVEAU_GETPARAM_FB_SIZE:
609 getparam->value=dev_priv->fb_available_size;
611 case NOUVEAU_GETPARAM_AGP_SIZE:
612 getparam->value=dev_priv->gart_info.aper_size;
615 DRM_ERROR("unknown parameter %lld\n", getparam->param);
622 int nouveau_ioctl_setparam(struct drm_device *dev, void *data, struct drm_file *file_priv)
624 struct drm_nouveau_private *dev_priv = dev->dev_private;
625 struct drm_nouveau_setparam *setparam = data;
627 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
629 switch (setparam->param) {
630 case NOUVEAU_SETPARAM_CMDBUF_LOCATION:
631 switch (setparam->value) {
632 case NOUVEAU_MEM_AGP:
634 case NOUVEAU_MEM_PCI:
635 case NOUVEAU_MEM_AGP | NOUVEAU_MEM_PCI_ACCEPTABLE:
638 DRM_ERROR("invalid CMDBUF_LOCATION value=%lld\n",
642 dev_priv->config.cmdbuf.location = setparam->value;
644 case NOUVEAU_SETPARAM_CMDBUF_SIZE:
645 dev_priv->config.cmdbuf.size = setparam->value;
648 DRM_ERROR("unknown parameter %lld\n", setparam->param);
656 void nouveau_wait_for_idle(struct drm_device *dev)
658 struct drm_nouveau_private *dev_priv=dev->dev_private;
659 switch(dev_priv->card_type) {
663 /* This stuff is more or less a copy of what is seen
664 * in nv28 kmmio dump.
666 uint64_t started = dev_priv->Engine.timer.read(dev);
667 uint64_t stopped = started;
670 uint32_t pmc_e = NV_READ(NV03_PMC_ENABLE);
672 status = NV_READ(NV04_PGRAPH_STATUS);
675 stopped = dev_priv->Engine.timer.read(dev);
676 /* It'll never wrap anyway... */
677 } while (stopped - started < 1000000000ULL);
679 DRM_ERROR("timed out with status 0x%08x\n",