shared-core/nv04_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
  32                                          NV04_RAMFC_##offset/4, (val))
  33 #define RAMFC_RD(offset)     INSTANCE_RD(chan->ramfc->gpuobj, \
  34                                          NV04_RAMFC_##offset/4)
  35 #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
  36 #define NV04_RAMFC__SIZE 32
  37
  38 int
  39 nv04_fifo_channel_id(struct drm_device *dev)
  40 {
  41         struct drm_nouveau_private *dev_priv = dev->dev_private;
  42
  43         return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
  44                         NV03_PFIFO_CACHE1_PUSH1_CHID_MASK);
  45 }
  46
  47 int
  48 nv04_fifo_create_context(struct nouveau_channel *chan)
  49 {
  50         struct drm_device *dev = chan->dev;
  51         struct drm_nouveau_private *dev_priv = dev->dev_private;
  52         int ret;
  53
  54         if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id), ~0,
  55                                                 NV04_RAMFC__SIZE,
  56                                                 NVOBJ_FLAG_ZERO_ALLOC |
  57                                                 NVOBJ_FLAG_ZERO_FREE,
  58                                                 NULL, &chan->ramfc)))
  59                 return ret;
  60
  61         /* Setup initial state */
  62         RAMFC_WR(DMA_PUT, chan->pushbuf_base);
  63         RAMFC_WR(DMA_GET, chan->pushbuf_base);
  64         RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4);
  65         RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
  66                              NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  67                              NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
  68 #ifdef __BIG_ENDIAN
  69                              NV_PFIFO_CACHE1_BIG_ENDIAN |
  70 #endif
  71                              0));
  72
  73         /* enable the fifo dma operation */
  74         NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id));
  75         return 0;
  76 }
  77
  78 void
  79 nv04_fifo_destroy_context(struct nouveau_channel *chan)
  80 {
  81         struct drm_device *dev = chan->dev;
  82         struct drm_nouveau_private *dev_priv = dev->dev_private;
  83
  84         NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
  85
  86         nouveau_gpuobj_ref_del(dev, &chan->ramfc);
  87 }
  88
  89 int
  90 nv04_fifo_load_context(struct nouveau_channel *chan)
  91 {
  92         struct drm_device *dev = chan->dev;
  93         struct drm_nouveau_private *dev_priv = dev->dev_private;
  94         uint32_t tmp;
  95
  96         NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
  97                  NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
  98
  99         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
 100         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
 101
 102         tmp = RAMFC_RD(DMA_INSTANCE);
 103         NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
 104         NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
 105
 106         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
 107         NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
 108         NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
 109         NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));
 110
 111         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 112         tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
 113         NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 114
 115         return 0;
 116 }
 117
 118 int
 119 nv04_fifo_save_context(struct nouveau_channel *chan)
 120 {
 121         struct drm_device *dev = chan->dev;
 122         struct drm_nouveau_private *dev_priv = dev->dev_private;
 123         uint32_t tmp;
 124
 125         RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);
 126         RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET);
 127
 128         tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
 129         tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE);
 130         RAMFC_WR(DMA_INSTANCE, tmp);
 131
 132         RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 133         RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
 134         RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 135         RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));
 136
 137         return 0;
 138 }