2 * Copyright (C) 2007 Ben Skeggs.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "nouveau_drv.h"
31 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
32 NV04_RAMFC_##offset/4, (val))
33 #define RAMFC_RD(offset) INSTANCE_RD(chan->ramfc->gpuobj, \
34 NV04_RAMFC_##offset/4)
35 #define NV04_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV04_RAMFC__SIZE))
36 #define NV04_RAMFC__SIZE 32
39 nv04_fifo_create_context(struct nouveau_channel *chan)
41 struct drm_device *dev = chan->dev;
42 struct drm_nouveau_private *dev_priv = dev->dev_private;
45 if ((ret = nouveau_gpuobj_new_fake(dev, NV04_RAMFC(chan->id),
47 NVOBJ_FLAG_ZERO_ALLOC |
52 /* Setup initial state */
53 RAMFC_WR(DMA_PUT, chan->pushbuf_base);
54 RAMFC_WR(DMA_GET, chan->pushbuf_base);
55 RAMFC_WR(DMA_INSTANCE, chan->pushbuf->instance >> 4);
56 RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
57 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
58 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
60 NV_PFIFO_CACHE1_BIG_ENDIAN |
64 /* enable the fifo dma operation */
65 NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE) | (1<<chan->id));
70 nv04_fifo_destroy_context(struct nouveau_channel *chan)
72 struct drm_device *dev = chan->dev;
73 struct drm_nouveau_private *dev_priv = dev->dev_private;
75 NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
77 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
81 nv04_fifo_load_context(struct nouveau_channel *chan)
83 struct drm_device *dev = chan->dev;
84 struct drm_nouveau_private *dev_priv = dev->dev_private;
87 NV_WRITE(NV03_PFIFO_CACHE1_PUSH1, (1<<8) | chan->id);
89 NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET, RAMFC_RD(DMA_GET));
90 NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT, RAMFC_RD(DMA_PUT));
92 tmp = RAMFC_RD(DMA_INSTANCE);
93 NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
94 NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
96 NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE, RAMFC_RD(DMA_STATE));
97 NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH, RAMFC_RD(DMA_FETCH));
98 NV_WRITE(NV04_PFIFO_CACHE1_ENGINE, RAMFC_RD(ENGINE));
99 NV_WRITE(NV04_PFIFO_CACHE1_PULL1, RAMFC_RD(PULL1_ENGINE));
101 /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
102 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
103 NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
109 nv04_fifo_save_context(struct nouveau_channel *chan)
111 struct drm_device *dev = chan->dev;
112 struct drm_nouveau_private *dev_priv = dev->dev_private;
115 RAMFC_WR(DMA_PUT, NV04_PFIFO_CACHE1_DMA_PUT);
116 RAMFC_WR(DMA_GET, NV04_PFIFO_CACHE1_DMA_GET);
118 tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16;
119 tmp |= NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE);
120 RAMFC_WR(DMA_INSTANCE, tmp);
122 RAMFC_WR(DMA_STATE, NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
123 RAMFC_WR(DMA_FETCH, NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
124 RAMFC_WR(ENGINE, NV_READ(NV04_PFIFO_CACHE1_ENGINE));
125 RAMFC_WR(PULL1_ENGINE, NV_READ(NV04_PFIFO_CACHE1_PULL1));