shared-core/nv04_graph.c

   1 /*
   2  * Copyright 2007 Stephane Marchesin
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drm.h"
  28 #include "nouveau_drv.h"
  29
  30 struct reg_interval
  31 {
  32         uint32_t reg;
  33         int number;
  34 } nv04_graph_ctx_regs [] = {
  35         {NV04_PGRAPH_CTX_SWITCH1,1},
  36         {NV04_PGRAPH_CTX_SWITCH2,1},
  37         {NV04_PGRAPH_CTX_SWITCH3,1},
  38         {NV04_PGRAPH_CTX_SWITCH4,1},
  39         {NV04_PGRAPH_CTX_CACHE1,1},
  40         {NV04_PGRAPH_CTX_CACHE2,1},
  41         {NV04_PGRAPH_CTX_CACHE3,1},
  42         {NV04_PGRAPH_CTX_CACHE4,1},
  43         {0x00400184,1},
  44         {0x004001a4,1},
  45         {0x004001c4,1},
  46         {0x004001e4,1},
  47         {0x00400188,1},
  48         {0x004001a8,1},
  49         {0x004001c8,1},
  50         {0x004001e8,1},
  51         {0x0040018c,1},
  52         {0x004001ac,1},
  53         {0x004001cc,1},
  54         {0x004001ec,1},
  55         {0x00400190,1},
  56         {0x004001b0,1},
  57         {0x004001d0,1},
  58         {0x004001f0,1},
  59         {0x00400194,1},
  60         {0x004001b4,1},
  61         {0x004001d4,1},
  62         {0x004001f4,1},
  63         {0x00400198,1},
  64         {0x004001b8,1},
  65         {0x004001d8,1},
  66         {0x004001f8,1},
  67         {0x0040019c,1},
  68         {0x004001bc,1},
  69         {0x004001dc,1},
  70         {0x004001fc,1},
  71         {0x00400174,1},
  72         {NV04_PGRAPH_DMA_START_0,1},
  73         {NV04_PGRAPH_DMA_START_1,1},
  74         {NV04_PGRAPH_DMA_LENGTH,1},
  75         {NV04_PGRAPH_DMA_MISC,1},
  76         {NV04_PGRAPH_DMA_PITCH,1},
  77         {NV04_PGRAPH_BOFFSET0,1},
  78         {NV04_PGRAPH_BBASE0,1},
  79         {NV04_PGRAPH_BLIMIT0,1},
  80         {NV04_PGRAPH_BOFFSET1,1},
  81         {NV04_PGRAPH_BBASE1,1},
  82         {NV04_PGRAPH_BLIMIT1,1},
  83         {NV04_PGRAPH_BOFFSET2,1},
  84         {NV04_PGRAPH_BBASE2,1},
  85         {NV04_PGRAPH_BLIMIT2,1},
  86         {NV04_PGRAPH_BOFFSET3,1},
  87         {NV04_PGRAPH_BBASE3,1},
  88         {NV04_PGRAPH_BLIMIT3,1},
  89         {NV04_PGRAPH_BOFFSET4,1},
  90         {NV04_PGRAPH_BBASE4,1},
  91         {NV04_PGRAPH_BLIMIT4,1},
  92         {NV04_PGRAPH_BOFFSET5,1},
  93         {NV04_PGRAPH_BBASE5,1},
  94         {NV04_PGRAPH_BLIMIT5,1},
  95         {NV04_PGRAPH_BPITCH0,1},
  96         {NV04_PGRAPH_BPITCH1,1},
  97         {NV04_PGRAPH_BPITCH2,1},
  98         {NV04_PGRAPH_BPITCH3,1},
  99         {NV04_PGRAPH_BPITCH4,1},
 100         {NV04_PGRAPH_SURFACE,1},
 101         {NV04_PGRAPH_STATE,1},
 102         {NV04_PGRAPH_BSWIZZLE2,1},
 103         {NV04_PGRAPH_BSWIZZLE5,1},
 104         {NV04_PGRAPH_BPIXEL,1},
 105         {NV04_PGRAPH_NOTIFY,1},
 106         {NV04_PGRAPH_PATT_COLOR0,1},
 107         {NV04_PGRAPH_PATT_COLOR1,1},
 108         {NV04_PGRAPH_PATT_COLORRAM,64},
 109         {NV04_PGRAPH_PATTERN,1},
 110         {0x0040080c,1},
 111         {NV04_PGRAPH_PATTERN_SHAPE,1},
 112         {0x00400600,1},
 113         {NV04_PGRAPH_ROP3,1},
 114         {NV04_PGRAPH_CHROMA,1},
 115         {NV04_PGRAPH_BETA_AND,1},
 116         {NV04_PGRAPH_BETA_PREMULT,1},
 117         {NV04_PGRAPH_CONTROL0,1},
 118         {NV04_PGRAPH_CONTROL1,1},
 119         {NV04_PGRAPH_CONTROL2,1},
 120         {NV04_PGRAPH_BLEND,1},
 121         {NV04_PGRAPH_STORED_FMT,1},
 122         {NV04_PGRAPH_SOURCE_COLOR,1},
 123         {0x00400560,1},
 124         {0x00400568,1},
 125         {0x00400564,1},
 126         {0x0040056c,1},
 127         {0x00400400,1},
 128         {0x00400480,1},
 129         {0x00400404,1},
 130         {0x00400484,1},
 131         {0x00400408,1},
 132         {0x00400488,1},
 133         {0x0040040c,1},
 134         {0x0040048c,1},
 135         {0x00400410,1},
 136         {0x00400490,1},
 137         {0x00400414,1},
 138         {0x00400494,1},
 139         {0x00400418,1},
 140         {0x00400498,1},
 141         {0x0040041c,1},
 142         {0x0040049c,1},
 143         {0x00400420,1},
 144         {0x004004a0,1},
 145         {0x00400424,1},
 146         {0x004004a4,1},
 147         {0x00400428,1},
 148         {0x004004a8,1},
 149         {0x0040042c,1},
 150         {0x004004ac,1},
 151         {0x00400430,1},
 152         {0x004004b0,1},
 153         {0x00400434,1},
 154         {0x004004b4,1},
 155         {0x00400438,1},
 156         {0x004004b8,1},
 157         {0x0040043c,1},
 158         {0x004004bc,1},
 159         {0x00400440,1},
 160         {0x004004c0,1},
 161         {0x00400444,1},
 162         {0x004004c4,1},
 163         {0x00400448,1},
 164         {0x004004c8,1},
 165         {0x0040044c,1},
 166         {0x004004cc,1},
 167         {0x00400450,1},
 168         {0x004004d0,1},
 169         {0x00400454,1},
 170         {0x004004d4,1},
 171         {0x00400458,1},
 172         {0x004004d8,1},
 173         {0x0040045c,1},
 174         {0x004004dc,1},
 175         {0x00400460,1},
 176         {0x004004e0,1},
 177         {0x00400464,1},
 178         {0x004004e4,1},
 179         {0x00400468,1},
 180         {0x004004e8,1},
 181         {0x0040046c,1},
 182         {0x004004ec,1},
 183         {0x00400470,1},
 184         {0x004004f0,1},
 185         {0x00400474,1},
 186         {0x004004f4,1},
 187         {0x00400478,1},
 188         {0x004004f8,1},
 189         {0x0040047c,1},
 190         {0x004004fc,1},
 191         {0x0040053c,1},
 192         {0x00400544,1},
 193         {0x00400540,1},
 194         {0x00400548,1},
 195         {0x00400560,1},
 196         {0x00400568,1},
 197         {0x00400564,1},
 198         {0x0040056c,1},
 199         {0x00400534,1},
 200         {0x00400538,1},
 201         {0x00400514,1},
 202         {0x00400518,1},
 203         {0x0040051c,1},
 204         {0x00400520,1},
 205         {0x00400524,1},
 206         {0x00400528,1},
 207         {0x0040052c,1},
 208         {0x00400530,1},
 209         {0x00400d00,1},
 210         {0x00400d40,1},
 211         {0x00400d80,1},
 212         {0x00400d04,1},
 213         {0x00400d44,1},
 214         {0x00400d84,1},
 215         {0x00400d08,1},
 216         {0x00400d48,1},
 217         {0x00400d88,1},
 218         {0x00400d0c,1},
 219         {0x00400d4c,1},
 220         {0x00400d8c,1},
 221         {0x00400d10,1},
 222         {0x00400d50,1},
 223         {0x00400d90,1},
 224         {0x00400d14,1},
 225         {0x00400d54,1},
 226         {0x00400d94,1},
 227         {0x00400d18,1},
 228         {0x00400d58,1},
 229         {0x00400d98,1},
 230         {0x00400d1c,1},
 231         {0x00400d5c,1},
 232         {0x00400d9c,1},
 233         {0x00400d20,1},
 234         {0x00400d60,1},
 235         {0x00400da0,1},
 236         {0x00400d24,1},
 237         {0x00400d64,1},
 238         {0x00400da4,1},
 239         {0x00400d28,1},
 240         {0x00400d68,1},
 241         {0x00400da8,1},
 242         {0x00400d2c,1},
 243         {0x00400d6c,1},
 244         {0x00400dac,1},
 245         {0x00400d30,1},
 246         {0x00400d70,1},
 247         {0x00400db0,1},
 248         {0x00400d34,1},
 249         {0x00400d74,1},
 250         {0x00400db4,1},
 251         {0x00400d38,1},
 252         {0x00400d78,1},
 253         {0x00400db8,1},
 254         {0x00400d3c,1},
 255         {0x00400d7c,1},
 256         {0x00400dbc,1},
 257         {0x00400590,1},
 258         {0x00400594,1},
 259         {0x00400598,1},
 260         {0x0040059c,1},
 261         {0x004005a8,1},
 262         {0x004005ac,1},
 263         {0x004005b0,1},
 264         {0x004005b4,1},
 265         {0x004005c0,1},
 266         {0x004005c4,1},
 267         {0x004005c8,1},
 268         {0x004005cc,1},
 269         {0x004005d0,1},
 270         {0x004005d4,1},
 271         {0x004005d8,1},
 272         {0x004005dc,1},
 273         {0x004005e0,1},
 274         {NV04_PGRAPH_PASSTHRU_0,1},
 275         {NV04_PGRAPH_PASSTHRU_1,1},
 276         {NV04_PGRAPH_PASSTHRU_2,1},
 277         {NV04_PGRAPH_DVD_COLORFMT,1},
 278         {NV04_PGRAPH_SCALED_FORMAT,1},
 279         {NV04_PGRAPH_MISC24_0,1},
 280         {NV04_PGRAPH_MISC24_1,1},
 281         {NV04_PGRAPH_MISC24_2,1},
 282         {0x00400500,1},
 283         {0x00400504,1},
 284         {NV04_PGRAPH_VALID1,1},
 285         {NV04_PGRAPH_VALID2,1}
 286
 287
 288 };
 289
 290 void nouveau_nv04_context_switch(drm_device_t *dev)
 291 {
 292         drm_nouveau_private_t *dev_priv = dev->dev_private;
 293         int channel, channel_old, i, j, index;
 294
 295         channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
 296         channel_old = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
 297
 298         DRM_DEBUG("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
 299
 300         NV_WRITE(NV03_PFIFO_CACHES, 0x0);
 301         NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
 302         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);
 303         NV_WRITE(NV04_PGRAPH_FIFO,0x0);
 304
 305         nouveau_wait_for_idle(dev);
 306
 307         // save PGRAPH context
 308         index=0;
 309         for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
 310                 for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
 311                 {
 312                         dev_priv->fifos[channel_old].pgraph_ctx[index] = NV_READ(nv04_graph_ctx_regs[i].reg+j*4);
 313                         index++;
 314                 }
 315
 316         NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
 317         NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
 318
 319         // restore PGRAPH context
 320         index=0;
 321         for (i = 0; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
 322                 for (j = 0; j<nv04_graph_ctx_regs[i].number; j++)
 323                 {
 324                         NV_WRITE(nv04_graph_ctx_regs[i].reg+j*4, dev_priv->fifos[channel].pgraph_ctx[index]);
 325                         index++;
 326                 }
 327
 328         NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
 329         NV_WRITE(NV04_PGRAPH_CTX_USER, channel << 24);
 330         NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
 331
 332         NV_WRITE(NV04_PGRAPH_FIFO,0x0);
 333         NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
 334         NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1);
 335         NV_WRITE(NV03_PFIFO_CACHES, 0x1);
 336         NV_WRITE(NV04_PGRAPH_FIFO,0x1);
 337 }
 338
 339 int nv04_graph_context_create(drm_device_t *dev, int channel) {
 340         drm_nouveau_private_t *dev_priv = dev->dev_private;
 341         DRM_DEBUG("nv04_graph_context_create %d\n", channel);
 342
 343         memset(dev_priv->fifos[channel].pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].pgraph_ctx));
 344
 345         //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
 346         dev_priv->fifos[channel].pgraph_ctx[0] = 0x0001ffff;
 347         /* is it really needed ??? */
 348         //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
 349         //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
 350
 351         return 0;
 352 }
 353
 354
 355 int nv04_graph_init(drm_device_t *dev) {
 356         drm_nouveau_private_t *dev_priv = dev->dev_private;
 357         int i,sum=0;
 358
 359         NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
 360                         ~NV_PMC_ENABLE_PGRAPH);
 361         NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
 362                          NV_PMC_ENABLE_PGRAPH);
 363
 364         // check the context is big enough
 365         for ( i = 0 ; i<sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
 366                 sum+=nv04_graph_ctx_regs[i].number;
 367         if ( sum*4>sizeof(dev_priv->fifos[0].pgraph_ctx) )
 368                 DRM_ERROR("pgraph_ctx too small\n");
 369
 370         NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);
 371         NV_WRITE(NV03_PGRAPH_INTR   , 0xFFFFFFFF);
 372
 373         NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF);
 374         NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1230C000);
 375         NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111101);
 376         NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11D5F071);
 377         NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x0004FF31);
 378         NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x4004FF31 |
 379                                     (0x00D00000) |
 380                                     (1<<29) |
 381                                     (1<<31));
 382
 383         NV_WRITE(NV04_PGRAPH_STATE        , 0xFFFFFFFF);
 384         NV_WRITE(NV04_PGRAPH_CTX_CONTROL  , 0x10010100);
 385         NV_WRITE(NV04_PGRAPH_FIFO         , 0x00000001);
 386
 387         /* These don't belong here, they're part of a per-channel context */
 388         NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
 389         NV_WRITE(NV04_PGRAPH_BETA_AND     , 0xFFFFFFFF);
 390
 391         return 0;
 392 }
 393
 394 void nv04_graph_takedown(drm_device_t *dev)
 395 {
 396 }
 397