2 * Copyright 2007 Stephane Marchesin
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drm.h"
28 #include "nouveau_drv.h"
30 static uint32_t nv04_graph_ctx_regs [] = {
31 NV04_PGRAPH_CTX_SWITCH1,
32 NV04_PGRAPH_CTX_SWITCH2,
33 NV04_PGRAPH_CTX_SWITCH3,
34 NV04_PGRAPH_CTX_SWITCH4,
35 NV04_PGRAPH_CTX_CACHE1,
36 NV04_PGRAPH_CTX_CACHE2,
37 NV04_PGRAPH_CTX_CACHE3,
38 NV04_PGRAPH_CTX_CACHE4,
68 NV04_PGRAPH_DMA_START_0,
69 NV04_PGRAPH_DMA_START_1,
70 NV04_PGRAPH_DMA_LENGTH,
72 NV04_PGRAPH_DMA_PITCH,
98 NV04_PGRAPH_BSWIZZLE2,
99 NV04_PGRAPH_BSWIZZLE5,
102 NV04_PGRAPH_PATT_COLOR0,
103 NV04_PGRAPH_PATT_COLOR1,
104 NV04_PGRAPH_PATT_COLORRAM+0x00,
105 NV04_PGRAPH_PATT_COLORRAM+0x01,
106 NV04_PGRAPH_PATT_COLORRAM+0x02,
107 NV04_PGRAPH_PATT_COLORRAM+0x03,
108 NV04_PGRAPH_PATT_COLORRAM+0x04,
109 NV04_PGRAPH_PATT_COLORRAM+0x05,
110 NV04_PGRAPH_PATT_COLORRAM+0x06,
111 NV04_PGRAPH_PATT_COLORRAM+0x07,
112 NV04_PGRAPH_PATT_COLORRAM+0x08,
113 NV04_PGRAPH_PATT_COLORRAM+0x09,
114 NV04_PGRAPH_PATT_COLORRAM+0x0A,
115 NV04_PGRAPH_PATT_COLORRAM+0x0B,
116 NV04_PGRAPH_PATT_COLORRAM+0x0C,
117 NV04_PGRAPH_PATT_COLORRAM+0x0D,
118 NV04_PGRAPH_PATT_COLORRAM+0x0E,
119 NV04_PGRAPH_PATT_COLORRAM+0x0F,
120 NV04_PGRAPH_PATT_COLORRAM+0x10,
121 NV04_PGRAPH_PATT_COLORRAM+0x11,
122 NV04_PGRAPH_PATT_COLORRAM+0x12,
123 NV04_PGRAPH_PATT_COLORRAM+0x13,
124 NV04_PGRAPH_PATT_COLORRAM+0x14,
125 NV04_PGRAPH_PATT_COLORRAM+0x15,
126 NV04_PGRAPH_PATT_COLORRAM+0x16,
127 NV04_PGRAPH_PATT_COLORRAM+0x17,
128 NV04_PGRAPH_PATT_COLORRAM+0x18,
129 NV04_PGRAPH_PATT_COLORRAM+0x19,
130 NV04_PGRAPH_PATT_COLORRAM+0x1A,
131 NV04_PGRAPH_PATT_COLORRAM+0x1B,
132 NV04_PGRAPH_PATT_COLORRAM+0x1C,
133 NV04_PGRAPH_PATT_COLORRAM+0x1D,
134 NV04_PGRAPH_PATT_COLORRAM+0x1E,
135 NV04_PGRAPH_PATT_COLORRAM+0x1F,
136 NV04_PGRAPH_PATT_COLORRAM+0x20,
137 NV04_PGRAPH_PATT_COLORRAM+0x21,
138 NV04_PGRAPH_PATT_COLORRAM+0x22,
139 NV04_PGRAPH_PATT_COLORRAM+0x23,
140 NV04_PGRAPH_PATT_COLORRAM+0x24,
141 NV04_PGRAPH_PATT_COLORRAM+0x25,
142 NV04_PGRAPH_PATT_COLORRAM+0x26,
143 NV04_PGRAPH_PATT_COLORRAM+0x27,
144 NV04_PGRAPH_PATT_COLORRAM+0x28,
145 NV04_PGRAPH_PATT_COLORRAM+0x29,
146 NV04_PGRAPH_PATT_COLORRAM+0x2A,
147 NV04_PGRAPH_PATT_COLORRAM+0x2B,
148 NV04_PGRAPH_PATT_COLORRAM+0x2C,
149 NV04_PGRAPH_PATT_COLORRAM+0x2D,
150 NV04_PGRAPH_PATT_COLORRAM+0x2E,
151 NV04_PGRAPH_PATT_COLORRAM+0x2F,
152 NV04_PGRAPH_PATT_COLORRAM+0x30,
153 NV04_PGRAPH_PATT_COLORRAM+0x31,
154 NV04_PGRAPH_PATT_COLORRAM+0x32,
155 NV04_PGRAPH_PATT_COLORRAM+0x33,
156 NV04_PGRAPH_PATT_COLORRAM+0x34,
157 NV04_PGRAPH_PATT_COLORRAM+0x35,
158 NV04_PGRAPH_PATT_COLORRAM+0x36,
159 NV04_PGRAPH_PATT_COLORRAM+0x37,
160 NV04_PGRAPH_PATT_COLORRAM+0x38,
161 NV04_PGRAPH_PATT_COLORRAM+0x39,
162 NV04_PGRAPH_PATT_COLORRAM+0x3A,
163 NV04_PGRAPH_PATT_COLORRAM+0x3B,
164 NV04_PGRAPH_PATT_COLORRAM+0x3C,
165 NV04_PGRAPH_PATT_COLORRAM+0x3D,
166 NV04_PGRAPH_PATT_COLORRAM+0x3E,
167 NV04_PGRAPH_PATT_COLORRAM+0x3F,
170 NV04_PGRAPH_PATTERN_SHAPE,
174 NV04_PGRAPH_BETA_AND,
175 NV04_PGRAPH_BETA_PREMULT,
176 NV04_PGRAPH_CONTROL0,
177 NV04_PGRAPH_CONTROL1,
178 NV04_PGRAPH_CONTROL2,
180 NV04_PGRAPH_STORED_FMT,
181 NV04_PGRAPH_SOURCE_COLOR,
333 NV04_PGRAPH_PASSTHRU_0,
334 NV04_PGRAPH_PASSTHRU_1,
335 NV04_PGRAPH_PASSTHRU_2,
336 NV04_PGRAPH_DVD_COLORFMT,
337 NV04_PGRAPH_SCALED_FORMAT,
338 NV04_PGRAPH_MISC24_0,
339 NV04_PGRAPH_MISC24_1,
340 NV04_PGRAPH_MISC24_2,
350 int nv04[sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0])];
353 void nouveau_nv04_context_switch(struct drm_device *dev)
355 struct drm_nouveau_private *dev_priv = dev->dev_private;
356 struct nouveau_engine *engine = &dev_priv->Engine;
357 struct nouveau_channel *next, *last;
361 DRM_DEBUG("Invalid drm_device\n");
364 dev_priv = dev->dev_private;
366 DRM_DEBUG("Invalid drm_nouveau_private\n");
369 if (!dev_priv->fifos) {
370 DRM_DEBUG("Invalid drm_nouveau_private->fifos\n");
374 chid = engine->fifo.channel_id(dev);
375 next = dev_priv->fifos[chid];
378 DRM_DEBUG("Invalid next channel\n");
382 chid = (NV_READ(NV04_PGRAPH_CTX_USER) >> 24) & (engine->fifo.channels - 1);
383 last = dev_priv->fifos[chid];
386 DRM_DEBUG("WARNING: Invalid last channel, switch to %x\n",
389 DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",
393 /* NV_WRITE(NV03_PFIFO_CACHES, 0x0);
394 NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
395 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x0);*/
396 NV_WRITE(NV04_PGRAPH_FIFO,0x0);
399 nv04_graph_save_context(last);
401 nouveau_wait_for_idle(dev);
403 NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10000000);
404 NV_WRITE(NV04_PGRAPH_CTX_USER, (NV_READ(NV04_PGRAPH_CTX_USER) & 0xffffff) | (0x0f << 24));
406 nouveau_wait_for_idle(dev);
408 nv04_graph_load_context(next);
410 NV_WRITE(NV04_PGRAPH_CTX_CONTROL, 0x10010100);
411 NV_WRITE(NV04_PGRAPH_CTX_USER, next->id << 24);
412 NV_WRITE(NV04_PGRAPH_FFINTFC_ST2, NV_READ(NV04_PGRAPH_FFINTFC_ST2)&0x000FFFFF);
414 /* NV_WRITE(NV04_PGRAPH_FIFO,0x0);
415 NV_WRITE(NV04_PFIFO_CACHE0_PULL0, 0x0);
416 NV_WRITE(NV04_PFIFO_CACHE1_PULL0, 0x1);
417 NV_WRITE(NV03_PFIFO_CACHES, 0x1);*/
418 NV_WRITE(NV04_PGRAPH_FIFO,0x1);
421 int nv04_graph_create_context(struct nouveau_channel *chan) {
422 struct graph_state* pgraph_ctx;
423 DRM_DEBUG("nv04_graph_context_create %d\n", chan->id);
425 chan->pgraph_ctx = pgraph_ctx = drm_calloc(1, sizeof(*pgraph_ctx),
428 if (pgraph_ctx == NULL)
431 //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
432 pgraph_ctx->nv04[0] = 0x0001ffff;
433 /* is it really needed ??? */
434 //dev_priv->fifos[channel].pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
435 //dev_priv->fifos[channel].pgraph_ctx[2] = NV_READ(0x004006b0);
440 void nv04_graph_destroy_context(struct nouveau_channel *chan)
442 struct graph_state* pgraph_ctx = chan->pgraph_ctx;
444 drm_free(pgraph_ctx, sizeof(*pgraph_ctx), DRM_MEM_DRIVER);
445 chan->pgraph_ctx = NULL;
448 int nv04_graph_load_context(struct nouveau_channel *chan)
450 struct drm_device *dev = chan->dev;
451 struct drm_nouveau_private *dev_priv = dev->dev_private;
452 struct graph_state* pgraph_ctx = chan->pgraph_ctx;
455 for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
456 NV_WRITE(nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
461 int nv04_graph_save_context(struct nouveau_channel *chan)
463 struct drm_device *dev = chan->dev;
464 struct drm_nouveau_private *dev_priv = dev->dev_private;
465 struct graph_state* pgraph_ctx = chan->pgraph_ctx;
468 for (i = 0; i < sizeof(nv04_graph_ctx_regs)/sizeof(nv04_graph_ctx_regs[0]); i++)
469 pgraph_ctx->nv04[i] = NV_READ(nv04_graph_ctx_regs[i]);
474 int nv04_graph_init(struct drm_device *dev) {
475 struct drm_nouveau_private *dev_priv = dev->dev_private;
477 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
478 ~NV_PMC_ENABLE_PGRAPH);
479 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
480 NV_PMC_ENABLE_PGRAPH);
482 /* Enable PGRAPH interrupts */
483 NV_WRITE(NV03_PGRAPH_INTR, 0xFFFFFFFF);
484 NV_WRITE(NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
486 NV_WRITE(NV04_PGRAPH_VALID1, 0);
487 NV_WRITE(NV04_PGRAPH_VALID2, 0);
488 /*NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x000001FF);
489 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
490 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x1231c000);
491 /*1231C000 blob, 001 haiku*/
492 //*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
493 NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x72111100);
494 /*0x72111100 blob , 01 haiku*/
495 /*NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
496 NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x11d5f071);
499 /*NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
500 NV_WRITE(NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
501 /*haiku and blob 10d4*/
503 NV_WRITE(NV04_PGRAPH_STATE , 0xFFFFFFFF);
504 NV_WRITE(NV04_PGRAPH_CTX_CONTROL , 0x10010100);
505 NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
507 /* These don't belong here, they're part of a per-channel context */
508 NV_WRITE(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
509 NV_WRITE(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
514 void nv04_graph_takedown(struct drm_device *dev)