shared-core/nv04_timer.c

   1 #include "drmP.h"
   2 #include "drm.h"
   3 #include "nouveau_drv.h"
   4 #include "nouveau_drm.h"
   5
   6 int
   7 nv04_timer_init(struct drm_device *dev)
   8 {
   9         struct drm_nouveau_private *dev_priv = dev->dev_private;
  10
  11         NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
  12         NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
  13
  14         NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
  15         NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
  16
  17         return 0;
  18 }
  19
  20 uint64_t
  21 nv04_timer_read(struct drm_device *dev)
  22 {
  23         struct drm_nouveau_private *dev_priv = dev->dev_private;
  24         uint32_t low;
  25         /* From kmmio dumps on nv28 this looks like how the blob does this.
  26          * It reads the high dword twice, before and after.
  27          * The only explanation seems to be that the 64-bit timer counter
  28          * advances between high and low dword reads and may corrupt the
  29          * result. Not confirmed.
  30          */
  31         uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1);
  32         uint32_t high1;
  33         do {
  34                 high1 = high2;
  35                 low = NV_READ(NV04_PTIMER_TIME_0);
  36                 high2 = NV_READ(NV04_PTIMER_TIME_1);
  37         } while(high1 != high2);
  38         return (((uint64_t)high2) << 32) | (uint64_t)low;
  39 }
  40
  41 void
  42 nv04_timer_takedown(struct drm_device *dev)
  43 {
  44 }