3 #include "nouveau_drv.h"
4 #include "nouveau_drm.h"
7 nv04_timer_init(struct drm_device *dev)
9 struct drm_nouveau_private *dev_priv = dev->dev_private;
11 NV_WRITE(NV04_PTIMER_INTR_EN_0, 0x00000000);
12 NV_WRITE(NV04_PTIMER_INTR_0, 0xFFFFFFFF);
14 NV_WRITE(NV04_PTIMER_NUMERATOR, 0x00000008);
15 NV_WRITE(NV04_PTIMER_DENOMINATOR, 0x00000003);
21 nv04_timer_read(struct drm_device *dev)
23 struct drm_nouveau_private *dev_priv = dev->dev_private;
25 /* From kmmio dumps on nv28 this looks like how the blob does this.
26 * It reads the high dword twice, before and after.
27 * The only explanation seems to be that the 64-bit timer counter
28 * advances between high and low dword reads and may corrupt the
29 * result. Not confirmed.
31 uint32_t high2 = NV_READ(NV04_PTIMER_TIME_1);
35 low = NV_READ(NV04_PTIMER_TIME_0);
36 high2 = NV_READ(NV04_PTIMER_TIME_1);
37 } while(high1 != high2);
38 return (((uint64_t)high2) << 32) | (uint64_t)low;
42 nv04_timer_takedown(struct drm_device *dev)