shared-core/nv10_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31
  32 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
  33                                          NV10_RAMFC_##offset/4, (val))
  34 #define RAMFC_RD(offset)     INSTANCE_RD(chan->ramfc->gpuobj, \
  35                                          NV10_RAMFC_##offset/4)
  36 #define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE))
  37 #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
  38
  39 int
  40 nv10_fifo_channel_id(struct drm_device *dev)
  41 {
  42         struct drm_nouveau_private *dev_priv = dev->dev_private;
  43
  44         return (NV_READ(NV03_PFIFO_CACHE1_PUSH1) &
  45                         NV10_PFIFO_CACHE1_PUSH1_CHID_MASK);
  46 }
  47
  48 int
  49 nv10_fifo_create_context(struct nouveau_channel *chan)
  50 {
  51         struct drm_device *dev = chan->dev;
  52         struct drm_nouveau_private *dev_priv = dev->dev_private;
  53         int ret;
  54
  55         if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
  56                                                 NV10_RAMFC__SIZE,
  57                                                 NVOBJ_FLAG_ZERO_ALLOC |
  58                                                 NVOBJ_FLAG_ZERO_FREE,
  59                                                 NULL, &chan->ramfc)))
  60                 return ret;
  61
  62         /* Fill entries that are seen filled in dumps of nvidia driver just
  63          * after channel's is put into DMA mode
  64          */
  65         RAMFC_WR(DMA_PUT       , chan->pushbuf_base);
  66         RAMFC_WR(DMA_GET       , chan->pushbuf_base);
  67         RAMFC_WR(DMA_INSTANCE  , chan->pushbuf->instance >> 4);
  68         RAMFC_WR(DMA_FETCH     , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
  69                                  NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  70                                  NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
  71 #ifdef __BIG_ENDIAN
  72                                  NV_PFIFO_CACHE1_BIG_ENDIAN |
  73 #endif
  74                                  0);
  75
  76         /* enable the fifo dma operation */
  77         NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
  78         return 0;
  79 }
  80
  81 void
  82 nv10_fifo_destroy_context(struct nouveau_channel *chan)
  83 {
  84         struct drm_device *dev = chan->dev;
  85         struct drm_nouveau_private *dev_priv = dev->dev_private;
  86
  87         NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
  88
  89         nouveau_gpuobj_ref_del(dev, &chan->ramfc);
  90 }
  91
  92 int
  93 nv10_fifo_load_context(struct nouveau_channel *chan)
  94 {
  95         struct drm_device *dev = chan->dev;
  96         struct drm_nouveau_private *dev_priv = dev->dev_private;
  97         uint32_t tmp;
  98
  99         NV_WRITE(NV03_PFIFO_CACHE1_PUSH1,
 100                  NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
 101
 102         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
 103         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
 104         NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT          , RAMFC_RD(REF_CNT));
 105
 106         tmp = RAMFC_RD(DMA_INSTANCE);
 107         NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE     , tmp & 0xFFFF);
 108         NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT       , tmp >> 16);
 109
 110         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE        , RAMFC_RD(DMA_STATE));
 111         NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH        , RAMFC_RD(DMA_FETCH));
 112         NV_WRITE(NV04_PFIFO_CACHE1_ENGINE           , RAMFC_RD(ENGINE));
 113         NV_WRITE(NV04_PFIFO_CACHE1_PULL1            , RAMFC_RD(PULL1_ENGINE));
 114
 115         if (dev_priv->chipset >= 0x17) {
 116                 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
 117                          RAMFC_RD(ACQUIRE_VALUE));
 118                 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
 119                          RAMFC_RD(ACQUIRE_TIMESTAMP));
 120                 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
 121                          RAMFC_RD(ACQUIRE_TIMEOUT));
 122                 NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE,
 123                          RAMFC_RD(SEMAPHORE));
 124                 NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
 125                          RAMFC_RD(DMA_SUBROUTINE));
 126         }
 127
 128         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 129         tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
 130         NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 131
 132         return 0;
 133 }
 134
 135 int
 136 nv10_fifo_save_context(struct nouveau_channel *chan)
 137 {
 138         struct drm_device *dev = chan->dev;
 139         struct drm_nouveau_private *dev_priv = dev->dev_private;
 140         uint32_t tmp;
 141
 142         RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
 143         RAMFC_WR(DMA_GET          , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 144         RAMFC_WR(REF_CNT          , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
 145
 146         tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
 147         tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
 148         RAMFC_WR(DMA_INSTANCE     , tmp);
 149
 150         RAMFC_WR(DMA_STATE        , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 151         RAMFC_WR(DMA_FETCH        , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
 152         RAMFC_WR(ENGINE           , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 153         RAMFC_WR(PULL1_ENGINE     , NV_READ(NV04_PFIFO_CACHE1_PULL1));
 154
 155         if (dev_priv->chipset >= 0x17) {
 156                 RAMFC_WR(ACQUIRE_VALUE,
 157                          NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 158                 RAMFC_WR(ACQUIRE_TIMESTAMP,
 159                          NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
 160                 RAMFC_WR(ACQUIRE_TIMEOUT,
 161                          NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 162                 RAMFC_WR(SEMAPHORE,
 163                          NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 164                 RAMFC_WR(DMA_SUBROUTINE,
 165                          NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 166         }
 167
 168         return 0;
 169 }