shared-core/nv10_fifo.c

   1 /*
   2  * Copyright (C) 2007 Ben Skeggs.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "drmP.h"
  28 #include "drm.h"
  29 #include "nouveau_drv.h"
  30
  31
  32 #define RAMFC_WR(offset,val) INSTANCE_WR(chan->ramfc->gpuobj, \
  33                                          NV10_RAMFC_##offset/4, (val))
  34 #define RAMFC_RD(offset)     INSTANCE_RD(chan->ramfc->gpuobj, \
  35                                          NV10_RAMFC_##offset/4)
  36 #define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE))
  37 #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
  38
  39 int
  40 nv10_fifo_create_context(struct nouveau_channel *chan)
  41 {
  42         struct drm_device *dev = chan->dev;
  43         struct drm_nouveau_private *dev_priv = dev->dev_private;
  44         int ret;
  45
  46         if ((ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id),
  47                                                 NV10_RAMFC__SIZE,
  48                                                 NVOBJ_FLAG_ZERO_ALLOC |
  49                                                 NVOBJ_FLAG_ZERO_FREE,
  50                                                 NULL, &chan->ramfc)))
  51                 return ret;
  52
  53         /* Fill entries that are seen filled in dumps of nvidia driver just
  54          * after channel's is put into DMA mode
  55          */
  56         RAMFC_WR(DMA_PUT       , chan->pushbuf_base);
  57         RAMFC_WR(DMA_GET       , chan->pushbuf_base);
  58         RAMFC_WR(DMA_INSTANCE  , chan->pushbuf->instance >> 4);
  59         RAMFC_WR(DMA_FETCH     , NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
  60                                  NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
  61                                  NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
  62 #ifdef __BIG_ENDIAN
  63                                  NV_PFIFO_CACHE1_BIG_ENDIAN |
  64 #endif
  65                                  0);
  66
  67         /* enable the fifo dma operation */
  68         NV_WRITE(NV04_PFIFO_MODE,NV_READ(NV04_PFIFO_MODE)|(1<<chan->id));
  69         return 0;
  70 }
  71
  72 void
  73 nv10_fifo_destroy_context(struct nouveau_channel *chan)
  74 {
  75         struct drm_device *dev = chan->dev;
  76         struct drm_nouveau_private *dev_priv = dev->dev_private;
  77
  78         NV_WRITE(NV04_PFIFO_MODE, NV_READ(NV04_PFIFO_MODE)&~(1<<chan->id));
  79
  80         nouveau_gpuobj_ref_del(dev, &chan->ramfc);
  81 }
  82
  83 int
  84 nv10_fifo_load_context(struct nouveau_channel *chan)
  85 {
  86         struct drm_device *dev = chan->dev;
  87         struct drm_nouveau_private *dev_priv = dev->dev_private;
  88         uint32_t tmp;
  89
  90         NV_WRITE(NV03_PFIFO_CACHE1_PUSH1            , 0x00000100 | chan->id);
  91
  92         NV_WRITE(NV04_PFIFO_CACHE1_DMA_GET          , RAMFC_RD(DMA_GET));
  93         NV_WRITE(NV04_PFIFO_CACHE1_DMA_PUT          , RAMFC_RD(DMA_PUT));
  94         NV_WRITE(NV10_PFIFO_CACHE1_REF_CNT          , RAMFC_RD(REF_CNT));
  95
  96         tmp = RAMFC_RD(DMA_INSTANCE);
  97         NV_WRITE(NV04_PFIFO_CACHE1_DMA_INSTANCE     , tmp & 0xFFFF);
  98         NV_WRITE(NV04_PFIFO_CACHE1_DMA_DCOUNT       , tmp >> 16);
  99
 100         NV_WRITE(NV04_PFIFO_CACHE1_DMA_STATE        , RAMFC_RD(DMA_STATE));
 101         NV_WRITE(NV04_PFIFO_CACHE1_DMA_FETCH        , RAMFC_RD(DMA_FETCH));
 102         NV_WRITE(NV04_PFIFO_CACHE1_ENGINE           , RAMFC_RD(ENGINE));
 103         NV_WRITE(NV04_PFIFO_CACHE1_PULL1            , RAMFC_RD(PULL1_ENGINE));
 104
 105         if (dev_priv->chipset >= 0x17) {
 106                 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_VALUE,
 107                          RAMFC_RD(ACQUIRE_VALUE));
 108                 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP,
 109                          RAMFC_RD(ACQUIRE_TIMESTAMP));
 110                 NV_WRITE(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT,
 111                          RAMFC_RD(ACQUIRE_TIMEOUT));
 112                 NV_WRITE(NV10_PFIFO_CACHE1_SEMAPHORE,
 113                          RAMFC_RD(SEMAPHORE));
 114                 NV_WRITE(NV10_PFIFO_CACHE1_DMA_SUBROUTINE,
 115                          RAMFC_RD(DMA_SUBROUTINE));
 116         }
 117
 118         /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
 119         tmp = NV_READ(NV04_PFIFO_CACHE1_DMA_CTL) & ~(1<<31);
 120         NV_WRITE(NV04_PFIFO_CACHE1_DMA_CTL, tmp);
 121
 122         return 0;
 123 }
 124
 125 int
 126 nv10_fifo_save_context(struct nouveau_channel *chan)
 127 {
 128         struct drm_device *dev = chan->dev;
 129         struct drm_nouveau_private *dev_priv = dev->dev_private;
 130         uint32_t tmp;
 131
 132         RAMFC_WR(DMA_PUT          , NV_READ(NV04_PFIFO_CACHE1_DMA_PUT));
 133         RAMFC_WR(DMA_GET          , NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 134         RAMFC_WR(REF_CNT          , NV_READ(NV10_PFIFO_CACHE1_REF_CNT));
 135
 136         tmp  = NV_READ(NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
 137         tmp |= (NV_READ(NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
 138         RAMFC_WR(DMA_INSTANCE     , tmp);
 139
 140         RAMFC_WR(DMA_STATE        , NV_READ(NV04_PFIFO_CACHE1_DMA_STATE));
 141         RAMFC_WR(DMA_FETCH        , NV_READ(NV04_PFIFO_CACHE1_DMA_FETCH));
 142         RAMFC_WR(ENGINE           , NV_READ(NV04_PFIFO_CACHE1_ENGINE));
 143         RAMFC_WR(PULL1_ENGINE     , NV_READ(NV04_PFIFO_CACHE1_PULL1));
 144
 145         if (dev_priv->chipset >= 0x17) {
 146                 RAMFC_WR(ACQUIRE_VALUE,
 147                          NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
 148                 RAMFC_WR(ACQUIRE_TIMESTAMP,
 149                          NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP));
 150                 RAMFC_WR(ACQUIRE_TIMEOUT,
 151                          NV_READ(NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
 152                 RAMFC_WR(SEMAPHORE,
 153                          NV_READ(NV10_PFIFO_CACHE1_SEMAPHORE));
 154                 RAMFC_WR(DMA_SUBROUTINE,
 155                          NV_READ(NV04_PFIFO_CACHE1_DMA_GET));
 156         }
 157
 158         return 0;
 159 }
 160