2 * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
27 #include "nouveau_drm.h"
28 #include "nouveau_drv.h"
31 static void nv10_praph_pipe(drm_device_t *dev) {
32 drm_nouveau_private_t *dev_priv = dev->dev_private;
35 nouveau_wait_for_idle(dev);
36 /* XXX check haiku comments */
37 NV_WRITE(NV10_PGRAPH_XFMODE0, 0x10000000);
38 NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
39 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0);
40 for (i = 0; i < 4; i++)
41 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
42 for (i = 0; i < 4; i++)
43 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
45 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
47 for (i = 0; i < 3; i++)
48 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
50 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006a80);
51 for (i = 0; i < 3; i++)
52 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
54 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
55 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000008);
57 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000200);
58 for (i = 0; i < 48; i++)
59 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
61 nouveau_wait_for_idle(dev);
63 NV_WRITE(NV10_PGRAPH_XFMODE0, 0x00000000);
64 NV_WRITE(NV10_PGRAPH_XFMODE1, 0x00000000);
65 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006400);
66 for (i = 0; i < 211; i++)
67 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
69 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
70 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
71 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
72 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
73 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x40000000);
74 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
75 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
76 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
77 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
78 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000);
79 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f000000);
80 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
81 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
82 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
83 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
84 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
85 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
86 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
87 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
88 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
89 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
90 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
91 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
92 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
93 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
95 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006800);
96 for (i = 0; i < 162; i++)
97 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
98 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x3f800000);
99 for (i = 0; i < 25; i++)
100 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
102 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00006c00);
103 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
104 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
105 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
106 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
107 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0xbf800000);
108 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
109 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
110 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
111 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
112 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
113 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
114 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
115 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007000);
116 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
117 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
118 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
119 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
120 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
121 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
122 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
123 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
124 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
125 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
126 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
127 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
128 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
129 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
130 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
131 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
132 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
133 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
134 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
135 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
136 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
137 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
138 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
139 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
140 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
141 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
142 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
143 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
144 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
145 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
146 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
147 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
148 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
149 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
150 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
151 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
152 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
153 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
154 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
155 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
156 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x7149f2ca);
157 for (i = 0; i < 35; i++)
158 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
161 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007400);
162 for (i = 0; i < 48; i++)
163 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
165 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00007800);
166 for (i = 0; i < 48; i++)
167 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
169 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00004400);
170 for (i = 0; i < 32; i++)
171 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
173 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000000);
174 for (i = 0; i < 16; i++)
175 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
177 NV_WRITE(NV10_PGRAPH_PIPE_ADDRESS, 0x00000040);
178 for (i = 0; i < 4; i++)
179 NV_WRITE(NV10_PGRAPH_PIPE_DATA, 0x00000000);
181 nouveau_wait_for_idle(dev);
184 /* TODO replace address with name
186 static int nv10_graph_ctx_regs [] = {
187 NV03_PGRAPH_XY_LOGIC_MISC0,
189 NV10_PGRAPH_CTX_SWITCH1,
190 NV10_PGRAPH_CTX_SWITCH2,
191 NV10_PGRAPH_CTX_SWITCH3,
192 NV10_PGRAPH_CTX_SWITCH4,
193 NV10_PGRAPH_CTX_SWITCH5,
194 NV10_PGRAPH_CTX_CACHE1, /* 8 values from 0x400160 to 0x40017c */
195 NV10_PGRAPH_CTX_CACHE2, /* 8 values from 0x400180 to 0x40019c */
196 NV10_PGRAPH_CTX_CACHE3, /* 8 values from 0x4001a0 to 0x4001bc */
197 NV10_PGRAPH_CTX_CACHE4, /* 8 values from 0x4001c0 to 0x4001dc */
198 NV10_PGRAPH_CTX_CACHE5, /* 8 values from 0x4001e0 to 0x4001fc */
234 NV10_PGRAPH_CTX_USER,
235 NV04_PGRAPH_DMA_START_0,
236 NV04_PGRAPH_DMA_START_1,
237 NV04_PGRAPH_DMA_LENGTH,
238 NV04_PGRAPH_DMA_MISC,
239 NV10_PGRAPH_DMA_PITCH,
240 NV04_PGRAPH_BOFFSET0,
243 NV04_PGRAPH_BOFFSET1,
246 NV04_PGRAPH_BOFFSET2,
249 NV04_PGRAPH_BOFFSET3,
252 NV04_PGRAPH_BOFFSET4,
255 NV04_PGRAPH_BOFFSET5,
265 NV04_PGRAPH_BSWIZZLE2,
266 NV04_PGRAPH_BSWIZZLE5,
269 NV04_PGRAPH_PATT_COLOR0,
270 NV04_PGRAPH_PATT_COLOR1,
271 NV04_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
335 NV04_PGRAPH_PATTERN, /* 2 values from 0x400808 to 0x40080c */
337 NV04_PGRAPH_PATTERN_SHAPE,
338 NV03_PGRAPH_MONO_COLOR0,
341 NV04_PGRAPH_BETA_AND,
342 NV04_PGRAPH_BETA_PREMULT,
358 NV10_PGRAPH_WINDOWCLIP_HORIZONTAL, /* 8 values from 0x400f00 to 0x400f1c */
359 NV10_PGRAPH_WINDOWCLIP_VERTICAL, /* 8 values from 0x400f20 to 0x400f3c */
376 NV10_PGRAPH_GLOBALSTATE0,
377 NV10_PGRAPH_GLOBALSTATE1,
378 NV04_PGRAPH_STORED_FMT,
379 NV04_PGRAPH_SOURCE_COLOR,
380 NV03_PGRAPH_ABS_X_RAM, /* 32 values from 0x400400 to 0x40047c */
381 NV03_PGRAPH_ABS_Y_RAM, /* 32 values from 0x400480 to 0x4004fc */
444 NV03_PGRAPH_ABS_UCLIP_XMIN,
445 NV03_PGRAPH_ABS_UCLIP_XMAX,
446 NV03_PGRAPH_ABS_UCLIP_YMIN,
447 NV03_PGRAPH_ABS_UCLIP_YMAX,
452 NV03_PGRAPH_ABS_UCLIPA_XMIN,
453 NV03_PGRAPH_ABS_UCLIPA_XMAX,
454 NV03_PGRAPH_ABS_UCLIPA_YMIN,
455 NV03_PGRAPH_ABS_UCLIPA_YMAX,
456 NV03_PGRAPH_ABS_ICLIP_XMAX,
457 NV03_PGRAPH_ABS_ICLIP_YMAX,
458 NV03_PGRAPH_XY_LOGIC_MISC1,
459 NV03_PGRAPH_XY_LOGIC_MISC2,
460 NV03_PGRAPH_XY_LOGIC_MISC3,
493 NV04_PGRAPH_PASSTHRU_0,
494 NV04_PGRAPH_PASSTHRU_1,
495 NV04_PGRAPH_PASSTHRU_2,
496 NV10_PGRAPH_DIMX_TEXTURE,
497 NV10_PGRAPH_WDIMX_TEXTURE,
498 NV10_PGRAPH_DVD_COLORFMT,
499 NV10_PGRAPH_SCALED_FORMAT,
500 NV04_PGRAPH_MISC24_0,
501 NV04_PGRAPH_MISC24_1,
502 NV04_PGRAPH_MISC24_2,
509 static int nv17_graph_ctx_regs [] = {
530 static int nv10_graph_ctx_regs_find_offset(drm_device_t *dev, int reg)
532 drm_nouveau_private_t *dev_priv = dev->dev_private;
534 for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++) {
535 if (nv10_graph_ctx_regs[i] == reg)
538 if (dev_priv->chipset>=0x17) {
539 for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++) {
540 if (nv17_graph_ctx_regs[j] == reg)
547 static void restore_ctx_regs(drm_device_t *dev, int channel)
549 drm_nouveau_private_t *dev_priv = dev->dev_private;
550 struct nouveau_fifo *fifo = dev_priv->fifos[channel];
552 for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
553 NV_WRITE(nv10_graph_ctx_regs[i], fifo->pgraph_ctx[i]);
554 if (dev_priv->chipset>=0x17) {
555 for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
556 NV_WRITE(nv17_graph_ctx_regs[j], fifo->pgraph_ctx[i]);
558 nouveau_wait_for_idle(dev);
561 void nouveau_nv10_context_switch(drm_device_t *dev)
563 drm_nouveau_private_t *dev_priv = dev->dev_private;
564 int channel, channel_old, i, j;
566 channel=NV_READ(NV03_PFIFO_CACHE1_PUSH1)&(nouveau_fifo_number(dev)-1);
567 channel_old = (NV_READ(NV10_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
569 DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
571 NV_WRITE(NV04_PGRAPH_FIFO,0x0);
573 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
574 NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
575 NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
578 // save PGRAPH context
579 for (i = 0; i < sizeof(nv10_graph_ctx_regs)/sizeof(nv10_graph_ctx_regs[0]); i++)
580 dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
581 if (dev_priv->chipset>=0x17) {
582 for (j = 0; j < sizeof(nv17_graph_ctx_regs)/sizeof(nv17_graph_ctx_regs[0]); i++,j++)
583 dev_priv->fifos[channel_old]->pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[j]);
586 nouveau_wait_for_idle(dev);
588 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10000000);
589 NV_WRITE(NV10_PGRAPH_CTX_USER, (NV_READ(NV10_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
591 nouveau_wait_for_idle(dev);
592 // restore PGRAPH context
594 restore_ctx_regs(dev, channel);
597 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
598 NV_WRITE(NV10_PGRAPH_CTX_USER, channel << 24);
599 NV_WRITE(NV10_PGRAPH_FFINTFC_ST2, NV_READ(NV10_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
602 NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
603 NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
604 NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
606 NV_WRITE(NV04_PGRAPH_FIFO,0x1);
609 #define NV_WRITE_CTX(reg, val) do { \
610 int offset = nv10_graph_ctx_regs_find_offset(dev, reg); \
612 fifo->pgraph_ctx[offset] = val; \
614 int nv10_graph_create_context(drm_device_t *dev, int channel) {
615 drm_nouveau_private_t *dev_priv = dev->dev_private;
616 struct nouveau_fifo *fifo = dev_priv->fifos[channel];
617 uint32_t tmp, vramsz;
619 DRM_DEBUG("nv10_graph_context_create %d\n", channel);
621 memset(fifo->pgraph_ctx, 0, sizeof(fifo->pgraph_ctx));
623 /* per channel init from ddx */
624 tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
625 /*XXX the original ddx code, does this in 2 steps :
626 * tmp = NV_READ(NV10_PGRAPH_SURFACE) & 0x0007ff00;
627 * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
628 * tmp = NV_READ(NV10_PGRAPH_SURFACE) | 0x00020100;
629 * NV_WRITE(NV10_PGRAPH_SURFACE, tmp);
632 NV_WRITE_CTX(NV10_PGRAPH_SURFACE, tmp);
634 vramsz = drm_get_resource_len(dev, 0) - 1;
635 NV_WRITE_CTX(NV04_PGRAPH_BOFFSET0, 0);
636 NV_WRITE_CTX(NV04_PGRAPH_BOFFSET1, 0);
637 NV_WRITE_CTX(NV04_PGRAPH_BLIMIT0 , vramsz);
638 NV_WRITE_CTX(NV04_PGRAPH_BLIMIT1 , vramsz);
640 NV_WRITE_CTX(NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
641 NV_WRITE_CTX(NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
643 NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMIN, 0);
644 NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMIN, 0);
645 NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_XMAX, 0x7fff);
646 NV_WRITE_CTX(NV03_PGRAPH_ABS_UCLIP_YMAX, 0x7fff);
648 NV_WRITE_CTX(NV03_PGRAPH_XY_LOGIC_MISC0, 0x0001ffff);
649 /* is it really needed ??? */
650 if (dev_priv->chipset>=0x17) {
651 NV_WRITE_CTX(NV10_PGRAPH_DEBUG_4, NV_READ(NV10_PGRAPH_DEBUG_4));
652 NV_WRITE_CTX(0x004006b0, NV_READ(0x004006b0));
655 /* for the first channel init the regs */
656 if (dev_priv->fifo_alloc_count == 0)
657 restore_ctx_regs(dev, channel);
660 //XXX should be saved/restored for each fifo
661 //we supposed here we have X fifo and only one 3D fifo.
662 nv10_praph_pipe(dev);
666 void nv10_graph_destroy_context(drm_device_t *dev, int channel)
670 int nv10_graph_load_context(drm_device_t *dev, int channel)
672 DRM_ERROR("stub!\n");
676 int nv10_graph_save_context(drm_device_t *dev, int channel)
678 DRM_ERROR("stub!\n");
682 int nv10_graph_init(drm_device_t *dev) {
683 drm_nouveau_private_t *dev_priv = dev->dev_private;
686 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) &
687 ~NV_PMC_ENABLE_PGRAPH);
688 NV_WRITE(NV03_PMC_ENABLE, NV_READ(NV03_PMC_ENABLE) |
689 NV_PMC_ENABLE_PGRAPH);
691 NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);
692 NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);
694 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
695 NV_WRITE(NV04_PGRAPH_DEBUG_0, 0x00000000);
696 NV_WRITE(NV04_PGRAPH_DEBUG_1, 0x00118700);
697 NV_WRITE(NV04_PGRAPH_DEBUG_2, 0x24E00810);
698 NV_WRITE(NV04_PGRAPH_DEBUG_3, 0x55DE0030 |
702 /* copy tile info from PFB */
703 for (i=0; i<NV10_PFB_TILE__SIZE; i++) {
704 NV_WRITE(NV10_PGRAPH_TILE(i), NV_READ(NV10_PFB_TILE(i)));
705 NV_WRITE(NV10_PGRAPH_TLIMIT(i), NV_READ(NV10_PFB_TLIMIT(i)));
706 NV_WRITE(NV10_PGRAPH_TSIZE(i), NV_READ(NV10_PFB_TSIZE(i)));
707 NV_WRITE(NV10_PGRAPH_TSTATUS(i), NV_READ(NV10_PFB_TSTATUS(i)));
710 NV_WRITE(NV10_PGRAPH_CTX_CONTROL, 0x10010100);
711 NV_WRITE(NV10_PGRAPH_STATE , 0xFFFFFFFF);
712 NV_WRITE(NV04_PGRAPH_FIFO , 0x00000001);
717 void nv10_graph_takedown(drm_device_t *dev)