shared-core/nv10_graph.c

   1 /*
   2  * Copyright 2007 Matthieu CASTET <castet.matthieu@free.fr>
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  */
  24
  25 #include "drmP.h"
  26 #include "drm.h"
  27 #include "nouveau_drm.h"
  28 #include "nouveau_drv.h"
  29
  30
  31 static void nv10_praph_pipe(drm_device_t *dev) {
  32         drm_nouveau_private_t *dev_priv = dev->dev_private;
  33         int i;
  34
  35         nouveau_wait_for_idle(dev);
  36         /* XXX check haiku comments */
  37         NV_WRITE(NV_PGRAPH_XFMODE0, 0x10000000);
  38         NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000);
  39         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x000064c0);
  40         for (i = 0; i < 4; i++)
  41                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  42         for (i = 0; i < 4; i++)
  43                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  44
  45         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006ab0);
  46
  47         for (i = 0; i < 3; i++)
  48                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  49
  50         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006a80);
  51         for (i = 0; i < 3; i++)
  52                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  53
  54         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040);
  55         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000008);
  56
  57         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000200);
  58         for (i = 0; i < 48; i++)
  59                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  60
  61         nouveau_wait_for_idle(dev);
  62
  63         NV_WRITE(NV_PGRAPH_XFMODE0, 0x00000000);
  64         NV_WRITE(NV_PGRAPH_XFMODE1, 0x00000000);
  65         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006400);
  66         for (i = 0; i < 211; i++)
  67                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  68
  69         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  70         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
  71         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
  72         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
  73         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x40000000);
  74         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  75         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  76         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  77         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  78         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000);
  79         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f000000);
  80         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  81         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  82         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  83         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  84         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  85         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  86         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  87         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  88         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  89         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  90         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  91         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  92         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  93         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  94
  95         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006800);
  96         for (i = 0; i < 162; i++)
  97                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
  98         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x3f800000);
  99         for (i = 0; i < 25; i++)
 100                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 101
 102         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00006c00);
 103         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 104         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 105         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 106         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 107         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0xbf800000);
 108         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 109         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 110         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 111         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 112         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 113         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 114         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 115         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007000);
 116         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 117         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 118         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 119         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 120         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 121         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 122         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 123         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 124         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 125         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 126         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 127         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 128         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 129         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 130         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 131         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 132         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 133         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 134         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 135         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 136         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 137         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 138         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 139         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 140         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 141         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 142         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 143         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 144         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 145         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 146         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 147         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 148         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 149         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 150         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 151         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 152         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 153         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 154         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 155         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 156         NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x7149f2ca);
 157         for (i = 0; i < 35; i++)
 158                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 159
 160
 161         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007400);
 162         for (i = 0; i < 48; i++)
 163                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 164
 165         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00007800);
 166         for (i = 0; i < 48; i++)
 167                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 168
 169         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00004400);
 170         for (i = 0; i < 32; i++)
 171                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 172
 173         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000000);
 174         for (i = 0; i < 16; i++)
 175                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 176
 177         NV_WRITE(NV_PGRAPH_PIPE_ADDRESS, 0x00000040);
 178         for (i = 0; i < 4; i++)
 179                 NV_WRITE(NV_PGRAPH_PIPE_DATA, 0x00000000);
 180
 181         nouveau_wait_for_idle(dev);
 182 }
 183
 184 /* TODO replace address with name
 185    use loops */
 186 static int nv10_graph_ctx_regs [] = {
 187 NV_PGRAPH_XY_LOGIC_MISC0,
 188 NV_PGRAPH_DEBUG_4,
 189 0x004006b0,
 190
 191 NV_PGRAPH_CTX_SWITCH1,
 192 NV_PGRAPH_CTX_SWITCH2,
 193 NV_PGRAPH_CTX_SWITCH3,
 194 NV_PGRAPH_CTX_SWITCH4,
 195 NV_PGRAPH_CTX_SWITCH5,
 196 NV_PGRAPH_CTX_CACHE1,   /* 8 values from 0x400160 to 0x40017c */
 197 NV_PGRAPH_CTX_CACHE2,   /* 8 values from 0x400180 to 0x40019c */
 198 NV_PGRAPH_CTX_CACHE3,   /* 8 values from 0x4001a0 to 0x4001bc */
 199 NV_PGRAPH_CTX_CACHE4,   /* 8 values from 0x4001c0 to 0x4001dc */
 200 NV_PGRAPH_CTX_CACHE5,   /* 8 values from 0x4001e0 to 0x4001fc */
 201 0x00400164,
 202 0x00400184,
 203 0x004001a4,
 204 0x004001c4,
 205 0x004001e4,
 206 0x00400168,
 207 0x00400188,
 208 0x004001a8,
 209 0x004001c8,
 210 0x004001e8,
 211 0x0040016c,
 212 0x0040018c,
 213 0x004001ac,
 214 0x004001cc,
 215 0x004001ec,
 216 0x00400170,
 217 0x00400190,
 218 0x004001b0,
 219 0x004001d0,
 220 0x004001f0,
 221 0x00400174,
 222 0x00400194,
 223 0x004001b4,
 224 0x004001d4,
 225 0x004001f4,
 226 0x00400178,
 227 0x00400198,
 228 0x004001b8,
 229 0x004001d8,
 230 0x004001f8,
 231 0x0040017c,
 232 0x0040019c,
 233 0x004001bc,
 234 0x004001dc,
 235 0x004001fc,
 236 NV_PGRAPH_CTX_USER,
 237 NV_PGRAPH_DMA_START_0,
 238 NV_PGRAPH_DMA_START_1,
 239 NV_PGRAPH_DMA_LENGTH,
 240 NV_PGRAPH_DMA_MISC,
 241 NV_PGRAPH_DMA_PITCH,
 242 NV_PGRAPH_BOFFSET0,
 243 NV_PGRAPH_BBASE0,
 244 NV_PGRAPH_BLIMIT0,
 245 NV_PGRAPH_BOFFSET1,
 246 NV_PGRAPH_BBASE1,
 247 NV_PGRAPH_BLIMIT1,
 248 NV_PGRAPH_BOFFSET2,
 249 NV_PGRAPH_BBASE2,
 250 NV_PGRAPH_BLIMIT2,
 251 NV_PGRAPH_BOFFSET3,
 252 NV_PGRAPH_BBASE3,
 253 NV_PGRAPH_BLIMIT3,
 254 NV_PGRAPH_BOFFSET4,
 255 NV_PGRAPH_BBASE4,
 256 NV_PGRAPH_BLIMIT4,
 257 NV_PGRAPH_BOFFSET5,
 258 NV_PGRAPH_BBASE5,
 259 NV_PGRAPH_BLIMIT5,
 260 NV_PGRAPH_BPITCH0,
 261 NV_PGRAPH_BPITCH1,
 262 NV_PGRAPH_BPITCH2,
 263 NV_PGRAPH_BPITCH3,
 264 NV_PGRAPH_BPITCH4,
 265 NV_PGRAPH_SURFACE,
 266 NV_PGRAPH_STATE,
 267 NV_PGRAPH_BSWIZZLE2,
 268 NV_PGRAPH_BSWIZZLE5,
 269 NV_PGRAPH_BPIXEL,
 270 NV_PGRAPH_NOTIFY,
 271 NV_PGRAPH_PATT_COLOR0,
 272 NV_PGRAPH_PATT_COLOR1,
 273 NV_PGRAPH_PATT_COLORRAM, /* 64 values from 0x400900 to 0x4009fc */
 274 0x00400904,
 275 0x00400908,
 276 0x0040090c,
 277 0x00400910,
 278 0x00400914,
 279 0x00400918,
 280 0x0040091c,
 281 0x00400920,
 282 0x00400924,
 283 0x00400928,
 284 0x0040092c,
 285 0x00400930,
 286 0x00400934,
 287 0x00400938,
 288 0x0040093c,
 289 0x00400940,
 290 0x00400944,
 291 0x00400948,
 292 0x0040094c,
 293 0x00400950,
 294 0x00400954,
 295 0x00400958,
 296 0x0040095c,
 297 0x00400960,
 298 0x00400964,
 299 0x00400968,
 300 0x0040096c,
 301 0x00400970,
 302 0x00400974,
 303 0x00400978,
 304 0x0040097c,
 305 0x00400980,
 306 0x00400984,
 307 0x00400988,
 308 0x0040098c,
 309 0x00400990,
 310 0x00400994,
 311 0x00400998,
 312 0x0040099c,
 313 0x004009a0,
 314 0x004009a4,
 315 0x004009a8,
 316 0x004009ac,
 317 0x004009b0,
 318 0x004009b4,
 319 0x004009b8,
 320 0x004009bc,
 321 0x004009c0,
 322 0x004009c4,
 323 0x004009c8,
 324 0x004009cc,
 325 0x004009d0,
 326 0x004009d4,
 327 0x004009d8,
 328 0x004009dc,
 329 0x004009e0,
 330 0x004009e4,
 331 0x004009e8,
 332 0x004009ec,
 333 0x004009f0,
 334 0x004009f4,
 335 0x004009f8,
 336 0x004009fc,
 337 NV_PGRAPH_PATTERN,      /* 2 values from 0x400808 to 0x40080c */
 338 0x0040080c,
 339 NV_PGRAPH_PATTERN_SHAPE,
 340 NV_PGRAPH_MONO_COLOR0,
 341 NV_PGRAPH_ROP3,
 342 NV_PGRAPH_CHROMA,
 343 NV_PGRAPH_BETA_AND,
 344 NV_PGRAPH_BETA_PREMULT,
 345 0x00400e70,
 346 0x00400e74,
 347 0x00400e78,
 348 0x00400e7c,
 349 0x00400e80,
 350 0x00400e84,
 351 0x00400e88,
 352 0x00400e8c,
 353 0x00400ea0,
 354 0x00400ea4,
 355 0x00400ea8,
 356 0x00400eac,
 357 0x00400e90,
 358 0x00400e94,
 359 0x00400e98,
 360 0x00400e9c,
 361 NV_PGRAPH_WINDOWCLIP_HORIZONTAL,/* 8 values from 0x400f00 to 0x400f1c */
 362 NV_PGRAPH_WINDOWCLIP_VERTICAL,  /* 8 values from 0x400f20 to 0x400f3c */
 363 0x00400f04,
 364 0x00400f24,
 365 0x00400f08,
 366 0x00400f28,
 367 0x00400f0c,
 368 0x00400f2c,
 369 0x00400f10,
 370 0x00400f30,
 371 0x00400f14,
 372 0x00400f34,
 373 0x00400f18,
 374 0x00400f38,
 375 0x00400f1c,
 376 0x00400f3c,
 377 NV_PGRAPH_XFMODE0,
 378 NV_PGRAPH_XFMODE1,
 379 NV_PGRAPH_GLOBALSTATE0,
 380 NV_PGRAPH_GLOBALSTATE1,
 381 NV_PGRAPH_STORED_FMT,
 382 NV_PGRAPH_SOURCE_COLOR,
 383 NV_PGRAPH_ABS_X_RAM,    /* 32 values from 0x400400 to 0x40047c */
 384 NV_PGRAPH_ABS_Y_RAM,    /* 32 values from 0x400480 to 0x4004fc */
 385 0x00400404,
 386 0x00400484,
 387 0x00400408,
 388 0x00400488,
 389 0x0040040c,
 390 0x0040048c,
 391 0x00400410,
 392 0x00400490,
 393 0x00400414,
 394 0x00400494,
 395 0x00400418,
 396 0x00400498,
 397 0x0040041c,
 398 0x0040049c,
 399 0x00400420,
 400 0x004004a0,
 401 0x00400424,
 402 0x004004a4,
 403 0x00400428,
 404 0x004004a8,
 405 0x0040042c,
 406 0x004004ac,
 407 0x00400430,
 408 0x004004b0,
 409 0x00400434,
 410 0x004004b4,
 411 0x00400438,
 412 0x004004b8,
 413 0x0040043c,
 414 0x004004bc,
 415 0x00400440,
 416 0x004004c0,
 417 0x00400444,
 418 0x004004c4,
 419 0x00400448,
 420 0x004004c8,
 421 0x0040044c,
 422 0x004004cc,
 423 0x00400450,
 424 0x004004d0,
 425 0x00400454,
 426 0x004004d4,
 427 0x00400458,
 428 0x004004d8,
 429 0x0040045c,
 430 0x004004dc,
 431 0x00400460,
 432 0x004004e0,
 433 0x00400464,
 434 0x004004e4,
 435 0x00400468,
 436 0x004004e8,
 437 0x0040046c,
 438 0x004004ec,
 439 0x00400470,
 440 0x004004f0,
 441 0x00400474,
 442 0x004004f4,
 443 0x00400478,
 444 0x004004f8,
 445 0x0040047c,
 446 0x004004fc,
 447 NV_PGRAPH_ABS_UCLIP_XMIN,
 448 NV_PGRAPH_ABS_UCLIP_XMAX,
 449 NV_PGRAPH_ABS_UCLIP_YMIN,
 450 NV_PGRAPH_ABS_UCLIP_YMAX,
 451 0x00400550,
 452 0x00400558,
 453 0x00400554,
 454 0x0040055c,
 455 NV_PGRAPH_ABS_UCLIPA_XMIN,
 456 NV_PGRAPH_ABS_UCLIPA_XMAX,
 457 NV_PGRAPH_ABS_UCLIPA_YMIN,
 458 NV_PGRAPH_ABS_UCLIPA_YMAX,
 459 NV_PGRAPH_ABS_ICLIP_XMAX,
 460 NV_PGRAPH_ABS_ICLIP_YMAX,
 461 NV_PGRAPH_XY_LOGIC_MISC1,
 462 NV_PGRAPH_XY_LOGIC_MISC2,
 463 NV_PGRAPH_XY_LOGIC_MISC3,
 464 NV_PGRAPH_CLIPX_0,
 465 NV_PGRAPH_CLIPX_1,
 466 NV_PGRAPH_CLIPY_0,
 467 NV_PGRAPH_CLIPY_1,
 468 0x00400e40,
 469 0x00400e44,
 470 0x00400e48,
 471 0x00400e4c,
 472 0x00400e50,
 473 0x00400e54,
 474 0x00400e58,
 475 0x00400e5c,
 476 0x00400e60,
 477 0x00400e64,
 478 0x00400e68,
 479 0x00400e6c,
 480 0x00400e00,
 481 0x00400e04,
 482 0x00400e08,
 483 0x00400e0c,
 484 0x00400e10,
 485 0x00400e14,
 486 0x00400e18,
 487 0x00400e1c,
 488 0x00400e20,
 489 0x00400e24,
 490 0x00400e28,
 491 0x00400e2c,
 492 0x00400e30,
 493 0x00400e34,
 494 0x00400e38,
 495 0x00400e3c,
 496 NV_PGRAPH_PASSTHRU_0,
 497 NV_PGRAPH_PASSTHRU_1,
 498 NV_PGRAPH_PASSTHRU_2,
 499 NV_PGRAPH_DIMX_TEXTURE,
 500 NV_PGRAPH_WDIMX_TEXTURE,
 501 NV_PGRAPH_DVD_COLORFMT,
 502 NV_PGRAPH_SCALED_FORMAT,
 503 NV_PGRAPH_MISC24_0,
 504 NV_PGRAPH_MISC24_1,
 505 NV_PGRAPH_MISC24_2,
 506 NV_PGRAPH_X_MISC,
 507 NV_PGRAPH_Y_MISC,
 508 NV_PGRAPH_VALID1,
 509 NV_PGRAPH_VALID2,
 510 0
 511 };
 512
 513 static int nv17_graph_ctx_regs [] = {
 514 0x00400eb0,
 515 0x00400eb4,
 516 0x00400eb8,
 517 0x00400ebc,
 518 0x00400ec0,
 519 0x00400ec4,
 520 0x00400ec8,
 521 0x00400ecc,
 522 0x00400ed0,
 523 0x00400ed4,
 524 0x00400ed8,
 525 0x00400edc,
 526 0x00400ee0,
 527 0x00400a00,
 528 0x00400a04,
 529 0
 530 };
 531
 532 void nouveau_nv10_context_switch(drm_device_t *dev)
 533 {
 534         drm_nouveau_private_t *dev_priv = dev->dev_private;
 535         int channel, channel_old, i, gpu_type;
 536
 537         channel=NV_READ(NV_PFIFO_CACH1_PSH1)&(nouveau_fifo_number(dev)-1);
 538         channel_old = (NV_READ(NV_PGRAPH_CTX_USER) >> 24) & (nouveau_fifo_number(dev)-1);
 539
 540         DRM_INFO("NV: PGRAPH context switch interrupt channel %x -> %x\n",channel_old, channel);
 541
 542         NV_WRITE(NV_PGRAPH_FIFO,0x0);
 543 #if 0
 544         NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000000);
 545         NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000000);
 546         NV_WRITE(NV_PFIFO_CACHES, 0x00000000);
 547 #endif
 548
 549         // save PGRAPH context
 550         for (i = 0; nv10_graph_ctx_regs[i]; i++)
 551                 dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv10_graph_ctx_regs[i]);
 552         gpu_type = (NV_READ(NV_PMC_BOOT_0) & 0x0ff00000);
 553         if ((gpu_type==0x01700000)
 554                 || (gpu_type==0x01800000)
 555                 || (gpu_type==0x01f00000))
 556         {
 557                 for (; nv17_graph_ctx_regs[i]; i++)
 558                         dev_priv->fifos[channel_old].nv10_pgraph_ctx[i] = NV_READ(nv17_graph_ctx_regs[i]);
 559         }
 560
 561         nouveau_wait_for_idle(dev);
 562
 563         NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10000000);
 564         NV_WRITE(NV_PGRAPH_CTX_USER, (NV_READ(NV_PGRAPH_CTX_USER) & 0xffffff) | (0x1f << 24));
 565
 566         nouveau_wait_for_idle(dev);
 567         // restore PGRAPH context
 568         //XXX not working yet
 569 #if 0
 570         for (i = 0; nv10_graph_ctx_regs[i]; i++)
 571                 NV_WRITE(nv10_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]);
 572         if ((gpu_type==0x01700000)
 573                 || (gpu_type==0x01800000)
 574                 || (gpu_type==0x01f00000))
 575         {
 576                 for (; nv17_graph_ctx_regs[i]; i++)
 577                         NV_WRITE(nv17_graph_ctx_regs[i], dev_priv->fifos[channel].nv10_pgraph_ctx[i]);
 578         }
 579         nouveau_wait_for_idle(dev);
 580 #endif
 581
 582         NV_WRITE(NV_PGRAPH_CTX_CONTROL, 0x10010100);
 583         NV_WRITE(NV_PGRAPH_CTX_USER, channel << 24);
 584         NV_WRITE(NV_PGRAPH_FFINTFC_ST2, NV_READ(NV_PGRAPH_FFINTFC_ST2)&0xCFFFFFFF);
 585
 586 #if 0
 587         NV_WRITE(NV_PFIFO_CACH1_PUL0, 0x00000001);
 588         NV_WRITE(NV_PFIFO_CACH1_PUL1, 0x00000001);
 589         NV_WRITE(NV_PFIFO_CACHES, 0x00000001);
 590 #endif
 591         NV_WRITE(NV_PGRAPH_FIFO,0x1);
 592 }
 593
 594 int nv10_graph_context_create(drm_device_t *dev, int channel) {
 595         drm_nouveau_private_t *dev_priv = dev->dev_private;
 596         DRM_DEBUG("nv10_graph_context_create %d\n", channel);
 597
 598         memset(dev_priv->fifos[channel].nv10_pgraph_ctx, 0, sizeof(dev_priv->fifos[channel].nv10_pgraph_ctx));
 599
 600         //dev_priv->fifos[channel].pgraph_ctx_user = channel << 24;
 601         dev_priv->fifos[channel].nv10_pgraph_ctx[0] = 0x0001ffff;
 602         /* is it really needed ??? */
 603         dev_priv->fifos[channel].nv10_pgraph_ctx[1] = NV_READ(NV_PGRAPH_DEBUG_4);
 604         dev_priv->fifos[channel].nv10_pgraph_ctx[2] = NV_READ(0x004006b0);
 605         return 0;
 606 }
 607
 608
 609 int nv10_graph_init(drm_device_t *dev) {
 610         //XXX should be call at each fifo init
 611         nv10_praph_pipe(dev);
 612         return 0;
 613 }