shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36 #include "r300_reg.h"
  37
  38 #include "radeon_microcode.h"
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 static int radeon_do_cleanup_cp(struct drm_device * dev);
  42 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  74             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  75             return RS690_READ_MCIND(dev_priv, addr);
  76         else
  77             return RS480_READ_MCIND(dev_priv, addr);
  78 }
  79
  80 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  81 {
  82
  83         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  84                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  85         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  86                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  87                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  88         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  89                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  90         else
  91                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  92 }
  93
  94 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  95 {
  96         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  97                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  98         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  99                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 100                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 101         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 102                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 103         else
 104                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 105 }
 106
 107 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 108 {
 109         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 110                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 111         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 112                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 113                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 114         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 115                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 116         else
 117                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 118 }
 119
 120 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 121 {
 122         u32 agp_base_hi = upper_32_bits(agp_base);
 123         u32 agp_base_lo = agp_base & 0xffffffff;
 124
 125         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 126                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 127                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 128         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 129                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 130                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 131                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 132         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 133                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 134                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 135         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 136                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 137                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 138                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 139         } else {
 140                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 141                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 142                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 143         }
 144 }
 145
 146 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 147 {
 148         drm_radeon_private_t *dev_priv = dev->dev_private;
 149
 150         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 151         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 152 }
 153
 154 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 155 {
 156         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 157         return RADEON_READ(RADEON_PCIE_DATA);
 158 }
 159
 160 #if RADEON_FIFO_DEBUG
 161 static void radeon_status(drm_radeon_private_t * dev_priv)
 162 {
 163         printk("%s:\n", __FUNCTION__);
 164         printk("RBBM_STATUS = 0x%08x\n",
 165                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 166         printk("CP_RB_RTPR = 0x%08x\n",
 167                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 168         printk("CP_RB_WTPR = 0x%08x\n",
 169                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 170         printk("AIC_CNTL = 0x%08x\n",
 171                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 172         printk("AIC_STAT = 0x%08x\n",
 173                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 174         printk("AIC_PT_BASE = 0x%08x\n",
 175                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 176         printk("TLB_ADDR = 0x%08x\n",
 177                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 178         printk("TLB_DATA = 0x%08x\n",
 179                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 180 }
 181 #endif
 182
 183 /* ================================================================
 184  * Engine, FIFO control
 185  */
 186
 187 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 188 {
 189         u32 tmp;
 190         int i;
 191
 192         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 193
 194         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 195                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 196                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 197                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 198
 199                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 200                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 201                               & RADEON_RB3D_DC_BUSY)) {
 202                                 return 0;
 203                         }
 204                         DRM_UDELAY(1);
 205                 }
 206         } else {
 207                 /* don't flush or purge cache here or lockup */
 208                 return 0;
 209         }
 210
 211 #if RADEON_FIFO_DEBUG
 212         DRM_ERROR("failed!\n");
 213         radeon_status(dev_priv);
 214 #endif
 215         return -EBUSY;
 216 }
 217
 218 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 219 {
 220         int i;
 221
 222         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 223
 224         for (i = 0; i < dev_priv->usec_timeout; i++) {
 225                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 226                              & RADEON_RBBM_FIFOCNT_MASK);
 227                 if (slots >= entries)
 228                         return 0;
 229                 DRM_UDELAY(1);
 230         }
 231         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
 232                  RADEON_READ(RADEON_RBBM_STATUS),
 233                  RADEON_READ(R300_VAP_CNTL_STATUS));
 234
 235 #if RADEON_FIFO_DEBUG
 236         DRM_ERROR("failed!\n");
 237         radeon_status(dev_priv);
 238 #endif
 239         return -EBUSY;
 240 }
 241
 242 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 243 {
 244         int i, ret;
 245
 246         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 247
 248         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 249         if (ret)
 250                 return ret;
 251
 252         for (i = 0; i < dev_priv->usec_timeout; i++) {
 253                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 254                       & RADEON_RBBM_ACTIVE)) {
 255                         radeon_do_pixcache_flush(dev_priv);
 256                         return 0;
 257                 }
 258                 DRM_UDELAY(1);
 259         }
 260         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 261                  RADEON_READ(RADEON_RBBM_STATUS),
 262                  RADEON_READ(R300_VAP_CNTL_STATUS));
 263
 264 #if RADEON_FIFO_DEBUG
 265         DRM_ERROR("failed!\n");
 266         radeon_status(dev_priv);
 267 #endif
 268         return -EBUSY;
 269 }
 270
 271 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 272 {
 273         uint32_t gb_tile_config, gb_pipe_sel = 0;
 274
 275         /* RS4xx/RS6xx/R4xx/R5xx */
 276         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 277                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 278                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 279         } else {
 280                 /* R3xx */
 281                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 282                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 283                         dev_priv->num_gb_pipes = 2;
 284                 } else {
 285                         /* R3Vxx */
 286                         dev_priv->num_gb_pipes = 1;
 287                 }
 288         }
 289         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 290
 291         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 292
 293         switch(dev_priv->num_gb_pipes) {
 294         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 295         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 296         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 297         default:
 298         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 299         }
 300
 301         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 302                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 303                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 304         }
 305         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 306         radeon_do_wait_for_idle(dev_priv);
 307         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 308         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 309                                                R300_DC_AUTOFLUSH_ENABLE |
 310                                                R300_DC_DC_DISABLE_IGNORE_PE));
 311
 312
 313 }
 314
 315 /* ================================================================
 316  * CP control, initialization
 317  */
 318
 319 /* Load the microcode for the CP */
 320 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 321 {
 322         int i;
 323         DRM_DEBUG("\n");
 324
 325         radeon_do_wait_for_idle(dev_priv);
 326
 327         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 328
 329         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 330             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 331             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 332             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 333             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 334                 DRM_INFO("Loading R100 Microcode\n");
 335                 for (i = 0; i < 256; i++) {
 336                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 337                                      R100_cp_microcode[i][1]);
 338                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 339                                      R100_cp_microcode[i][0]);
 340                 }
 341         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 342                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 343                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 344                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 345                 DRM_INFO("Loading R200 Microcode\n");
 346                 for (i = 0; i < 256; i++) {
 347                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 348                                      R200_cp_microcode[i][1]);
 349                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 350                                      R200_cp_microcode[i][0]);
 351                 }
 352         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 353                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 354                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 355                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 356                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 357                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 358                 DRM_INFO("Loading R300 Microcode\n");
 359                 for (i = 0; i < 256; i++) {
 360                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 361                                      R300_cp_microcode[i][1]);
 362                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 363                                      R300_cp_microcode[i][0]);
 364                 }
 365         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 366                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 367                 DRM_INFO("Loading R400 Microcode\n");
 368                 for (i = 0; i < 256; i++) {
 369                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 370                                      R420_cp_microcode[i][1]);
 371                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 372                                      R420_cp_microcode[i][0]);
 373                 }
 374         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 375                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 376                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 377                 for (i = 0; i < 256; i++) {
 378                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 379                                      RS690_cp_microcode[i][1]);
 380                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 381                                      RS690_cp_microcode[i][0]);
 382                 }
 383         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 384                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 385                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 386                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 387                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 388                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 389                 DRM_INFO("Loading R500 Microcode\n");
 390                 for (i = 0; i < 256; i++) {
 391                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 392                                      R520_cp_microcode[i][1]);
 393                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 394                                      R520_cp_microcode[i][0]);
 395                 }
 396         }
 397 }
 398
 399 /* Flush any pending commands to the CP.  This should only be used just
 400  * prior to a wait for idle, as it informs the engine that the command
 401  * stream is ending.
 402  */
 403 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 404 {
 405         DRM_DEBUG("\n");
 406 #if 0
 407         u32 tmp;
 408
 409         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 410         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 411 #endif
 412 }
 413
 414 /* Wait for the CP to go idle.
 415  */
 416 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 417 {
 418         RING_LOCALS;
 419         DRM_DEBUG("\n");
 420
 421         BEGIN_RING(6);
 422
 423         RADEON_PURGE_CACHE();
 424         RADEON_PURGE_ZCACHE();
 425         RADEON_WAIT_UNTIL_IDLE();
 426
 427         ADVANCE_RING();
 428         COMMIT_RING();
 429
 430         return radeon_do_wait_for_idle(dev_priv);
 431 }
 432
 433 /* Start the Command Processor.
 434  */
 435 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 436 {
 437         RING_LOCALS;
 438         DRM_DEBUG("\n");
 439
 440         radeon_do_wait_for_idle(dev_priv);
 441
 442         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 443
 444         dev_priv->cp_running = 1;
 445
 446         BEGIN_RING(8);
 447         /* isync can only be written through cp on r5xx write it here */
 448         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 449         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 450                  RADEON_ISYNC_ANY3D_IDLE2D |
 451                  RADEON_ISYNC_WAIT_IDLEGUI |
 452                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 453         RADEON_PURGE_CACHE();
 454         RADEON_PURGE_ZCACHE();
 455         RADEON_WAIT_UNTIL_IDLE();
 456         ADVANCE_RING();
 457         COMMIT_RING();
 458
 459         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 460 }
 461
 462 /* Reset the Command Processor.  This will not flush any pending
 463  * commands, so you must wait for the CP command stream to complete
 464  * before calling this routine.
 465  */
 466 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 467 {
 468         u32 cur_read_ptr;
 469         DRM_DEBUG("\n");
 470
 471         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 472         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 473         SET_RING_HEAD(dev_priv, cur_read_ptr);
 474         dev_priv->ring.tail = cur_read_ptr;
 475 }
 476
 477 /* Stop the Command Processor.  This will not flush any pending
 478  * commands, so you must flush the command stream and wait for the CP
 479  * to go idle before calling this routine.
 480  */
 481 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 482 {
 483         DRM_DEBUG("\n");
 484
 485         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 486
 487         dev_priv->cp_running = 0;
 488 }
 489
 490 /* Reset the engine.  This will stop the CP if it is running.
 491  */
 492 static int radeon_do_engine_reset(struct drm_device * dev)
 493 {
 494         drm_radeon_private_t *dev_priv = dev->dev_private;
 495         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 496         DRM_DEBUG("\n");
 497
 498         radeon_do_pixcache_flush(dev_priv);
 499
 500         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 501                 /* may need something similar for newer chips */
 502                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 503                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 504
 505                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 506                                                     RADEON_FORCEON_MCLKA |
 507                                                     RADEON_FORCEON_MCLKB |
 508                                                     RADEON_FORCEON_YCLKA |
 509                                                     RADEON_FORCEON_YCLKB |
 510                                                     RADEON_FORCEON_MC |
 511                                                     RADEON_FORCEON_AIC));
 512         }
 513
 514         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 515
 516         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 517                                               RADEON_SOFT_RESET_CP |
 518                                               RADEON_SOFT_RESET_HI |
 519                                               RADEON_SOFT_RESET_SE |
 520                                               RADEON_SOFT_RESET_RE |
 521                                               RADEON_SOFT_RESET_PP |
 522                                               RADEON_SOFT_RESET_E2 |
 523                                               RADEON_SOFT_RESET_RB));
 524         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 525         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 526                                               ~(RADEON_SOFT_RESET_CP |
 527                                                 RADEON_SOFT_RESET_HI |
 528                                                 RADEON_SOFT_RESET_SE |
 529                                                 RADEON_SOFT_RESET_RE |
 530                                                 RADEON_SOFT_RESET_PP |
 531                                                 RADEON_SOFT_RESET_E2 |
 532                                                 RADEON_SOFT_RESET_RB)));
 533         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 534
 535         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 536                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 537                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 538                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 539         }
 540
 541         /* setup the raster pipes */
 542         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 543             radeon_init_pipes(dev_priv);
 544
 545         /* Reset the CP ring */
 546         radeon_do_cp_reset(dev_priv);
 547
 548         /* The CP is no longer running after an engine reset */
 549         dev_priv->cp_running = 0;
 550
 551         /* Reset any pending vertex, indirect buffers */
 552         radeon_freelist_reset(dev);
 553
 554         return 0;
 555 }
 556
 557 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 558                                        drm_radeon_private_t * dev_priv)
 559 {
 560         u32 ring_start, cur_read_ptr;
 561         u32 tmp;
 562
 563         /* Initialize the memory controller. With new memory map, the fb location
 564          * is not changed, it should have been properly initialized already. Part
 565          * of the problem is that the code below is bogus, assuming the GART is
 566          * always appended to the fb which is not necessarily the case
 567          */
 568         if (!dev_priv->new_memmap)
 569                 radeon_write_fb_location(dev_priv,
 570                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 571                              | (dev_priv->fb_location >> 16));
 572
 573 #if __OS_HAS_AGP
 574         if (dev_priv->flags & RADEON_IS_AGP) {
 575                 radeon_write_agp_base(dev_priv, dev->agp->base);
 576
 577                 radeon_write_agp_location(dev_priv,
 578                              (((dev_priv->gart_vm_start - 1 +
 579                                 dev_priv->gart_size) & 0xffff0000) |
 580                               (dev_priv->gart_vm_start >> 16)));
 581
 582                 ring_start = (dev_priv->cp_ring->offset
 583                               - dev->agp->base
 584                               + dev_priv->gart_vm_start);
 585         } else
 586 #endif
 587                 ring_start = (dev_priv->cp_ring->offset
 588                               - (unsigned long)dev->sg->virtual
 589                               + dev_priv->gart_vm_start);
 590
 591         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 592
 593         /* Set the write pointer delay */
 594         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 595
 596         /* Initialize the ring buffer's read and write pointers */
 597         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 598         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 599         SET_RING_HEAD(dev_priv, cur_read_ptr);
 600         dev_priv->ring.tail = cur_read_ptr;
 601
 602 #if __OS_HAS_AGP
 603         if (dev_priv->flags & RADEON_IS_AGP) {
 604                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 605                              dev_priv->ring_rptr->offset
 606                              - dev->agp->base + dev_priv->gart_vm_start);
 607         } else
 608 #endif
 609         {
 610                 struct drm_sg_mem *entry = dev->sg;
 611                 unsigned long tmp_ofs, page_ofs;
 612
 613                 tmp_ofs = dev_priv->ring_rptr->offset -
 614                                 (unsigned long)dev->sg->virtual;
 615                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 616
 617                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 618                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 619                           (unsigned long)entry->busaddr[page_ofs],
 620                           entry->handle + tmp_ofs);
 621         }
 622
 623         /* Set ring buffer size */
 624 #ifdef __BIG_ENDIAN
 625         RADEON_WRITE(RADEON_CP_RB_CNTL,
 626                      RADEON_BUF_SWAP_32BIT |
 627                      (dev_priv->ring.fetch_size_l2ow << 18) |
 628                      (dev_priv->ring.rptr_update_l2qw << 8) |
 629                      dev_priv->ring.size_l2qw);
 630 #else
 631         RADEON_WRITE(RADEON_CP_RB_CNTL,
 632                      (dev_priv->ring.fetch_size_l2ow << 18) |
 633                      (dev_priv->ring.rptr_update_l2qw << 8) |
 634                      dev_priv->ring.size_l2qw);
 635 #endif
 636
 637         /* Initialize the scratch register pointer.  This will cause
 638          * the scratch register values to be written out to memory
 639          * whenever they are updated.
 640          *
 641          * We simply put this behind the ring read pointer, this works
 642          * with PCI GART as well as (whatever kind of) AGP GART
 643          */
 644         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 645                      + RADEON_SCRATCH_REG_OFFSET);
 646
 647         dev_priv->scratch = ((__volatile__ u32 *)
 648                              dev_priv->ring_rptr->handle +
 649                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 650
 651         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 652
 653         /* Turn on bus mastering */
 654         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 655         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 656
 657         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 658         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 659
 660         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 661         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 662                      dev_priv->sarea_priv->last_dispatch);
 663
 664         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 665         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 666
 667         radeon_do_wait_for_idle(dev_priv);
 668
 669         /* Sync everything up */
 670         RADEON_WRITE(RADEON_ISYNC_CNTL,
 671                      (RADEON_ISYNC_ANY2D_IDLE3D |
 672                       RADEON_ISYNC_ANY3D_IDLE2D |
 673                       RADEON_ISYNC_WAIT_IDLEGUI |
 674                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 675
 676 }
 677
 678 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 679 {
 680         u32 tmp;
 681
 682         /* Writeback doesn't seem to work everywhere, test it here and possibly
 683          * enable it if it appears to work
 684          */
 685         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 686         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 687
 688         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 689                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 690                     0xdeadbeef)
 691                         break;
 692                 DRM_UDELAY(1);
 693         }
 694
 695         if (tmp < dev_priv->usec_timeout) {
 696                 dev_priv->writeback_works = 1;
 697                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 698         } else {
 699                 dev_priv->writeback_works = 0;
 700                 DRM_INFO("writeback test failed\n");
 701         }
 702         if (radeon_no_wb == 1) {
 703                 dev_priv->writeback_works = 0;
 704                 DRM_INFO("writeback forced off\n");
 705         }
 706
 707         if (!dev_priv->writeback_works) {
 708                 /* Disable writeback to avoid unnecessary bus master transfers */
 709                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
 710                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 711         }
 712 }
 713
 714 /* Enable or disable IGP GART on the chip */
 715 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 716 {
 717         u32 temp;
 718
 719         if (on) {
 720                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 721                          dev_priv->gart_vm_start,
 722                          (long)dev_priv->gart_info.bus_addr,
 723                          dev_priv->gart_size);
 724
 725                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 726
 727                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 728                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 729                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 730                                                              RS690_BLOCK_GFX_D3_EN));
 731                 else
 732                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 733
 734                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 735                                                                RS480_VA_SIZE_32MB));
 736
 737                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 738                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 739                                                         RS480_TLB_ENABLE |
 740                                                         RS480_GTW_LAC_EN |
 741                                                         RS480_1LEVEL_GART));
 742
 743                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 744                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 745                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 746
 747                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 748                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 749                                                       RS480_REQ_TYPE_SNOOP_DIS));
 750
 751                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 752
 753                 dev_priv->gart_size = 32*1024*1024;
 754                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 755                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 756
 757                 radeon_write_agp_location(dev_priv, temp);
 758
 759                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 760                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 761                                                                RS480_VA_SIZE_32MB));
 762
 763                 do {
 764                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 765                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 766                                 break;
 767                         DRM_UDELAY(1);
 768                 } while(1);
 769
 770                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 771                                 RS480_GART_CACHE_INVALIDATE);
 772
 773                 do {
 774                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 775                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 776                                 break;
 777                         DRM_UDELAY(1);
 778                 } while(1);
 779
 780                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 781         } else {
 782                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 783         }
 784 }
 785
 786 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 787 {
 788         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 789         if (on) {
 790
 791                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 792                           dev_priv->gart_vm_start,
 793                           (long)dev_priv->gart_info.bus_addr,
 794                           dev_priv->gart_size);
 795                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 796                                   dev_priv->gart_vm_start);
 797                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 798                                   dev_priv->gart_info.bus_addr);
 799                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 800                                   dev_priv->gart_vm_start);
 801                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 802                                   dev_priv->gart_vm_start +
 803                                   dev_priv->gart_size - 1);
 804
 805                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 806
 807                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 808                                   RADEON_PCIE_TX_GART_EN);
 809         } else {
 810                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 811                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 812         }
 813 }
 814
 815 /* Enable or disable PCI GART on the chip */
 816 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 817 {
 818         u32 tmp;
 819
 820         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 821             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
 822             (dev_priv->flags & RADEON_IS_IGPGART)) {
 823                 radeon_set_igpgart(dev_priv, on);
 824                 return;
 825         }
 826
 827         if (dev_priv->flags & RADEON_IS_PCIE) {
 828                 radeon_set_pciegart(dev_priv, on);
 829                 return;
 830         }
 831
 832         tmp = RADEON_READ(RADEON_AIC_CNTL);
 833
 834         if (on) {
 835                 RADEON_WRITE(RADEON_AIC_CNTL,
 836                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 837
 838                 /* set PCI GART page-table base address
 839                  */
 840                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 841
 842                 /* set address range for PCI address translate
 843                  */
 844                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 845                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 846                              + dev_priv->gart_size - 1);
 847
 848                 /* Turn off AGP aperture -- is this required for PCI GART?
 849                  */
 850                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 851                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 852         } else {
 853                 RADEON_WRITE(RADEON_AIC_CNTL,
 854                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 855         }
 856 }
 857
 858 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 859 {
 860         drm_radeon_private_t *dev_priv = dev->dev_private;
 861
 862         DRM_DEBUG("\n");
 863
 864         /* if we require new memory map but we don't have it fail */
 865         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 866                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 867                 radeon_do_cleanup_cp(dev);
 868                 return -EINVAL;
 869         }
 870
 871         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
 872         {
 873                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 874                 dev_priv->flags &= ~RADEON_IS_AGP;
 875         }
 876         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 877                  && !init->is_pci)
 878         {
 879                 DRM_DEBUG("Restoring AGP flag\n");
 880                 dev_priv->flags |= RADEON_IS_AGP;
 881         }
 882
 883         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 884                 DRM_ERROR("PCI GART memory not allocated!\n");
 885                 radeon_do_cleanup_cp(dev);
 886                 return -EINVAL;
 887         }
 888
 889         dev_priv->usec_timeout = init->usec_timeout;
 890         if (dev_priv->usec_timeout < 1 ||
 891             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 892                 DRM_DEBUG("TIMEOUT problem!\n");
 893                 radeon_do_cleanup_cp(dev);
 894                 return -EINVAL;
 895         }
 896
 897         /* Enable vblank on CRTC1 for older X servers
 898          */
 899         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 900
 901         dev_priv->do_boxes = 0;
 902         dev_priv->cp_mode = init->cp_mode;
 903
 904         /* We don't support anything other than bus-mastering ring mode,
 905          * but the ring can be in either AGP or PCI space for the ring
 906          * read pointer.
 907          */
 908         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 909             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 910                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 911                 radeon_do_cleanup_cp(dev);
 912                 return -EINVAL;
 913         }
 914
 915         switch (init->fb_bpp) {
 916         case 16:
 917                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 918                 break;
 919         case 32:
 920         default:
 921                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 922                 break;
 923         }
 924         dev_priv->front_offset = init->front_offset;
 925         dev_priv->front_pitch = init->front_pitch;
 926         dev_priv->back_offset = init->back_offset;
 927         dev_priv->back_pitch = init->back_pitch;
 928
 929         switch (init->depth_bpp) {
 930         case 16:
 931                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 932                 break;
 933         case 32:
 934         default:
 935                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 936                 break;
 937         }
 938         dev_priv->depth_offset = init->depth_offset;
 939         dev_priv->depth_pitch = init->depth_pitch;
 940
 941         /* Hardware state for depth clears.  Remove this if/when we no
 942          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 943          * all values to prevent unwanted 3D state from slipping through
 944          * and screwing with the clear operation.
 945          */
 946         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 947                                            (dev_priv->color_fmt << 10) |
 948                                            (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
 949
 950         dev_priv->depth_clear.rb3d_zstencilcntl =
 951             (dev_priv->depth_fmt |
 952              RADEON_Z_TEST_ALWAYS |
 953              RADEON_STENCIL_TEST_ALWAYS |
 954              RADEON_STENCIL_S_FAIL_REPLACE |
 955              RADEON_STENCIL_ZPASS_REPLACE |
 956              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 957
 958         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 959                                          RADEON_BFACE_SOLID |
 960                                          RADEON_FFACE_SOLID |
 961                                          RADEON_FLAT_SHADE_VTX_LAST |
 962                                          RADEON_DIFFUSE_SHADE_FLAT |
 963                                          RADEON_ALPHA_SHADE_FLAT |
 964                                          RADEON_SPECULAR_SHADE_FLAT |
 965                                          RADEON_FOG_SHADE_FLAT |
 966                                          RADEON_VTX_PIX_CENTER_OGL |
 967                                          RADEON_ROUND_MODE_TRUNC |
 968                                          RADEON_ROUND_PREC_8TH_PIX);
 969
 970
 971         dev_priv->ring_offset = init->ring_offset;
 972         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 973         dev_priv->buffers_offset = init->buffers_offset;
 974         dev_priv->gart_textures_offset = init->gart_textures_offset;
 975
 976         dev_priv->sarea = drm_getsarea(dev);
 977         if (!dev_priv->sarea) {
 978                 DRM_ERROR("could not find sarea!\n");
 979                 radeon_do_cleanup_cp(dev);
 980                 return -EINVAL;
 981         }
 982
 983         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 984         if (!dev_priv->cp_ring) {
 985                 DRM_ERROR("could not find cp ring region!\n");
 986                 radeon_do_cleanup_cp(dev);
 987                 return -EINVAL;
 988         }
 989         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
 990         if (!dev_priv->ring_rptr) {
 991                 DRM_ERROR("could not find ring read pointer!\n");
 992                 radeon_do_cleanup_cp(dev);
 993                 return -EINVAL;
 994         }
 995         dev->agp_buffer_token = init->buffers_offset;
 996         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
 997         if (!dev->agp_buffer_map) {
 998                 DRM_ERROR("could not find dma buffer region!\n");
 999                 radeon_do_cleanup_cp(dev);
1000                 return -EINVAL;
1001         }
1002
1003         if (init->gart_textures_offset) {
1004                 dev_priv->gart_textures =
1005                     drm_core_findmap(dev, init->gart_textures_offset);
1006                 if (!dev_priv->gart_textures) {
1007                         DRM_ERROR("could not find GART texture region!\n");
1008                         radeon_do_cleanup_cp(dev);
1009                         return -EINVAL;
1010                 }
1011         }
1012
1013         dev_priv->sarea_priv =
1014             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1015                                     init->sarea_priv_offset);
1016
1017 #if __OS_HAS_AGP
1018         if (dev_priv->flags & RADEON_IS_AGP) {
1019                 drm_core_ioremap(dev_priv->cp_ring, dev);
1020                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1021                 drm_core_ioremap(dev->agp_buffer_map, dev);
1022                 if (!dev_priv->cp_ring->handle ||
1023                     !dev_priv->ring_rptr->handle ||
1024                     !dev->agp_buffer_map->handle) {
1025                         DRM_ERROR("could not find ioremap agp regions!\n");
1026                         radeon_do_cleanup_cp(dev);
1027                         return -EINVAL;
1028                 }
1029         } else
1030 #endif
1031         {
1032                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1033                 dev_priv->ring_rptr->handle =
1034                     (void *)dev_priv->ring_rptr->offset;
1035                 dev->agp_buffer_map->handle =
1036                     (void *)dev->agp_buffer_map->offset;
1037
1038                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1039                           dev_priv->cp_ring->handle);
1040                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1041                           dev_priv->ring_rptr->handle);
1042                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1043                           dev->agp_buffer_map->handle);
1044         }
1045
1046         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1047         dev_priv->fb_size =
1048                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1049                 - dev_priv->fb_location;
1050
1051         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1052                                         ((dev_priv->front_offset
1053                                           + dev_priv->fb_location) >> 10));
1054
1055         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1056                                        ((dev_priv->back_offset
1057                                          + dev_priv->fb_location) >> 10));
1058
1059         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1060                                         ((dev_priv->depth_offset
1061                                           + dev_priv->fb_location) >> 10));
1062
1063         dev_priv->gart_size = init->gart_size;
1064
1065         /* New let's set the memory map ... */
1066         if (dev_priv->new_memmap) {
1067                 u32 base = 0;
1068
1069                 DRM_INFO("Setting GART location based on new memory map\n");
1070
1071                 /* If using AGP, try to locate the AGP aperture at the same
1072                  * location in the card and on the bus, though we have to
1073                  * align it down.
1074                  */
1075 #if __OS_HAS_AGP
1076                 if (dev_priv->flags & RADEON_IS_AGP) {
1077                         base = dev->agp->base;
1078                         /* Check if valid */
1079                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1080                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1081                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1082                                          dev->agp->base);
1083                                 base = 0;
1084                         }
1085                 }
1086 #endif
1087                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1088                 if (base == 0) {
1089                         base = dev_priv->fb_location + dev_priv->fb_size;
1090                         if (base < dev_priv->fb_location ||
1091                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1092                                 base = dev_priv->fb_location
1093                                         - dev_priv->gart_size;
1094                 }
1095                 dev_priv->gart_vm_start = base & 0xffc00000u;
1096                 if (dev_priv->gart_vm_start != base)
1097                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1098                                  base, dev_priv->gart_vm_start);
1099         } else {
1100                 DRM_INFO("Setting GART location based on old memory map\n");
1101                 dev_priv->gart_vm_start = dev_priv->fb_location +
1102                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1103         }
1104
1105 #if __OS_HAS_AGP
1106         if (dev_priv->flags & RADEON_IS_AGP)
1107                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1108                                                  - dev->agp->base
1109                                                  + dev_priv->gart_vm_start);
1110         else
1111 #endif
1112                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1113                                         - (unsigned long)dev->sg->virtual
1114                                         + dev_priv->gart_vm_start);
1115
1116         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1117         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1118         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1119                   dev_priv->gart_buffers_offset);
1120
1121         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1122         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1123                               + init->ring_size / sizeof(u32));
1124         dev_priv->ring.size = init->ring_size;
1125         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1126
1127         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1128         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1129
1130         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1131         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1132
1133         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1134
1135         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1136
1137 #if __OS_HAS_AGP
1138         if (dev_priv->flags & RADEON_IS_AGP) {
1139                 /* Turn off PCI GART */
1140                 radeon_set_pcigart(dev_priv, 0);
1141         } else
1142 #endif
1143         {
1144                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1145                 /* if we have an offset set from userspace */
1146                 if (dev_priv->pcigart_offset_set) {
1147                         dev_priv->gart_info.bus_addr =
1148                             dev_priv->pcigart_offset + dev_priv->fb_location;
1149                         dev_priv->gart_info.mapping.offset =
1150                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1151                         dev_priv->gart_info.mapping.size =
1152                             dev_priv->gart_info.table_size;
1153
1154                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1155                         dev_priv->gart_info.addr =
1156                             dev_priv->gart_info.mapping.handle;
1157
1158                         if (dev_priv->flags & RADEON_IS_PCIE)
1159                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1160                         else
1161                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1162                         dev_priv->gart_info.gart_table_location =
1163                             DRM_ATI_GART_FB;
1164
1165                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1166                                   dev_priv->gart_info.addr,
1167                                   dev_priv->pcigart_offset);
1168                 } else {
1169                         if (dev_priv->flags & RADEON_IS_IGPGART)
1170                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1171                         else
1172                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1173                         dev_priv->gart_info.gart_table_location =
1174                             DRM_ATI_GART_MAIN;
1175                         dev_priv->gart_info.addr = NULL;
1176                         dev_priv->gart_info.bus_addr = 0;
1177                         if (dev_priv->flags & RADEON_IS_PCIE) {
1178                                 DRM_ERROR
1179                                     ("Cannot use PCI Express without GART in FB memory\n");
1180                                 radeon_do_cleanup_cp(dev);
1181                                 return -EINVAL;
1182                         }
1183                 }
1184
1185                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1186                         DRM_ERROR("failed to init PCI GART!\n");
1187                         radeon_do_cleanup_cp(dev);
1188                         return -ENOMEM;
1189                 }
1190
1191                 /* Turn on PCI GART */
1192                 radeon_set_pcigart(dev_priv, 1);
1193         }
1194
1195         /* Start with assuming that writeback doesn't work */
1196         dev_priv->writeback_works = 0;
1197
1198         radeon_cp_load_microcode(dev_priv);
1199         radeon_cp_init_ring_buffer(dev, dev_priv);
1200
1201         dev_priv->last_buf = 0;
1202
1203         radeon_do_engine_reset(dev);
1204         radeon_test_writeback(dev_priv);
1205
1206         return 0;
1207 }
1208
1209 static int radeon_do_cleanup_cp(struct drm_device * dev)
1210 {
1211         drm_radeon_private_t *dev_priv = dev->dev_private;
1212         DRM_DEBUG("\n");
1213
1214         /* Make sure interrupts are disabled here because the uninstall ioctl
1215          * may not have been called from userspace and after dev_private
1216          * is freed, it's too late.
1217          */
1218         if (dev->irq_enabled)
1219                 drm_irq_uninstall(dev);
1220
1221 #if __OS_HAS_AGP
1222         if (dev_priv->flags & RADEON_IS_AGP) {
1223                 if (dev_priv->cp_ring != NULL) {
1224                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1225                         dev_priv->cp_ring = NULL;
1226                 }
1227                 if (dev_priv->ring_rptr != NULL) {
1228                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1229                         dev_priv->ring_rptr = NULL;
1230                 }
1231                 if (dev->agp_buffer_map != NULL) {
1232                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1233                         dev->agp_buffer_map = NULL;
1234                 }
1235         } else
1236 #endif
1237         {
1238
1239                 if (dev_priv->gart_info.bus_addr) {
1240                         /* Turn off PCI GART */
1241                         radeon_set_pcigart(dev_priv, 0);
1242                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1243                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1244                 }
1245
1246                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1247                 {
1248                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1249                         dev_priv->gart_info.addr = 0;
1250                 }
1251         }
1252         /* only clear to the start of flags */
1253         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1254
1255         return 0;
1256 }
1257
1258 /* This code will reinit the Radeon CP hardware after a resume from disc.
1259  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1260  * here we make sure that all Radeon hardware initialisation is re-done without
1261  * affecting running applications.
1262  *
1263  * Charl P. Botha <http://cpbotha.net>
1264  */
1265 static int radeon_do_resume_cp(struct drm_device * dev)
1266 {
1267         drm_radeon_private_t *dev_priv = dev->dev_private;
1268
1269         if (!dev_priv) {
1270                 DRM_ERROR("Called with no initialization\n");
1271                 return -EINVAL;
1272         }
1273
1274         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1275
1276 #if __OS_HAS_AGP
1277         if (dev_priv->flags & RADEON_IS_AGP) {
1278                 /* Turn off PCI GART */
1279                 radeon_set_pcigart(dev_priv, 0);
1280         } else
1281 #endif
1282         {
1283                 /* Turn on PCI GART */
1284                 radeon_set_pcigart(dev_priv, 1);
1285         }
1286
1287         radeon_cp_load_microcode(dev_priv);
1288         radeon_cp_init_ring_buffer(dev, dev_priv);
1289
1290         radeon_do_engine_reset(dev);
1291         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1292
1293         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1294
1295         return 0;
1296 }
1297
1298 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1299 {
1300         drm_radeon_init_t *init = data;
1301
1302         LOCK_TEST_WITH_RETURN(dev, file_priv);
1303
1304         if (init->func == RADEON_INIT_R300_CP)
1305                 r300_init_reg_flags(dev);
1306
1307         switch (init->func) {
1308         case RADEON_INIT_CP:
1309         case RADEON_INIT_R200_CP:
1310         case RADEON_INIT_R300_CP:
1311                 return radeon_do_init_cp(dev, init);
1312         case RADEON_CLEANUP_CP:
1313                 return radeon_do_cleanup_cp(dev);
1314         }
1315
1316         return -EINVAL;
1317 }
1318
1319 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1320 {
1321         drm_radeon_private_t *dev_priv = dev->dev_private;
1322         DRM_DEBUG("\n");
1323
1324         LOCK_TEST_WITH_RETURN(dev, file_priv);
1325
1326         if (dev_priv->cp_running) {
1327                 DRM_DEBUG("while CP running\n");
1328                 return 0;
1329         }
1330         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1331                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1332                           dev_priv->cp_mode);
1333                 return 0;
1334         }
1335
1336         radeon_do_cp_start(dev_priv);
1337
1338         return 0;
1339 }
1340
1341 /* Stop the CP.  The engine must have been idled before calling this
1342  * routine.
1343  */
1344 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1345 {
1346         drm_radeon_private_t *dev_priv = dev->dev_private;
1347         drm_radeon_cp_stop_t *stop = data;
1348         int ret;
1349         DRM_DEBUG("\n");
1350
1351         LOCK_TEST_WITH_RETURN(dev, file_priv);
1352
1353         if (!dev_priv->cp_running)
1354                 return 0;
1355
1356         /* Flush any pending CP commands.  This ensures any outstanding
1357          * commands are exectuted by the engine before we turn it off.
1358          */
1359         if (stop->flush) {
1360                 radeon_do_cp_flush(dev_priv);
1361         }
1362
1363         /* If we fail to make the engine go idle, we return an error
1364          * code so that the DRM ioctl wrapper can try again.
1365          */
1366         if (stop->idle) {
1367                 ret = radeon_do_cp_idle(dev_priv);
1368                 if (ret)
1369                         return ret;
1370         }
1371
1372         /* Finally, we can turn off the CP.  If the engine isn't idle,
1373          * we will get some dropped triangles as they won't be fully
1374          * rendered before the CP is shut down.
1375          */
1376         radeon_do_cp_stop(dev_priv);
1377
1378         /* Reset the engine */
1379         radeon_do_engine_reset(dev);
1380
1381         return 0;
1382 }
1383
1384 void radeon_do_release(struct drm_device * dev)
1385 {
1386         drm_radeon_private_t *dev_priv = dev->dev_private;
1387         int i, ret;
1388
1389         if (dev_priv) {
1390                 if (dev_priv->cp_running) {
1391                         /* Stop the cp */
1392                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1393                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1394 #ifdef __linux__
1395                                 schedule();
1396 #else
1397 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1398                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1399                                        1);
1400 #else
1401                                 tsleep(&ret, PZERO, "rdnrel", 1);
1402 #endif
1403 #endif
1404                         }
1405                         radeon_do_cp_stop(dev_priv);
1406                         radeon_do_engine_reset(dev);
1407                 }
1408
1409                 /* Disable *all* interrupts */
1410                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1411                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1412
1413                 if (dev_priv->mmio) {   /* remove all surfaces */
1414                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1415                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1416                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1417                                              16 * i, 0);
1418                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1419                                              16 * i, 0);
1420                         }
1421                 }
1422
1423                 /* Free memory heap structures */
1424                 radeon_mem_takedown(&(dev_priv->gart_heap));
1425                 radeon_mem_takedown(&(dev_priv->fb_heap));
1426
1427                 /* deallocate kernel resources */
1428                 radeon_do_cleanup_cp(dev);
1429         }
1430 }
1431
1432 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1433  */
1434 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1435 {
1436         drm_radeon_private_t *dev_priv = dev->dev_private;
1437         DRM_DEBUG("\n");
1438
1439         LOCK_TEST_WITH_RETURN(dev, file_priv);
1440
1441         if (!dev_priv) {
1442                 DRM_DEBUG("called before init done\n");
1443                 return -EINVAL;
1444         }
1445
1446         radeon_do_cp_reset(dev_priv);
1447
1448         /* The CP is no longer running after an engine reset */
1449         dev_priv->cp_running = 0;
1450
1451         return 0;
1452 }
1453
1454 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1455 {
1456         drm_radeon_private_t *dev_priv = dev->dev_private;
1457         DRM_DEBUG("\n");
1458
1459         LOCK_TEST_WITH_RETURN(dev, file_priv);
1460
1461         return radeon_do_cp_idle(dev_priv);
1462 }
1463
1464 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1465  */
1466 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1467 {
1468
1469         return radeon_do_resume_cp(dev);
1470 }
1471
1472 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1473 {
1474         DRM_DEBUG("\n");
1475
1476         LOCK_TEST_WITH_RETURN(dev, file_priv);
1477
1478         return radeon_do_engine_reset(dev);
1479 }
1480
1481 /* ================================================================
1482  * Fullscreen mode
1483  */
1484
1485 /* KW: Deprecated to say the least:
1486  */
1487 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1488 {
1489         return 0;
1490 }
1491
1492 /* ================================================================
1493  * Freelist management
1494  */
1495
1496 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1497  *   bufs until freelist code is used.  Note this hides a problem with
1498  *   the scratch register * (used to keep track of last buffer
1499  *   completed) being written to before * the last buffer has actually
1500  *   completed rendering.
1501  *
1502  * KW:  It's also a good way to find free buffers quickly.
1503  *
1504  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1505  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1506  * we essentially have to do this, else old clients will break.
1507  *
1508  * However, it does leave open a potential deadlock where all the
1509  * buffers are held by other clients, which can't release them because
1510  * they can't get the lock.
1511  */
1512
1513 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1514 {
1515         struct drm_device_dma *dma = dev->dma;
1516         drm_radeon_private_t *dev_priv = dev->dev_private;
1517         drm_radeon_buf_priv_t *buf_priv;
1518         struct drm_buf *buf;
1519         int i, t;
1520         int start;
1521
1522         if (++dev_priv->last_buf >= dma->buf_count)
1523                 dev_priv->last_buf = 0;
1524
1525         start = dev_priv->last_buf;
1526
1527         for (t = 0; t < dev_priv->usec_timeout; t++) {
1528                 u32 done_age = GET_SCRATCH(1);
1529                 DRM_DEBUG("done_age = %d\n", done_age);
1530                 for (i = start; i < dma->buf_count; i++) {
1531                         buf = dma->buflist[i];
1532                         buf_priv = buf->dev_private;
1533                         if (buf->file_priv == NULL || (buf->pending &&
1534                                                        buf_priv->age <=
1535                                                        done_age)) {
1536                                 dev_priv->stats.requested_bufs++;
1537                                 buf->pending = 0;
1538                                 return buf;
1539                         }
1540                         start = 0;
1541                 }
1542
1543                 if (t) {
1544                         DRM_UDELAY(1);
1545                         dev_priv->stats.freelist_loops++;
1546                 }
1547         }
1548
1549         DRM_DEBUG("returning NULL!\n");
1550         return NULL;
1551 }
1552
1553 #if 0
1554 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1555 {
1556         struct drm_device_dma *dma = dev->dma;
1557         drm_radeon_private_t *dev_priv = dev->dev_private;
1558         drm_radeon_buf_priv_t *buf_priv;
1559         struct drm_buf *buf;
1560         int i, t;
1561         int start;
1562         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1563
1564         if (++dev_priv->last_buf >= dma->buf_count)
1565                 dev_priv->last_buf = 0;
1566
1567         start = dev_priv->last_buf;
1568         dev_priv->stats.freelist_loops++;
1569
1570         for (t = 0; t < 2; t++) {
1571                 for (i = start; i < dma->buf_count; i++) {
1572                         buf = dma->buflist[i];
1573                         buf_priv = buf->dev_private;
1574                         if (buf->file_priv == 0 || (buf->pending &&
1575                                                     buf_priv->age <=
1576                                                     done_age)) {
1577                                 dev_priv->stats.requested_bufs++;
1578                                 buf->pending = 0;
1579                                 return buf;
1580                         }
1581                 }
1582                 start = 0;
1583         }
1584
1585         return NULL;
1586 }
1587 #endif
1588
1589 void radeon_freelist_reset(struct drm_device * dev)
1590 {
1591         struct drm_device_dma *dma = dev->dma;
1592         drm_radeon_private_t *dev_priv = dev->dev_private;
1593         int i;
1594
1595         dev_priv->last_buf = 0;
1596         for (i = 0; i < dma->buf_count; i++) {
1597                 struct drm_buf *buf = dma->buflist[i];
1598                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1599                 buf_priv->age = 0;
1600         }
1601 }
1602
1603 /* ================================================================
1604  * CP command submission
1605  */
1606
1607 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1608 {
1609         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1610         int i;
1611         u32 last_head = GET_RING_HEAD(dev_priv);
1612
1613         for (i = 0; i < dev_priv->usec_timeout; i++) {
1614                 u32 head = GET_RING_HEAD(dev_priv);
1615
1616                 ring->space = (head - ring->tail) * sizeof(u32);
1617                 if (ring->space <= 0)
1618                         ring->space += ring->size;
1619                 if (ring->space > n)
1620                         return 0;
1621
1622                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1623
1624                 if (head != last_head)
1625                         i = 0;
1626                 last_head = head;
1627
1628                 DRM_UDELAY(1);
1629         }
1630
1631         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1632 #if RADEON_FIFO_DEBUG
1633         radeon_status(dev_priv);
1634         DRM_ERROR("failed!\n");
1635 #endif
1636         return -EBUSY;
1637 }
1638
1639 static int radeon_cp_get_buffers(struct drm_device *dev,
1640                                  struct drm_file *file_priv,
1641                                  struct drm_dma * d)
1642 {
1643         int i;
1644         struct drm_buf *buf;
1645
1646         for (i = d->granted_count; i < d->request_count; i++) {
1647                 buf = radeon_freelist_get(dev);
1648                 if (!buf)
1649                         return -EBUSY;  /* NOTE: broken client */
1650
1651                 buf->file_priv = file_priv;
1652
1653                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1654                                      sizeof(buf->idx)))
1655                         return -EFAULT;
1656                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1657                                      sizeof(buf->total)))
1658                         return -EFAULT;
1659
1660                 d->granted_count++;
1661         }
1662         return 0;
1663 }
1664
1665 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1666 {
1667         struct drm_device_dma *dma = dev->dma;
1668         int ret = 0;
1669         struct drm_dma *d = data;
1670
1671         LOCK_TEST_WITH_RETURN(dev, file_priv);
1672
1673         /* Please don't send us buffers.
1674          */
1675         if (d->send_count != 0) {
1676                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1677                           DRM_CURRENTPID, d->send_count);
1678                 return -EINVAL;
1679         }
1680
1681         /* We'll send you buffers.
1682          */
1683         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1684                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1685                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1686                 return -EINVAL;
1687         }
1688
1689         d->granted_count = 0;
1690
1691         if (d->request_count) {
1692                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1693         }
1694
1695         return ret;
1696 }
1697
1698 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1699 {
1700         drm_radeon_private_t *dev_priv;
1701         int ret = 0;
1702
1703         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1704         if (dev_priv == NULL)
1705                 return -ENOMEM;
1706
1707         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1708         dev->dev_private = (void *)dev_priv;
1709         dev_priv->flags = flags;
1710
1711         switch (flags & RADEON_FAMILY_MASK) {
1712         case CHIP_R100:
1713         case CHIP_RV200:
1714         case CHIP_R200:
1715         case CHIP_R300:
1716         case CHIP_R350:
1717         case CHIP_R420:
1718         case CHIP_RV410:
1719         case CHIP_RV515:
1720         case CHIP_R520:
1721         case CHIP_RV570:
1722         case CHIP_R580:
1723                 dev_priv->flags |= RADEON_HAS_HIERZ;
1724                 break;
1725         default:
1726                 /* all other chips have no hierarchical z buffer */
1727                 break;
1728         }
1729
1730         dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
1731         if (drm_device_is_agp(dev))
1732                 dev_priv->flags |= RADEON_IS_AGP;
1733         else if (drm_device_is_pcie(dev))
1734                 dev_priv->flags |= RADEON_IS_PCIE;
1735         else
1736                 dev_priv->flags |= RADEON_IS_PCI;
1737
1738         DRM_DEBUG("%s card detected\n",
1739                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1740         return ret;
1741 }
1742
1743 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1744  * have to find them.
1745  */
1746 int radeon_driver_firstopen(struct drm_device *dev)
1747 {
1748         int ret;
1749         drm_local_map_t *map;
1750         drm_radeon_private_t *dev_priv = dev->dev_private;
1751
1752         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1753
1754         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1755                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1756                          _DRM_READ_ONLY, &dev_priv->mmio);
1757         if (ret != 0)
1758                 return ret;
1759
1760         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1761         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1762                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1763                          _DRM_WRITE_COMBINING, &map);
1764         if (ret != 0)
1765                 return ret;
1766
1767         return 0;
1768 }
1769
1770 int radeon_driver_unload(struct drm_device *dev)
1771 {
1772         drm_radeon_private_t *dev_priv = dev->dev_private;
1773
1774         DRM_DEBUG("\n");
1775         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1776
1777         dev->dev_private = NULL;
1778         return 0;
1779 }