shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40 #define RADEON_FIFO_DEBUG       0
  41
  42 static int radeon_do_cleanup_cp(struct drm_device * dev);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  74             return RS690_READ_MCIND(dev_priv, addr);
  75         else
  76             return RS480_READ_MCIND(dev_priv, addr);
  77 }
  78
  79 u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr)
  80 {
  81         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  82                 return IGP_READ_MCIND(dev_priv, addr);
  83         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515)
  84                 return R500_READ_MCIND(dev_priv, addr);
  85         return 0;
  86 }
  87
  88 void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val)
  89 {
  90         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  91                 IGP_WRITE_MCIND(addr, val);
  92         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515)
  93                 R500_WRITE_MCIND(addr, val);
  94 }
  95
  96 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  97 {
  98
  99         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 100                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 101         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 102                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 103         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 104                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 105         else
 106                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 107 }
 108
 109 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 110 {
 111         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 112                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 113         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 114                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 115         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 116                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 117         else
 118                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 119 }
 120
 121 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 122 {
 123         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 124                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 125         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 126                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 127         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 128                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 129         else
 130                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 131 }
 132
 133 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 134 {
 135         u32 agp_base_hi = upper_32_bits(agp_base);
 136         u32 agp_base_lo = agp_base & 0xffffffff;
 137
 138         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 139                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 140                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 141         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 142                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 143                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 144         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 145                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 146                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 147         } else {
 148                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_base_lo);
 149                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 150                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 151         }
 152 }
 153
 154
 155 void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv)
 156 {
 157         if (!(dev_priv->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS))
 158                 return;
 159
 160         (void)RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 161         (void)RADEON_READ(RADEON_CRTC_GEN_CNTL);
 162 }
 163
 164 void radeon_pll_errata_after_data(struct drm_radeon_private *dev_priv)
 165 {
 166         /* This workarounds is necessary on RV100, RS100 and RS200 chips
 167          * or the chip could hang on a subsequent access
 168          */
 169         if (dev_priv->pll_errata & CHIP_ERRATA_PLL_DELAY)
 170                 udelay(5000);
 171
 172         /* This function is required to workaround a hardware bug in some (all?)
 173          * revisions of the R300.  This workaround should be called after every
 174          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
 175          * may not be correct.
 176          */
 177         if (dev_priv->pll_errata & CHIP_ERRATA_R300_CG) {
 178                 uint32_t save, tmp;
 179
 180                 save = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 181                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
 182                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, tmp);
 183                 tmp = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 184                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, save);
 185         }
 186 }
 187
 188 int RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
 189 {
 190         uint32_t data;
 191
 192         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
 193         radeon_pll_errata_after_index(dev_priv);
 194         data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 195         radeon_pll_errata_after_data(dev_priv);
 196         return data;
 197 }
 198
 199 void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data)
 200 {
 201         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f) | RADEON_PLL_WR_EN));
 202         radeon_pll_errata_after_index(dev_priv);
 203         RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, data);
 204         radeon_pll_errata_after_data(dev_priv);
 205 }
 206
 207 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 208 {
 209         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 210         return RADEON_READ(RADEON_PCIE_DATA);
 211 }
 212
 213 /* ATOM accessor methods */
 214 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 215 {
 216         uint32_t ret = radeon_read_mc_reg(info->dev->dev_private, reg);
 217
 218         //      DRM_DEBUG("(%x) = %x\n", reg, ret);
 219         return ret;
 220 }
 221
 222 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 223 {
 224   //    DRM_DEBUG("(%x,  %x)\n", reg, val);
 225         radeon_write_mc_reg(info->dev->dev_private, reg, val);
 226 }
 227
 228 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 229 {
 230         drm_radeon_private_t *dev_priv = info->dev->dev_private;
 231
 232         //      DRM_DEBUG("(%x,  %x)\n", reg*4, val);
 233         RADEON_WRITE(reg*4, val);
 234 }
 235
 236 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 237 {
 238         uint32_t ret;
 239         drm_radeon_private_t *dev_priv = info->dev->dev_private;
 240
 241         ret = RADEON_READ(reg*4);
 242         //      DRM_DEBUG("(%x) = %x\n", reg*4, ret);
 243         return ret;
 244 }
 245
 246 #if RADEON_FIFO_DEBUG
 247 static void radeon_status(drm_radeon_private_t * dev_priv)
 248 {
 249         printk("%s:\n", __FUNCTION__);
 250         printk("RBBM_STATUS = 0x%08x\n",
 251                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 252         printk("CP_RB_RTPR = 0x%08x\n",
 253                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 254         printk("CP_RB_WTPR = 0x%08x\n",
 255                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 256         printk("AIC_CNTL = 0x%08x\n",
 257                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 258         printk("AIC_STAT = 0x%08x\n",
 259                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 260         printk("AIC_PT_BASE = 0x%08x\n",
 261                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 262         printk("TLB_ADDR = 0x%08x\n",
 263                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 264         printk("TLB_DATA = 0x%08x\n",
 265                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 266 }
 267 #endif
 268
 269 /* ================================================================
 270  * Engine, FIFO control
 271  */
 272
 273 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 274 {
 275         u32 tmp;
 276         int i;
 277
 278         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 279
 280         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 281                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 282                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 283                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 284
 285                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 286                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 287                               & RADEON_RB3D_DC_BUSY)) {
 288                                 return 0;
 289                         }
 290                         DRM_UDELAY(1);
 291                 }
 292         } else {
 293                 /* 3D */
 294                 tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
 295                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 296                 RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
 297
 298                 /* 2D */
 299                 tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
 300                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 301                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 302
 303                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 304                         if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
 305                           & RADEON_RB3D_DC_BUSY)) {
 306                                 return 0;
 307                         }
 308                         DRM_UDELAY(1);
 309                 }
 310         }
 311
 312 #if RADEON_FIFO_DEBUG
 313         DRM_ERROR("failed!\n");
 314         radeon_status(dev_priv);
 315 #endif
 316         return -EBUSY;
 317 }
 318
 319 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 320 {
 321         int i;
 322
 323         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 324
 325         for (i = 0; i < dev_priv->usec_timeout; i++) {
 326                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 327                              & RADEON_RBBM_FIFOCNT_MASK);
 328                 if (slots >= entries)
 329                         return 0;
 330                 DRM_UDELAY(1);
 331         }
 332
 333 #if RADEON_FIFO_DEBUG
 334         DRM_ERROR("failed!\n");
 335         radeon_status(dev_priv);
 336 #endif
 337         return -EBUSY;
 338 }
 339
 340 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 341 {
 342         int i, ret;
 343
 344         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 345
 346         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 347         if (ret)
 348                 return ret;
 349
 350         for (i = 0; i < dev_priv->usec_timeout; i++) {
 351                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 352                       & RADEON_RBBM_ACTIVE)) {
 353                         radeon_do_pixcache_flush(dev_priv);
 354                         return 0;
 355                 }
 356                 DRM_UDELAY(1);
 357         }
 358
 359 #if RADEON_FIFO_DEBUG
 360         DRM_ERROR("failed!\n");
 361         radeon_status(dev_priv);
 362 #endif
 363         return -EBUSY;
 364 }
 365
 366 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 367 {
 368         uint32_t gb_tile_config, gb_pipe_sel = 0;
 369
 370         /* RS4xx/RS6xx/R4xx/R5xx */
 371         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 372                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 373                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 374         } else {
 375                 /* R3xx */
 376                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 377                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 378                         dev_priv->num_gb_pipes = 2;
 379                 } else {
 380                         /* R3Vxx */
 381                         dev_priv->num_gb_pipes = 1;
 382                 }
 383         }
 384         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 385
 386         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 387
 388         switch(dev_priv->num_gb_pipes) {
 389         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 390         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 391         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 392         default:
 393         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 394         }
 395
 396         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 397                 RADEON_WRITE_PLL(dev_priv, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 398                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 399         }
 400         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 401         radeon_do_wait_for_idle(dev_priv);
 402         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 403         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 404                                                R300_DC_AUTOFLUSH_ENABLE |
 405                                                R300_DC_DC_DISABLE_IGNORE_PE));
 406
 407
 408 }
 409
 410 /* ================================================================
 411  * CP control, initialization
 412  */
 413
 414 /* Load the microcode for the CP */
 415 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 416 {
 417         int i;
 418         DRM_DEBUG("\n");
 419
 420         radeon_do_wait_for_idle(dev_priv);
 421
 422         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 423
 424         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 425             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 426             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 427             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 428             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 429                 DRM_INFO("Loading R100 Microcode\n");
 430                 for (i = 0; i < 256; i++) {
 431                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 432                                      R100_cp_microcode[i][1]);
 433                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 434                                      R100_cp_microcode[i][0]);
 435                 }
 436         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 437                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 438                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 439                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 440                 DRM_INFO("Loading R200 Microcode\n");
 441                 for (i = 0; i < 256; i++) {
 442                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 443                                      R200_cp_microcode[i][1]);
 444                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 445                                      R200_cp_microcode[i][0]);
 446                 }
 447         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 448                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 449                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 450                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 451                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 452                 DRM_INFO("Loading R300 Microcode\n");
 453                 for (i = 0; i < 256; i++) {
 454                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 455                                      R300_cp_microcode[i][1]);
 456                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 457                                      R300_cp_microcode[i][0]);
 458                 }
 459         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 460                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 461                 DRM_INFO("Loading R400 Microcode\n");
 462                 for (i = 0; i < 256; i++) {
 463                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 464                                      R420_cp_microcode[i][1]);
 465                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 466                                      R420_cp_microcode[i][0]);
 467                 }
 468         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 469                 DRM_INFO("Loading RS690 Microcode\n");
 470                 for (i = 0; i < 256; i++) {
 471                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 472                                      RS690_cp_microcode[i][1]);
 473                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 474                                      RS690_cp_microcode[i][0]);
 475                 }
 476         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 477                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 478                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 479                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 480                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 481                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 482                 DRM_INFO("Loading R500 Microcode\n");
 483                 for (i = 0; i < 256; i++) {
 484                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 485                                      R520_cp_microcode[i][1]);
 486                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 487                                      R520_cp_microcode[i][0]);
 488                 }
 489         }
 490 }
 491
 492 /* Flush any pending commands to the CP.  This should only be used just
 493  * prior to a wait for idle, as it informs the engine that the command
 494  * stream is ending.
 495  */
 496 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 497 {
 498         DRM_DEBUG("\n");
 499 #if 0
 500         u32 tmp;
 501
 502         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 503         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 504 #endif
 505 }
 506
 507 /* Wait for the CP to go idle.
 508  */
 509 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 510 {
 511         RING_LOCALS;
 512         DRM_DEBUG("\n");
 513
 514         BEGIN_RING(6);
 515
 516         RADEON_PURGE_CACHE();
 517         RADEON_PURGE_ZCACHE();
 518         RADEON_WAIT_UNTIL_IDLE();
 519
 520         ADVANCE_RING();
 521         COMMIT_RING();
 522
 523         return radeon_do_wait_for_idle(dev_priv);
 524 }
 525
 526 /* Start the Command Processor.
 527  */
 528 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 529 {
 530         RING_LOCALS;
 531         DRM_DEBUG("\n");
 532
 533         radeon_do_wait_for_idle(dev_priv);
 534
 535         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 536
 537         dev_priv->cp_running = 1;
 538
 539         BEGIN_RING(6);
 540
 541         RADEON_PURGE_CACHE();
 542         RADEON_PURGE_ZCACHE();
 543         RADEON_WAIT_UNTIL_IDLE();
 544
 545         ADVANCE_RING();
 546         COMMIT_RING();
 547 }
 548
 549 /* Reset the Command Processor.  This will not flush any pending
 550  * commands, so you must wait for the CP command stream to complete
 551  * before calling this routine.
 552  */
 553 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 554 {
 555         u32 cur_read_ptr;
 556         DRM_DEBUG("\n");
 557
 558         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 559         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 560         SET_RING_HEAD(dev_priv, cur_read_ptr);
 561         dev_priv->ring.tail = cur_read_ptr;
 562 }
 563
 564 /* Stop the Command Processor.  This will not flush any pending
 565  * commands, so you must flush the command stream and wait for the CP
 566  * to go idle before calling this routine.
 567  */
 568 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 569 {
 570         DRM_DEBUG("\n");
 571
 572         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 573
 574         dev_priv->cp_running = 0;
 575 }
 576
 577 /* Reset the engine.  This will stop the CP if it is running.
 578  */
 579 static int radeon_do_engine_reset(struct drm_device * dev)
 580 {
 581         drm_radeon_private_t *dev_priv = dev->dev_private;
 582         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 583         DRM_DEBUG("\n");
 584
 585         radeon_do_pixcache_flush(dev_priv);
 586
 587         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 588                 /* may need something similar for newer chips */
 589                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 590                 mclk_cntl = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
 591
 592                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, (mclk_cntl |
 593                                                               RADEON_FORCEON_MCLKA |
 594                                                               RADEON_FORCEON_MCLKB |
 595                                                               RADEON_FORCEON_YCLKA |
 596                                                               RADEON_FORCEON_YCLKB |
 597                                                               RADEON_FORCEON_MC |
 598                                                               RADEON_FORCEON_AIC));
 599         }
 600
 601         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 602
 603         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 604                                               RADEON_SOFT_RESET_CP |
 605                                               RADEON_SOFT_RESET_HI |
 606                                               RADEON_SOFT_RESET_SE |
 607                                               RADEON_SOFT_RESET_RE |
 608                                               RADEON_SOFT_RESET_PP |
 609                                               RADEON_SOFT_RESET_E2 |
 610                                               RADEON_SOFT_RESET_RB));
 611         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 612         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 613                                               ~(RADEON_SOFT_RESET_CP |
 614                                                 RADEON_SOFT_RESET_HI |
 615                                                 RADEON_SOFT_RESET_SE |
 616                                                 RADEON_SOFT_RESET_RE |
 617                                                 RADEON_SOFT_RESET_PP |
 618                                                 RADEON_SOFT_RESET_E2 |
 619                                                 RADEON_SOFT_RESET_RB)));
 620         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 621
 622         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 623                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
 624                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 625                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 626         }
 627
 628         /* setup the raster pipes */
 629         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 630             radeon_init_pipes(dev_priv);
 631
 632         /* Reset the CP ring */
 633         radeon_do_cp_reset(dev_priv);
 634
 635         /* The CP is no longer running after an engine reset */
 636         dev_priv->cp_running = 0;
 637
 638         /* Reset any pending vertex, indirect buffers */
 639         if (dev->dma)
 640                 radeon_freelist_reset(dev);
 641
 642         return 0;
 643 }
 644
 645 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 646                                        drm_radeon_private_t * dev_priv)
 647 {
 648         u32 ring_start, cur_read_ptr;
 649         u32 tmp;
 650
 651         /* Initialize the memory controller. With new memory map, the fb location
 652          * is not changed, it should have been properly initialized already. Part
 653          * of the problem is that the code below is bogus, assuming the GART is
 654          * always appended to the fb which is not necessarily the case
 655          */
 656         if (!dev_priv->new_memmap)
 657                 radeon_write_fb_location(dev_priv,
 658                                          ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 659                                          | (dev_priv->fb_location >> 16));
 660
 661         if (dev_priv->mm.ring) {
 662                 ring_start = dev_priv->mm.ring->offset +
 663                         dev_priv->gart_vm_start;
 664         } else
 665 #if __OS_HAS_AGP
 666         if (dev_priv->flags & RADEON_IS_AGP) {
 667                 radeon_write_agp_base(dev_priv, dev->agp->base);
 668
 669                 radeon_write_agp_location(dev_priv,
 670                              (((dev_priv->gart_vm_start - 1 +
 671                                 dev_priv->gart_size) & 0xffff0000) |
 672                               (dev_priv->gart_vm_start >> 16)));
 673
 674                 ring_start = (dev_priv->cp_ring->offset
 675                               - dev->agp->base
 676                               + dev_priv->gart_vm_start);
 677         } else
 678 #endif
 679                 ring_start = (dev_priv->cp_ring->offset
 680                               - (unsigned long)dev->sg->virtual
 681                               + dev_priv->gart_vm_start);
 682
 683         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 684
 685         /* Set the write pointer delay */
 686         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 687
 688         /* Initialize the ring buffer's read and write pointers */
 689         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 690         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 691         SET_RING_HEAD(dev_priv, cur_read_ptr);
 692         dev_priv->ring.tail = cur_read_ptr;
 693
 694
 695         if (dev_priv->mm.ring_read_ptr) {
 696                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 697                              dev_priv->mm.ring_read_ptr->offset +
 698                              dev_priv->gart_vm_start);
 699         } else
 700 #if __OS_HAS_AGP
 701         if (dev_priv->flags & RADEON_IS_AGP) {
 702                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 703                              dev_priv->ring_rptr->offset
 704                              - dev->agp->base + dev_priv->gart_vm_start);
 705         } else
 706 #endif
 707         {
 708                 struct drm_sg_mem *entry = dev->sg;
 709                 unsigned long tmp_ofs, page_ofs;
 710
 711                 tmp_ofs = dev_priv->ring_rptr->offset -
 712                                 (unsigned long)dev->sg->virtual;
 713                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 714
 715                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 716                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 717                           (unsigned long)entry->busaddr[page_ofs],
 718                           entry->handle + tmp_ofs);
 719         }
 720
 721         /* Set ring buffer size */
 722 #ifdef __BIG_ENDIAN
 723         RADEON_WRITE(RADEON_CP_RB_CNTL,
 724                      RADEON_BUF_SWAP_32BIT |
 725                      (dev_priv->ring.fetch_size_l2ow << 18) |
 726                      (dev_priv->ring.rptr_update_l2qw << 8) |
 727                      dev_priv->ring.size_l2qw);
 728 #else
 729         RADEON_WRITE(RADEON_CP_RB_CNTL,
 730                      (dev_priv->ring.fetch_size_l2ow << 18) |
 731                      (dev_priv->ring.rptr_update_l2qw << 8) |
 732                      dev_priv->ring.size_l2qw);
 733 #endif
 734
 735         /* Start with assuming that writeback doesn't work */
 736         dev_priv->writeback_works = 0;
 737
 738         /* Initialize the scratch register pointer.  This will cause
 739          * the scratch register values to be written out to memory
 740          * whenever they are updated.
 741          *
 742          * We simply put this behind the ring read pointer, this works
 743          * with PCI GART as well as (whatever kind of) AGP GART
 744          */
 745         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 746                      + RADEON_SCRATCH_REG_OFFSET);
 747
 748         if (dev_priv->mm.ring_read_ptr)
 749                 dev_priv->scratch = ((__volatile__ u32 *)
 750                                      dev_priv->mm.ring_read_ptr_map.virtual +
 751                                      (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 752         else
 753                 dev_priv->scratch = ((__volatile__ u32 *)
 754                                      dev_priv->ring_rptr->handle +
 755                                      (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 756
 757         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 758
 759         /* Turn on bus mastering */
 760         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 761         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 762
 763         dev_priv->scratch[0] = 0;
 764         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 765
 766         dev_priv->scratch[1] = 0;
 767         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 768
 769         dev_priv->scratch[2] = 0;
 770         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 771
 772         radeon_do_wait_for_idle(dev_priv);
 773
 774         /* Sync everything up */
 775         RADEON_WRITE(RADEON_ISYNC_CNTL,
 776                      (RADEON_ISYNC_ANY2D_IDLE3D |
 777                       RADEON_ISYNC_ANY3D_IDLE2D |
 778                       RADEON_ISYNC_WAIT_IDLEGUI |
 779                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 780
 781 }
 782
 783 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 784 {
 785         u32 tmp;
 786         void *ring_read_ptr;
 787
 788         if (dev_priv->mm.ring_read_ptr)
 789                 ring_read_ptr = dev_priv->mm.ring_read_ptr_map.virtual;
 790         else
 791                 ring_read_ptr = dev_priv->ring_rptr->handle;
 792
 793         /* Writeback doesn't seem to work everywhere, test it here and possibly
 794          * enable it if it appears to work
 795          */
 796         writel(0, ring_read_ptr + RADEON_SCRATCHOFF(1));
 797         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 798
 799         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 800                 if (readl(ring_read_ptr + RADEON_SCRATCHOFF(1)) ==
 801                     0xdeadbeef)
 802                         break;
 803                 DRM_UDELAY(1);
 804         }
 805
 806         if (tmp < dev_priv->usec_timeout) {
 807                 dev_priv->writeback_works = 1;
 808                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 809         } else {
 810                 dev_priv->writeback_works = 0;
 811                 DRM_INFO("writeback test failed\n");
 812         }
 813         if (radeon_no_wb == 1) {
 814                 dev_priv->writeback_works = 0;
 815                 DRM_INFO("writeback forced off\n");
 816         }
 817
 818         if (!dev_priv->writeback_works) {
 819                 /* Disable writeback to avoid unnecessary bus master transfers */
 820                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
 821                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 822         }
 823 }
 824
 825 /* Enable or disable IGP GART on the chip */
 826 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 827 {
 828         u32 temp;
 829
 830         if (on) {
 831                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 832                          dev_priv->gart_vm_start,
 833                          (long)dev_priv->gart_info.bus_addr,
 834                          dev_priv->gart_size);
 835
 836                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 837
 838                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 839                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 840                                                              RS690_BLOCK_GFX_D3_EN));
 841                 else
 842                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 843
 844                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 845                                                                RS480_VA_SIZE_32MB));
 846
 847                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 848                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 849                                                         RS480_TLB_ENABLE |
 850                                                         RS480_GTW_LAC_EN |
 851                                                         RS480_1LEVEL_GART));
 852
 853                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 854                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 855                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 856
 857                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 858                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 859                                                       RS480_REQ_TYPE_SNOOP_DIS));
 860
 861                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 862                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
 863                                         (unsigned int)dev_priv->gart_vm_start);
 864                         IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
 865                 } else {
 866                         RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
 867                         RADEON_WRITE(RS480_AGP_BASE_2, 0);
 868                 }
 869
 870                 dev_priv->gart_size = 32*1024*1024;
 871                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 872                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 873
 874                 radeon_write_agp_location(dev_priv, temp);
 875
 876                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 877                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 878                                                                RS480_VA_SIZE_32MB));
 879
 880                 do {
 881                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 882                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 883                                 break;
 884                         DRM_UDELAY(1);
 885                 } while(1);
 886
 887                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 888                                 RS480_GART_CACHE_INVALIDATE);
 889
 890                 do {
 891                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 892                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 893                                 break;
 894                         DRM_UDELAY(1);
 895                 } while(1);
 896
 897                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 898         } else {
 899                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 900         }
 901 }
 902
 903 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 904 {
 905         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 906         if (on) {
 907
 908                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 909                           dev_priv->gart_vm_start,
 910                           (long)dev_priv->gart_info.bus_addr,
 911                           dev_priv->gart_size);
 912                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 913                                   dev_priv->gart_vm_start);
 914                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 915                                   dev_priv->gart_info.bus_addr);
 916                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 917                                   dev_priv->gart_vm_start);
 918                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 919                                   dev_priv->gart_vm_start +
 920                                   dev_priv->gart_size - 1);
 921
 922                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 923
 924                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 925                                   RADEON_PCIE_TX_GART_EN);
 926         } else {
 927                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 928                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 929         }
 930 }
 931
 932 /* Enable or disable PCI GART on the chip */
 933 void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 934 {
 935         u32 tmp;
 936
 937         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 938             (dev_priv->flags & RADEON_IS_IGPGART)) {
 939                 radeon_set_igpgart(dev_priv, on);
 940                 return;
 941         }
 942
 943         if (dev_priv->flags & RADEON_IS_PCIE) {
 944                 radeon_set_pciegart(dev_priv, on);
 945                 return;
 946         }
 947
 948         tmp = RADEON_READ(RADEON_AIC_CNTL);
 949
 950         if (on) {
 951                 RADEON_WRITE(RADEON_AIC_CNTL,
 952                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 953
 954                 /* set PCI GART page-table base address
 955                  */
 956                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 957
 958                 /* set address range for PCI address translate
 959                  */
 960                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 961                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 962                              + dev_priv->gart_size - 1);
 963
 964                 /* Turn off AGP aperture -- is this required for PCI GART?
 965                  */
 966                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 967                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 968         } else {
 969                 RADEON_WRITE(RADEON_AIC_CNTL,
 970                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 971         }
 972 }
 973
 974 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
 975                              struct drm_file *file_priv)
 976 {
 977         drm_radeon_private_t *dev_priv = dev->dev_private;
 978         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
 979
 980         DRM_DEBUG("\n");
 981
 982         /* if we require new memory map but we don't have it fail */
 983         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 984                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 985                 radeon_do_cleanup_cp(dev);
 986                 return -EINVAL;
 987         }
 988
 989         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
 990         {
 991                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 992                 dev_priv->flags &= ~RADEON_IS_AGP;
 993         }
 994         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 995                  && !init->is_pci)
 996         {
 997                 DRM_DEBUG("Restoring AGP flag\n");
 998                 dev_priv->flags |= RADEON_IS_AGP;
 999         }
1000
1001         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1002                 DRM_ERROR("PCI GART memory not allocated!\n");
1003                 radeon_do_cleanup_cp(dev);
1004                 return -EINVAL;
1005         }
1006
1007         dev_priv->usec_timeout = init->usec_timeout;
1008         if (dev_priv->usec_timeout < 1 ||
1009             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1010                 DRM_DEBUG("TIMEOUT problem!\n");
1011                 radeon_do_cleanup_cp(dev);
1012                 return -EINVAL;
1013         }
1014
1015         /* Enable vblank on CRTC1 for older X servers
1016          */
1017         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1018
1019         dev_priv->do_boxes = 0;
1020         dev_priv->cp_mode = init->cp_mode;
1021
1022         /* We don't support anything other than bus-mastering ring mode,
1023          * but the ring can be in either AGP or PCI space for the ring
1024          * read pointer.
1025          */
1026         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1027             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1028                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1029                 radeon_do_cleanup_cp(dev);
1030                 return -EINVAL;
1031         }
1032
1033         switch (init->fb_bpp) {
1034         case 16:
1035                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1036                 break;
1037         case 32:
1038         default:
1039                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1040                 break;
1041         }
1042         dev_priv->front_offset = init->front_offset;
1043         dev_priv->front_pitch = init->front_pitch;
1044         dev_priv->back_offset = init->back_offset;
1045         dev_priv->back_pitch = init->back_pitch;
1046
1047         switch (init->depth_bpp) {
1048         case 16:
1049                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1050                 break;
1051         case 32:
1052         default:
1053                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1054                 break;
1055         }
1056         dev_priv->depth_offset = init->depth_offset;
1057         dev_priv->depth_pitch = init->depth_pitch;
1058
1059         /* Hardware state for depth clears.  Remove this if/when we no
1060          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1061          * all values to prevent unwanted 3D state from slipping through
1062          * and screwing with the clear operation.
1063          */
1064         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1065                                            (dev_priv->color_fmt << 10) |
1066                                            (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
1067
1068         dev_priv->depth_clear.rb3d_zstencilcntl =
1069             (dev_priv->depth_fmt |
1070              RADEON_Z_TEST_ALWAYS |
1071              RADEON_STENCIL_TEST_ALWAYS |
1072              RADEON_STENCIL_S_FAIL_REPLACE |
1073              RADEON_STENCIL_ZPASS_REPLACE |
1074              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1075
1076         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1077                                          RADEON_BFACE_SOLID |
1078                                          RADEON_FFACE_SOLID |
1079                                          RADEON_FLAT_SHADE_VTX_LAST |
1080                                          RADEON_DIFFUSE_SHADE_FLAT |
1081                                          RADEON_ALPHA_SHADE_FLAT |
1082                                          RADEON_SPECULAR_SHADE_FLAT |
1083                                          RADEON_FOG_SHADE_FLAT |
1084                                          RADEON_VTX_PIX_CENTER_OGL |
1085                                          RADEON_ROUND_MODE_TRUNC |
1086                                          RADEON_ROUND_PREC_8TH_PIX);
1087
1088
1089         dev_priv->ring_offset = init->ring_offset;
1090         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1091         dev_priv->buffers_offset = init->buffers_offset;
1092         dev_priv->gart_textures_offset = init->gart_textures_offset;
1093
1094         master_priv->sarea = drm_getsarea(dev);
1095         if (!master_priv->sarea) {
1096                 DRM_ERROR("could not find sarea!\n");
1097                 radeon_do_cleanup_cp(dev);
1098                 return -EINVAL;
1099         }
1100
1101         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1102         if (!dev_priv->cp_ring) {
1103                 DRM_ERROR("could not find cp ring region!\n");
1104                 radeon_do_cleanup_cp(dev);
1105                 return -EINVAL;
1106         }
1107         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1108         if (!dev_priv->ring_rptr) {
1109                 DRM_ERROR("could not find ring read pointer!\n");
1110                 radeon_do_cleanup_cp(dev);
1111                 return -EINVAL;
1112         }
1113         dev->agp_buffer_token = init->buffers_offset;
1114         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1115         if (!dev->agp_buffer_map) {
1116                 DRM_ERROR("could not find dma buffer region!\n");
1117                 radeon_do_cleanup_cp(dev);
1118                 return -EINVAL;
1119         }
1120
1121         if (init->gart_textures_offset) {
1122                 dev_priv->gart_textures =
1123                     drm_core_findmap(dev, init->gart_textures_offset);
1124                 if (!dev_priv->gart_textures) {
1125                         DRM_ERROR("could not find GART texture region!\n");
1126                         radeon_do_cleanup_cp(dev);
1127                         return -EINVAL;
1128                 }
1129         }
1130
1131 #if __OS_HAS_AGP
1132         if (dev_priv->flags & RADEON_IS_AGP) {
1133                 drm_core_ioremap(dev_priv->cp_ring, dev);
1134                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1135                 drm_core_ioremap(dev->agp_buffer_map, dev);
1136                 if (!dev_priv->cp_ring->handle ||
1137                     !dev_priv->ring_rptr->handle ||
1138                     !dev->agp_buffer_map->handle) {
1139                         DRM_ERROR("could not find ioremap agp regions!\n");
1140                         radeon_do_cleanup_cp(dev);
1141                         return -EINVAL;
1142                 }
1143         } else
1144 #endif
1145         {
1146                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1147                 dev_priv->ring_rptr->handle =
1148                     (void *)dev_priv->ring_rptr->offset;
1149                 dev->agp_buffer_map->handle =
1150                     (void *)dev->agp_buffer_map->offset;
1151
1152                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1153                           dev_priv->cp_ring->handle);
1154                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1155                           dev_priv->ring_rptr->handle);
1156                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1157                           dev->agp_buffer_map->handle);
1158         }
1159
1160         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1161         dev_priv->fb_size =
1162                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1163                 - dev_priv->fb_location;
1164
1165         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1166                                         ((dev_priv->front_offset
1167                                           + dev_priv->fb_location) >> 10));
1168
1169         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1170                                        ((dev_priv->back_offset
1171                                          + dev_priv->fb_location) >> 10));
1172
1173         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1174                                         ((dev_priv->depth_offset
1175                                           + dev_priv->fb_location) >> 10));
1176
1177         dev_priv->gart_size = init->gart_size;
1178
1179         /* New let's set the memory map ... */
1180         if (dev_priv->new_memmap) {
1181                 u32 base = 0;
1182
1183                 DRM_INFO("Setting GART location based on new memory map\n");
1184
1185                 /* If using AGP, try to locate the AGP aperture at the same
1186                  * location in the card and on the bus, though we have to
1187                  * align it down.
1188                  */
1189 #if __OS_HAS_AGP
1190                 if (dev_priv->flags & RADEON_IS_AGP) {
1191                         base = dev->agp->base;
1192                         /* Check if valid */
1193                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1194                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1195                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1196                                          dev->agp->base);
1197                                 base = 0;
1198                         }
1199                 }
1200 #endif
1201                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1202                 if (base == 0) {
1203                         base = dev_priv->fb_location + dev_priv->fb_size;
1204                         if (base < dev_priv->fb_location ||
1205                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1206                                 base = dev_priv->fb_location
1207                                         - dev_priv->gart_size;
1208                 }
1209                 dev_priv->gart_vm_start = base & 0xffc00000u;
1210                 if (dev_priv->gart_vm_start != base)
1211                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1212                                  base, dev_priv->gart_vm_start);
1213         } else {
1214                 DRM_INFO("Setting GART location based on old memory map\n");
1215                 dev_priv->gart_vm_start = dev_priv->fb_location +
1216                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1217         }
1218
1219 #if __OS_HAS_AGP
1220         if (dev_priv->flags & RADEON_IS_AGP)
1221                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1222                                                  - dev->agp->base
1223                                                  + dev_priv->gart_vm_start);
1224         else
1225 #endif
1226                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1227                                         - (unsigned long)dev->sg->virtual
1228                                         + dev_priv->gart_vm_start);
1229
1230         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1231         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1232         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1233                   dev_priv->gart_buffers_offset);
1234
1235         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1236         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1237                               + init->ring_size / sizeof(u32));
1238         dev_priv->ring.size = init->ring_size;
1239         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1240
1241         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1242         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1243
1244         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1245         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1246
1247         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1248
1249         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1250
1251 #if __OS_HAS_AGP
1252         if (dev_priv->flags & RADEON_IS_AGP) {
1253                 /* Turn off PCI GART */
1254                 radeon_set_pcigart(dev_priv, 0);
1255         } else
1256 #endif
1257         {
1258                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1259                 /* if we have an offset set from userspace */
1260                 if (dev_priv->pcigart_offset_set) {
1261
1262                         /* if it came from userspace - remap it */
1263                         if (dev_priv->pcigart_offset_set == 1) {
1264                                 dev_priv->gart_info.bus_addr =
1265                                         dev_priv->pcigart_offset + dev_priv->fb_location;
1266                                 dev_priv->gart_info.mapping.offset =
1267                                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1268                                 dev_priv->gart_info.mapping.size =
1269                                         dev_priv->gart_info.table_size;
1270
1271                                 /* this is done by the mm now */
1272                                 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1273                                 dev_priv->gart_info.addr =
1274                                         dev_priv->gart_info.mapping.handle;
1275
1276                                 memset(dev_priv->gart_info.addr, 0, dev_priv->gart_info.table_size);
1277                                 if (dev_priv->flags & RADEON_IS_PCIE)
1278                                         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1279                                 else
1280                                         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1281                                 dev_priv->gart_info.gart_table_location =
1282                                         DRM_ATI_GART_FB;
1283
1284                                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1285                                           dev_priv->gart_info.addr,
1286                                           dev_priv->pcigart_offset);
1287                         }
1288                 } else {
1289
1290                         if (dev_priv->flags & RADEON_IS_PCIE) {
1291                                 DRM_ERROR
1292                                     ("Cannot use PCI Express without GART in FB memory\n");
1293                                 radeon_do_cleanup_cp(dev);
1294                                 return -EINVAL;
1295                         }
1296                         if (dev_priv->flags & RADEON_IS_IGPGART)
1297                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1298                         else
1299                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1300                         dev_priv->gart_info.gart_table_location =
1301                             DRM_ATI_GART_MAIN;
1302                         dev_priv->gart_info.addr = NULL;
1303                         dev_priv->gart_info.bus_addr = 0;
1304
1305                 }
1306
1307                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1308                         DRM_ERROR("failed to init PCI GART!\n");
1309                         radeon_do_cleanup_cp(dev);
1310                         return -ENOMEM;
1311                 }
1312
1313                 /* Turn on PCI GART */
1314                 radeon_set_pcigart(dev_priv, 1);
1315         }
1316
1317         radeon_cp_load_microcode(dev_priv);
1318         radeon_cp_init_ring_buffer(dev, dev_priv);
1319
1320         dev_priv->last_buf = 0;
1321
1322         radeon_do_engine_reset(dev);
1323         radeon_test_writeback(dev_priv);
1324
1325         return 0;
1326 }
1327
1328 static int radeon_do_cleanup_cp(struct drm_device * dev)
1329 {
1330         drm_radeon_private_t *dev_priv = dev->dev_private;
1331         DRM_DEBUG("\n");
1332
1333         /* Make sure interrupts are disabled here because the uninstall ioctl
1334          * may not have been called from userspace and after dev_private
1335          * is freed, it's too late.
1336          */
1337         if (dev->irq_enabled)
1338                 drm_irq_uninstall(dev);
1339
1340 #if __OS_HAS_AGP
1341         if (dev_priv->flags & RADEON_IS_AGP) {
1342                 if (dev_priv->cp_ring != NULL) {
1343                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1344                         dev_priv->cp_ring = NULL;
1345                 }
1346                 if (dev_priv->ring_rptr != NULL) {
1347                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1348                         dev_priv->ring_rptr = NULL;
1349                 }
1350                 if (dev->agp_buffer_map != NULL) {
1351                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1352                         dev->agp_buffer_map = NULL;
1353                 }
1354         } else
1355 #endif
1356         {
1357
1358                 if (dev_priv->gart_info.bus_addr) {
1359                         /* Turn off PCI GART */
1360                         radeon_set_pcigart(dev_priv, 0);
1361                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1362                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1363                 }
1364
1365                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1366                 {
1367                         if (dev_priv->pcigart_offset_set == 1) {
1368                                 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1369                                 dev_priv->gart_info.addr = NULL;
1370                         }
1371                 }
1372         }
1373         /* only clear to the start of flags */
1374         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1375
1376         return 0;
1377 }
1378
1379 /* This code will reinit the Radeon CP hardware after a resume from disc.
1380  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1381  * here we make sure that all Radeon hardware initialisation is re-done without
1382  * affecting running applications.
1383  *
1384  * Charl P. Botha <http://cpbotha.net>
1385  */
1386 static int radeon_do_resume_cp(struct drm_device * dev)
1387 {
1388         drm_radeon_private_t *dev_priv = dev->dev_private;
1389
1390         if (!dev_priv) {
1391                 DRM_ERROR("Called with no initialization\n");
1392                 return -EINVAL;
1393         }
1394
1395         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1396
1397 #if __OS_HAS_AGP
1398         if (dev_priv->flags & RADEON_IS_AGP) {
1399                 /* Turn off PCI GART */
1400                 radeon_set_pcigart(dev_priv, 0);
1401         } else
1402 #endif
1403         {
1404                 /* Turn on PCI GART */
1405                 radeon_set_pcigart(dev_priv, 1);
1406         }
1407
1408         radeon_cp_load_microcode(dev_priv);
1409         radeon_cp_init_ring_buffer(dev, dev_priv);
1410
1411         radeon_do_engine_reset(dev);
1412
1413         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1414
1415         return 0;
1416 }
1417
1418 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1419 {
1420         drm_radeon_init_t *init = data;
1421
1422         /* on a modesetting driver ignore this stuff */
1423         if (drm_core_check_feature(dev, DRIVER_MODESET))
1424                 return 0;
1425
1426         LOCK_TEST_WITH_RETURN(dev, file_priv);
1427
1428         if (init->func == RADEON_INIT_R300_CP)
1429                 r300_init_reg_flags(dev);
1430
1431         switch (init->func) {
1432         case RADEON_INIT_CP:
1433         case RADEON_INIT_R200_CP:
1434         case RADEON_INIT_R300_CP:
1435                 return radeon_do_init_cp(dev, init, file_priv);
1436         case RADEON_CLEANUP_CP:
1437                 return radeon_do_cleanup_cp(dev);
1438         }
1439
1440         return -EINVAL;
1441 }
1442
1443 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1444 {
1445         drm_radeon_private_t *dev_priv = dev->dev_private;
1446         DRM_DEBUG("\n");
1447
1448         if (drm_core_check_feature(dev, DRIVER_MODESET))
1449                 return 0;
1450
1451         LOCK_TEST_WITH_RETURN(dev, file_priv);
1452
1453         if (dev_priv->cp_running) {
1454                 DRM_DEBUG("while CP running\n");
1455                 return 0;
1456         }
1457         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1458                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1459                           dev_priv->cp_mode);
1460                 return 0;
1461         }
1462
1463         radeon_do_cp_start(dev_priv);
1464
1465         return 0;
1466 }
1467
1468 /* Stop the CP.  The engine must have been idled before calling this
1469  * routine.
1470  */
1471 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1472 {
1473         drm_radeon_private_t *dev_priv = dev->dev_private;
1474         drm_radeon_cp_stop_t *stop = data;
1475         int ret;
1476         DRM_DEBUG("\n");
1477
1478         if (drm_core_check_feature(dev, DRIVER_MODESET))
1479                 return 0;
1480
1481         LOCK_TEST_WITH_RETURN(dev, file_priv);
1482
1483         if (!dev_priv->cp_running)
1484                 return 0;
1485
1486         /* Flush any pending CP commands.  This ensures any outstanding
1487          * commands are exectuted by the engine before we turn it off.
1488          */
1489         if (stop->flush) {
1490                 radeon_do_cp_flush(dev_priv);
1491         }
1492
1493         /* If we fail to make the engine go idle, we return an error
1494          * code so that the DRM ioctl wrapper can try again.
1495          */
1496         if (stop->idle) {
1497                 ret = radeon_do_cp_idle(dev_priv);
1498                 if (ret)
1499                         return ret;
1500         }
1501
1502         /* Finally, we can turn off the CP.  If the engine isn't idle,
1503          * we will get some dropped triangles as they won't be fully
1504          * rendered before the CP is shut down.
1505          */
1506         radeon_do_cp_stop(dev_priv);
1507
1508         /* Reset the engine */
1509         radeon_do_engine_reset(dev);
1510
1511         return 0;
1512 }
1513
1514 void radeon_do_release(struct drm_device * dev)
1515 {
1516         drm_radeon_private_t *dev_priv = dev->dev_private;
1517         int i, ret;
1518
1519         if (drm_core_check_feature(dev, DRIVER_MODESET))
1520                 return;
1521
1522         if (dev_priv) {
1523                 if (dev_priv->cp_running) {
1524                         /* Stop the cp */
1525                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1526                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1527 #ifdef __linux__
1528                                 schedule();
1529 #else
1530 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1531                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1532                                        1);
1533 #else
1534                                 tsleep(&ret, PZERO, "rdnrel", 1);
1535 #endif
1536 #endif
1537                         }
1538                         radeon_do_cp_stop(dev_priv);
1539                         radeon_do_engine_reset(dev);
1540                 }
1541
1542                 /* Disable *all* interrupts */
1543                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1544                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1545
1546                 if (dev_priv->mmio) {   /* remove all surfaces */
1547                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1548                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1549                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1550                                              16 * i, 0);
1551                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1552                                              16 * i, 0);
1553                         }
1554                 }
1555
1556                 /* Free memory heap structures */
1557                 radeon_mem_takedown(&(dev_priv->gart_heap));
1558                 radeon_mem_takedown(&(dev_priv->fb_heap));
1559
1560
1561                 radeon_gem_mm_fini(dev);
1562
1563                 /* deallocate kernel resources */
1564                 radeon_do_cleanup_cp(dev);
1565         }
1566 }
1567
1568 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1569  */
1570 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1571 {
1572         drm_radeon_private_t *dev_priv = dev->dev_private;
1573         DRM_DEBUG("\n");
1574
1575         if (drm_core_check_feature(dev, DRIVER_MODESET))
1576                 return 0;
1577
1578         LOCK_TEST_WITH_RETURN(dev, file_priv);
1579
1580         if (!dev_priv) {
1581                 DRM_DEBUG("called before init done\n");
1582                 return -EINVAL;
1583         }
1584
1585         radeon_do_cp_reset(dev_priv);
1586
1587         /* The CP is no longer running after an engine reset */
1588         dev_priv->cp_running = 0;
1589
1590         return 0;
1591 }
1592
1593 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1594 {
1595         drm_radeon_private_t *dev_priv = dev->dev_private;
1596         DRM_DEBUG("\n");
1597
1598
1599         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1600                 LOCK_TEST_WITH_RETURN(dev, file_priv);
1601
1602         return radeon_do_cp_idle(dev_priv);
1603 }
1604
1605 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1606  */
1607 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1608 {
1609
1610         if (drm_core_check_feature(dev, DRIVER_MODESET))
1611                 return 0;
1612
1613         return radeon_do_resume_cp(dev);
1614 }
1615
1616 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1617 {
1618         DRM_DEBUG("\n");
1619
1620         if (drm_core_check_feature(dev, DRIVER_MODESET))
1621                 return 0;
1622
1623         LOCK_TEST_WITH_RETURN(dev, file_priv);
1624
1625         return radeon_do_engine_reset(dev);
1626 }
1627
1628 /* ================================================================
1629  * Fullscreen mode
1630  */
1631
1632 /* KW: Deprecated to say the least:
1633  */
1634 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1635 {
1636         return 0;
1637 }
1638
1639 /* ================================================================
1640  * Freelist management
1641  */
1642
1643 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1644  *   bufs until freelist code is used.  Note this hides a problem with
1645  *   the scratch register * (used to keep track of last buffer
1646  *   completed) being written to before * the last buffer has actually
1647  *   completed rendering.
1648  *
1649  * KW:  It's also a good way to find free buffers quickly.
1650  *
1651  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1652  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1653  * we essentially have to do this, else old clients will break.
1654  *
1655  * However, it does leave open a potential deadlock where all the
1656  * buffers are held by other clients, which can't release them because
1657  * they can't get the lock.
1658  */
1659
1660 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1661 {
1662         struct drm_device_dma *dma = dev->dma;
1663         drm_radeon_private_t *dev_priv = dev->dev_private;
1664         drm_radeon_buf_priv_t *buf_priv;
1665         struct drm_buf *buf;
1666         int i, t;
1667         int start;
1668
1669         if (++dev_priv->last_buf >= dma->buf_count)
1670                 dev_priv->last_buf = 0;
1671
1672         start = dev_priv->last_buf;
1673
1674         for (t = 0; t < dev_priv->usec_timeout; t++) {
1675                 u32 done_age = GET_SCRATCH(1);
1676                 DRM_DEBUG("done_age = %d\n", done_age);
1677                 for (i = start; i < dma->buf_count; i++) {
1678                         buf = dma->buflist[i];
1679                         buf_priv = buf->dev_private;
1680                         if (buf->file_priv == NULL || (buf->pending &&
1681                                                        buf_priv->age <=
1682                                                        done_age)) {
1683                                 dev_priv->stats.requested_bufs++;
1684                                 buf->pending = 0;
1685                                 return buf;
1686                         }
1687                         start = 0;
1688                 }
1689
1690                 if (t) {
1691                         DRM_UDELAY(1);
1692                         dev_priv->stats.freelist_loops++;
1693                 }
1694         }
1695
1696         DRM_DEBUG("returning NULL!\n");
1697         return NULL;
1698 }
1699
1700 #if 0
1701 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1702 {
1703         struct drm_device_dma *dma = dev->dma;
1704         drm_radeon_private_t *dev_priv = dev->dev_private;
1705         drm_radeon_buf_priv_t *buf_priv;
1706         struct drm_buf *buf;
1707         int i, t;
1708         int start;
1709         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1710
1711         if (++dev_priv->last_buf >= dma->buf_count)
1712                 dev_priv->last_buf = 0;
1713
1714         start = dev_priv->last_buf;
1715         dev_priv->stats.freelist_loops++;
1716
1717         for (t = 0; t < 2; t++) {
1718                 for (i = start; i < dma->buf_count; i++) {
1719                         buf = dma->buflist[i];
1720                         buf_priv = buf->dev_private;
1721                         if (buf->file_priv == 0 || (buf->pending &&
1722                                                     buf_priv->age <=
1723                                                     done_age)) {
1724                                 dev_priv->stats.requested_bufs++;
1725                                 buf->pending = 0;
1726                                 return buf;
1727                         }
1728                 }
1729                 start = 0;
1730         }
1731
1732         return NULL;
1733 }
1734 #endif
1735
1736 void radeon_freelist_reset(struct drm_device * dev)
1737 {
1738         struct drm_device_dma *dma = dev->dma;
1739         drm_radeon_private_t *dev_priv = dev->dev_private;
1740         int i;
1741
1742         dev_priv->last_buf = 0;
1743         for (i = 0; i < dma->buf_count; i++) {
1744                 struct drm_buf *buf = dma->buflist[i];
1745                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1746                 buf_priv->age = 0;
1747         }
1748 }
1749
1750 /* ================================================================
1751  * CP command submission
1752  */
1753
1754 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1755 {
1756         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1757         int i;
1758         u32 last_head = GET_RING_HEAD(dev_priv);
1759
1760         for (i = 0; i < dev_priv->usec_timeout; i++) {
1761                 u32 head = GET_RING_HEAD(dev_priv);
1762
1763                 ring->space = (head - ring->tail) * sizeof(u32);
1764                 if (ring->space <= 0)
1765                         ring->space += ring->size;
1766                 if (ring->space > n)
1767                         return 0;
1768
1769                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1770
1771                 if (head != last_head)
1772                         i = 0;
1773                 last_head = head;
1774
1775                 DRM_UDELAY(1);
1776         }
1777
1778         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1779 #if RADEON_FIFO_DEBUG
1780         radeon_status(dev_priv);
1781         DRM_ERROR("failed!\n");
1782 #endif
1783         return -EBUSY;
1784 }
1785
1786 static int radeon_cp_get_buffers(struct drm_device *dev,
1787                                  struct drm_file *file_priv,
1788                                  struct drm_dma * d)
1789 {
1790         int i;
1791         struct drm_buf *buf;
1792
1793         for (i = d->granted_count; i < d->request_count; i++) {
1794                 buf = radeon_freelist_get(dev);
1795                 if (!buf)
1796                         return -EBUSY;  /* NOTE: broken client */
1797
1798                 buf->file_priv = file_priv;
1799
1800                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1801                                      sizeof(buf->idx)))
1802                         return -EFAULT;
1803                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1804                                      sizeof(buf->total)))
1805                         return -EFAULT;
1806
1807                 d->granted_count++;
1808         }
1809         return 0;
1810 }
1811
1812 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1813 {
1814         struct drm_device_dma *dma = dev->dma;
1815         int ret = 0;
1816         struct drm_dma *d = data;
1817
1818         LOCK_TEST_WITH_RETURN(dev, file_priv);
1819
1820         /* Please don't send us buffers.
1821          */
1822         if (d->send_count != 0) {
1823                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1824                           DRM_CURRENTPID, d->send_count);
1825                 return -EINVAL;
1826         }
1827
1828         /* We'll send you buffers.
1829          */
1830         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1831                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1832                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1833                 return -EINVAL;
1834         }
1835
1836         d->granted_count = 0;
1837
1838         if (d->request_count) {
1839                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1840         }
1841
1842         return ret;
1843 }
1844
1845 static void radeon_get_vram_type(struct drm_device *dev)
1846 {
1847         struct drm_radeon_private *dev_priv = dev->dev_private;
1848         uint32_t tmp;
1849
1850         if (dev_priv->flags & RADEON_IS_IGP || (dev_priv->chip_family >= CHIP_R300))
1851                 dev_priv->is_ddr = true;
1852         else if (RADEON_READ(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1853                 dev_priv->is_ddr = true;
1854         else
1855                 dev_priv->is_ddr = false;
1856
1857         if ((dev_priv->chip_family >= CHIP_R600) &&
1858             (dev_priv->chip_family <= CHIP_RV635)) {
1859                 int chansize;
1860
1861                 tmp = RADEON_READ(R600_RAMCFG);
1862                 if (tmp & R600_CHANSIZE_OVERRIDE)
1863                         chansize = 16;
1864                 else if (tmp & R600_CHANSIZE)
1865                         chansize = 64;
1866                 else
1867                         chansize = 32;
1868
1869                 if (dev_priv->chip_family == CHIP_R600)
1870                         dev_priv->ram_width = 8 * chansize;
1871                 else if (dev_priv->chip_family == CHIP_RV670)
1872                         dev_priv->ram_width = 4 * chansize;
1873                 else if ((dev_priv->chip_family == CHIP_RV610) ||
1874                          (dev_priv->chip_family == CHIP_RV620))
1875                         dev_priv->ram_width = chansize;
1876                 else if ((dev_priv->chip_family == CHIP_RV630) ||
1877                          (dev_priv->chip_family == CHIP_RV635))
1878                         dev_priv->ram_width = 2 * chansize;
1879         } else if (dev_priv->chip_family == CHIP_RV515) {
1880                 tmp = radeon_read_mc_reg(dev_priv, RV515_MC_CNTL);
1881                 tmp &= RV515_MEM_NUM_CHANNELS_MASK;
1882                 switch (tmp) {
1883                 case 0: dev_priv->ram_width = 64; break;
1884                 case 1: dev_priv->ram_width = 128; break;
1885                 default: dev_priv->ram_width = 128; break;
1886                 }
1887         } else if ((dev_priv->chip_family >= CHIP_R520) &&
1888                    (dev_priv->chip_family <= CHIP_RV570)) {
1889                 tmp = radeon_read_mc_reg(dev_priv, R520_MC_CNTL0);
1890                 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
1891                 case 0: dev_priv->ram_width = 32; break;
1892                 case 1: dev_priv->ram_width = 64; break;
1893                 case 2: dev_priv->ram_width = 128; break;
1894                 case 3: dev_priv->ram_width = 256; break;
1895                 default: dev_priv->ram_width = 128; break;
1896                 }
1897         } else if ((dev_priv->chip_family == CHIP_RV100) ||
1898                    (dev_priv->chip_family == CHIP_RS100) ||
1899                    (dev_priv->chip_family == CHIP_RS200)) {
1900                 tmp = RADEON_READ(RADEON_MEM_CNTL);
1901                 if (tmp & RV100_HALF_MODE)
1902                         dev_priv->ram_width = 32;
1903                 else
1904                         dev_priv->ram_width = 64;
1905
1906                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
1907                         dev_priv->ram_width /= 4;
1908                         dev_priv->is_ddr = true;
1909                 }
1910         } else if (dev_priv->chip_family <= CHIP_RV280) {
1911                 tmp = RADEON_READ(RADEON_MEM_CNTL);
1912                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
1913                         dev_priv->ram_width = 128;
1914                 else
1915                         dev_priv->ram_width = 64;
1916         } else {
1917                 /* newer IGPs */
1918                 dev_priv->ram_width = 128;
1919         }
1920         DRM_DEBUG("RAM width %d bits %cDR\n", dev_priv->ram_width, dev_priv->is_ddr ? 'D' : 'S');
1921 }
1922
1923 static void radeon_force_some_clocks(struct drm_device *dev)
1924 {
1925         struct drm_radeon_private *dev_priv = dev->dev_private;
1926         uint32_t tmp;
1927
1928         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1929         tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
1930         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
1931 }
1932
1933 static void radeon_set_dynamic_clock(struct drm_device *dev, int mode)
1934 {
1935         struct drm_radeon_private *dev_priv = dev->dev_private;
1936         uint32_t tmp;
1937
1938         switch(mode) {
1939         case 0:
1940                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
1941                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1942                         tmp |= (RADEON_SCLK_FORCE_CP   | RADEON_SCLK_FORCE_HDP |
1943                                 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
1944                                 RADEON_SCLK_FORCE_E2   | RADEON_SCLK_FORCE_SE  |
1945                                 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
1946                                 RADEON_SCLK_FORCE_RE   | RADEON_SCLK_FORCE_PB  |
1947                                 RADEON_SCLK_FORCE_TAM  | RADEON_SCLK_FORCE_TDM |
1948                                 RADEON_SCLK_FORCE_RB);
1949                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
1950                 } else if (dev_priv->chip_family == CHIP_RV350) {
1951                         /* for RV350/M10, no delays are required. */
1952                         tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
1953                         tmp |= (R300_SCLK_FORCE_TCL |
1954                                 R300_SCLK_FORCE_GA |
1955                                 R300_SCLK_FORCE_CBA);
1956                         RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
1957
1958                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1959                         tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
1960                                  RADEON_SCLK_FORCE_HDP   | RADEON_SCLK_FORCE_DISP1   |
1961                                  RADEON_SCLK_FORCE_TOP   | RADEON_SCLK_FORCE_E2      |
1962                                  R300_SCLK_FORCE_VAP     | RADEON_SCLK_FORCE_IDCT    |
1963                                  RADEON_SCLK_FORCE_VIP   | R300_SCLK_FORCE_SR        |
1964                                  R300_SCLK_FORCE_PX      | R300_SCLK_FORCE_TX        |
1965                                  R300_SCLK_FORCE_US      | RADEON_SCLK_FORCE_TV_SCLK |
1966                                  R300_SCLK_FORCE_SU      | RADEON_SCLK_FORCE_OV0);
1967                         tmp |=  RADEON_DYN_STOP_LAT_MASK;
1968                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
1969
1970                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
1971                         tmp &= ~RADEON_SCLK_MORE_FORCEON;
1972                         tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
1973                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
1974
1975                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
1976                         tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
1977                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
1978                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
1979
1980                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
1981                         tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
1982                                 RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
1983                                 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
1984                                 R300_DVOCLK_ALWAYS_ONb            |
1985                                 RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
1986                                 RADEON_PIXCLK_GV_ALWAYS_ONb       |
1987                                 R300_PIXCLK_DVO_ALWAYS_ONb        |
1988                                 RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
1989                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
1990                                 R300_PIXCLK_TRANS_ALWAYS_ONb      |
1991                                 R300_PIXCLK_TVO_ALWAYS_ONb        |
1992                                 R300_P2G2CLK_ALWAYS_ONb           |
1993                                 R300_P2G2CLK_ALWAYS_ONb);
1994                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
1995                 } else {
1996                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
1997                         tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
1998                         tmp |= RADEON_SCLK_FORCE_SE;
1999
2000                         if ( dev_priv->flags & RADEON_SINGLE_CRTC ) {
2001                                 tmp |= ( RADEON_SCLK_FORCE_RB    |
2002                                          RADEON_SCLK_FORCE_TDM   |
2003                                          RADEON_SCLK_FORCE_TAM   |
2004                                          RADEON_SCLK_FORCE_PB    |
2005                                          RADEON_SCLK_FORCE_RE    |
2006                                          RADEON_SCLK_FORCE_VIP   |
2007                                          RADEON_SCLK_FORCE_IDCT  |
2008                                          RADEON_SCLK_FORCE_TOP   |
2009                                          RADEON_SCLK_FORCE_DISP1 |
2010                                          RADEON_SCLK_FORCE_DISP2 |
2011                                          RADEON_SCLK_FORCE_HDP    );
2012                         } else if ((dev_priv->chip_family == CHIP_R300) ||
2013                                    (dev_priv->chip_family == CHIP_R350)) {
2014                                 tmp |= ( RADEON_SCLK_FORCE_HDP   |
2015                                          RADEON_SCLK_FORCE_DISP1 |
2016                                          RADEON_SCLK_FORCE_DISP2 |
2017                                          RADEON_SCLK_FORCE_TOP   |
2018                                          RADEON_SCLK_FORCE_IDCT  |
2019                                          RADEON_SCLK_FORCE_VIP);
2020                         }
2021
2022                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2023
2024                         udelay(16000);
2025
2026                         if ((dev_priv->chip_family == CHIP_R300) ||
2027                             (dev_priv->chip_family == CHIP_R350)) {
2028                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2029                                 tmp |= ( R300_SCLK_FORCE_TCL |
2030                                          R300_SCLK_FORCE_GA  |
2031                                          R300_SCLK_FORCE_CBA);
2032                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2033                                 udelay(16000);
2034                         }
2035
2036                         if (dev_priv->flags & RADEON_IS_IGP) {
2037                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2038                                 tmp &= ~(RADEON_FORCEON_MCLKA |
2039                                          RADEON_FORCEON_YCLKA);
2040                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, tmp);
2041                                 udelay(16000);
2042                         }
2043
2044                         if ((dev_priv->chip_family == CHIP_RV200) ||
2045                             (dev_priv->chip_family == CHIP_RV250) ||
2046                             (dev_priv->chip_family == CHIP_RV280)) {
2047                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2048                                 tmp |= RADEON_SCLK_MORE_FORCEON;
2049                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2050                                 udelay(16000);
2051                         }
2052
2053                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2054                         tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb         |
2055                                  RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2056                                  RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2057                                  RADEON_PIXCLK_GV_ALWAYS_ONb       |
2058                                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
2059                                  RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2060                                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
2061
2062                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2063                         udelay(16000);
2064
2065                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2066                         tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb  |
2067                                  RADEON_PIXCLK_DAC_ALWAYS_ONb);
2068                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2069                 }
2070                 DRM_DEBUG("Dynamic Clock Scaling Disabled\n");
2071                 break;
2072         case 1:
2073                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
2074                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2075                         if ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) >
2076                             RADEON_CFG_ATI_REV_A13) {
2077                                 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
2078                         }
2079                         tmp &= ~(RADEON_SCLK_FORCE_HDP  | RADEON_SCLK_FORCE_DISP1 |
2080                                  RADEON_SCLK_FORCE_TOP  | RADEON_SCLK_FORCE_SE   |
2081                                  RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE   |
2082                                  RADEON_SCLK_FORCE_PB   | RADEON_SCLK_FORCE_TAM  |
2083                                  RADEON_SCLK_FORCE_TDM);
2084                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2085                 } else if ((dev_priv->chip_family == CHIP_R300) ||
2086                            (dev_priv->chip_family == CHIP_R350) ||
2087                            (dev_priv->chip_family == CHIP_RV350)) {
2088                         if (dev_priv->chip_family == CHIP_RV350) {
2089                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2090                                 tmp &= ~(R300_SCLK_FORCE_TCL |
2091                                          R300_SCLK_FORCE_GA  |
2092                                          R300_SCLK_FORCE_CBA);
2093                                 tmp |=  (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
2094                                          R300_SCLK_GA_MAX_DYN_STOP_LAT  |
2095                                          R300_SCLK_CBA_MAX_DYN_STOP_LAT);
2096                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2097
2098                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2099                                 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
2100                                          RADEON_SCLK_FORCE_HDP   | RADEON_SCLK_FORCE_DISP1   |
2101                                          RADEON_SCLK_FORCE_TOP   | RADEON_SCLK_FORCE_E2      |
2102                                          R300_SCLK_FORCE_VAP     | RADEON_SCLK_FORCE_IDCT    |
2103                                          RADEON_SCLK_FORCE_VIP   | R300_SCLK_FORCE_SR        |
2104                                          R300_SCLK_FORCE_PX      | R300_SCLK_FORCE_TX        |
2105                                          R300_SCLK_FORCE_US      | RADEON_SCLK_FORCE_TV_SCLK |
2106                                          R300_SCLK_FORCE_SU      | RADEON_SCLK_FORCE_OV0);
2107                                 tmp |=  RADEON_DYN_STOP_LAT_MASK;
2108                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2109
2110                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2111                                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
2112                                 tmp |=  RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
2113                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2114
2115                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2116                                 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
2117                                         RADEON_PIXCLK_DAC_ALWAYS_ONb);
2118                                 RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2119
2120                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2121                                 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
2122                                         RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2123                                         RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
2124                                         R300_DVOCLK_ALWAYS_ONb            |
2125                                         RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2126                                         RADEON_PIXCLK_GV_ALWAYS_ONb       |
2127                                         R300_PIXCLK_DVO_ALWAYS_ONb        |
2128                                         RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2129                                         RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
2130                                         R300_PIXCLK_TRANS_ALWAYS_ONb      |
2131                                         R300_PIXCLK_TVO_ALWAYS_ONb        |
2132                                         R300_P2G2CLK_ALWAYS_ONb           |
2133                                         R300_P2G2CLK_ALWAYS_ONb);
2134                                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2135
2136                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_MISC);
2137                                 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
2138                                         RADEON_IO_MCLK_DYN_ENABLE);
2139                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_MISC, tmp);
2140
2141                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2142                                 tmp |= (RADEON_FORCEON_MCLKA |
2143                                         RADEON_FORCEON_MCLKB);
2144
2145                                 tmp &= ~(RADEON_FORCEON_YCLKA  |
2146                                          RADEON_FORCEON_YCLKB  |
2147                                          RADEON_FORCEON_MC);
2148
2149                                 /* Some releases of vbios have set DISABLE_MC_MCLKA
2150                                    and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
2151                                    bits will cause H/W hang when reading video memory with dynamic clocking
2152                                    enabled. */
2153                                 if ((tmp & R300_DISABLE_MC_MCLKA) &&
2154                                     (tmp & R300_DISABLE_MC_MCLKB)) {
2155                                         /* If both bits are set, then check the active channels */
2156                                         tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2157                                         if (dev_priv->ram_width == 64) {
2158                                                 if (RADEON_READ(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
2159                                                         tmp &= ~R300_DISABLE_MC_MCLKB;
2160                                                 else
2161                                                         tmp &= ~R300_DISABLE_MC_MCLKA;
2162                                         } else {
2163                                                 tmp &= ~(R300_DISABLE_MC_MCLKA |
2164                                                          R300_DISABLE_MC_MCLKB);
2165                                         }
2166                                 }
2167
2168                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, tmp);
2169                         } else {
2170                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2171                                 tmp &= ~(R300_SCLK_FORCE_VAP);
2172                                 tmp |= RADEON_SCLK_FORCE_CP;
2173                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2174                                 udelay(15000);
2175
2176                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2177                                 tmp &= ~(R300_SCLK_FORCE_TCL |
2178                                          R300_SCLK_FORCE_GA  |
2179                                          R300_SCLK_FORCE_CBA);
2180                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2181                         }
2182                 } else {
2183                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
2184                         tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK     |
2185                                  RADEON_DISP_DYN_STOP_LAT_MASK   |
2186                                  RADEON_DYN_STOP_MODE_MASK);
2187
2188                         tmp |= (RADEON_ENGIN_DYNCLK_MODE |
2189                                 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
2190                         RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL, tmp);
2191                         udelay(15000);
2192
2193                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PIN_CNTL);
2194                         tmp |= RADEON_SCLK_DYN_START_CNTL;
2195                         RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PIN_CNTL, tmp);
2196                         udelay(15000);
2197
2198                         /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
2199                            to lockup randomly, leave them as set by BIOS.
2200                         */
2201                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2202                         /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
2203                         tmp &= ~RADEON_SCLK_FORCEON_MASK;
2204
2205                         /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
2206                         if (((dev_priv->chip_family == CHIP_RV250) &&
2207                              ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2208                               RADEON_CFG_ATI_REV_A13)) ||
2209                             ((dev_priv->chip_family == CHIP_RV100) &&
2210                              ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
2211                               RADEON_CFG_ATI_REV_A13))){
2212                                 tmp |= RADEON_SCLK_FORCE_CP;
2213                                 tmp |= RADEON_SCLK_FORCE_VIP;
2214                         }
2215
2216                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2217
2218                         if ((dev_priv->chip_family == CHIP_RV200) ||
2219                             (dev_priv->chip_family == CHIP_RV250) ||
2220                             (dev_priv->chip_family == CHIP_RV280)) {
2221                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2222                                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
2223
2224                                 /* RV200::A11 A12 RV250::A11 A12 */
2225                                 if (((dev_priv->chip_family == CHIP_RV200) ||
2226                                      (dev_priv->chip_family == CHIP_RV250)) &&
2227                                     ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2228                                      RADEON_CFG_ATI_REV_A13)) {
2229                                         tmp |= RADEON_SCLK_MORE_FORCEON;
2230                                 }
2231                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2232                                 udelay(15000);
2233                         }
2234
2235                         /* RV200::A11 A12, RV250::A11 A12 */
2236                         if (((dev_priv->chip_family == CHIP_RV200) ||
2237                              (dev_priv->chip_family == CHIP_RV250)) &&
2238                             ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2239                              RADEON_CFG_ATI_REV_A13)) {
2240                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_PLL_PWRMGT_CNTL);
2241                                 tmp |= RADEON_TCL_BYPASS_DISABLE;
2242                                 RADEON_WRITE_PLL(dev_priv, RADEON_PLL_PWRMGT_CNTL, tmp);
2243                         }
2244                         udelay(15000);
2245
2246                         /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/
2247                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2248                         tmp |=  (RADEON_PIX2CLK_ALWAYS_ONb         |
2249                                  RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2250                                  RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2251                                  RADEON_PIXCLK_GV_ALWAYS_ONb       |
2252                                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
2253                                  RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2254                                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
2255
2256                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2257                         udelay(15000);
2258
2259                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2260                         tmp |= (RADEON_PIXCLK_ALWAYS_ONb  |
2261                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
2262
2263                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2264                         udelay(15000);
2265                 }
2266                 DRM_DEBUG("Dynamic Clock Scaling Enabled\n");
2267                 break;
2268         default:
2269                 break;
2270         }
2271
2272 }
2273
2274 int radeon_modeset_cp_init(struct drm_device *dev)
2275 {
2276         drm_radeon_private_t *dev_priv = dev->dev_private;
2277
2278         /* allocate a ring and ring rptr bits from GART space */
2279         /* these are allocated in GEM files */
2280
2281         dev_priv->usec_timeout = RADEON_DEFAULT_CP_TIMEOUT;
2282         dev_priv->ring.size = RADEON_DEFAULT_RING_SIZE;
2283         dev_priv->cp_mode = RADEON_CSQ_PRIBM_INDBM;
2284
2285         dev_priv->ring.start = (u32 *)(void *)(unsigned long)dev_priv->mm.ring_map.virtual;
2286         dev_priv->ring.end = (u32 *)(void *)(unsigned long)dev_priv->mm.ring_map.virtual +
2287                 dev_priv->ring.size / sizeof(u32);
2288         dev_priv->ring.size_l2qw = drm_order(dev_priv->ring.size / 8);
2289         dev_priv->ring.rptr_update = 4096;
2290         dev_priv->ring.rptr_update_l2qw = drm_order(4096 / 8);
2291         dev_priv->ring.fetch_size = 32;
2292         dev_priv->ring.fetch_size_l2ow = drm_order(32 / 16);
2293         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2294         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2295
2296         dev_priv->new_memmap = 1;
2297
2298         radeon_cp_load_microcode(dev_priv);
2299
2300         DRM_DEBUG("ring offset is %x %x\n", dev_priv->mm.ring->offset, dev_priv->mm.ring_read_ptr->offset);
2301
2302         radeon_cp_init_ring_buffer(dev, dev_priv);
2303
2304         radeon_do_engine_reset(dev);
2305         radeon_test_writeback(dev_priv);
2306
2307         radeon_do_cp_start(dev_priv);
2308         return 0;
2309 }
2310
2311 static bool radeon_get_bios(struct drm_device *dev)
2312 {
2313         drm_radeon_private_t *dev_priv = dev->dev_private;
2314         u8 __iomem *bios;
2315         size_t size;
2316         uint16_t tmp;
2317
2318         bios = pci_map_rom(dev->pdev, &size);
2319         if (!bios)
2320                 return -1;
2321
2322         dev_priv->bios = kmalloc(size, GFP_KERNEL);
2323         if (!dev_priv->bios) {
2324                 pci_unmap_rom(dev->pdev, bios);
2325                 return -1;
2326         }
2327
2328         memcpy(dev_priv->bios, bios, size);
2329
2330         pci_unmap_rom(dev->pdev, bios);
2331
2332         if (dev_priv->bios[0] != 0x55 || dev_priv->bios[1] != 0xaa)
2333                 goto free_bios;
2334
2335         dev_priv->bios_header_start = radeon_bios16(dev_priv, 0x48);
2336
2337         if (!dev_priv->bios_header_start)
2338                 goto free_bios;
2339
2340         tmp = dev_priv->bios_header_start + 4;
2341
2342         if (!memcmp(dev_priv->bios + tmp, "ATOM", 4) ||
2343             !memcmp(dev_priv->bios + tmp, "MOTA", 4))
2344                 dev_priv->is_atom_bios = true;
2345         else
2346                 dev_priv->is_atom_bios = false;
2347
2348         DRM_DEBUG("%sBIOS detected\n", dev_priv->is_atom_bios ? "ATOM" : "COM");
2349         return true;
2350 free_bios:
2351         kfree(dev_priv->bios);
2352         dev_priv->bios = NULL;
2353         return false;
2354 }
2355
2356 int radeon_modeset_preinit(struct drm_device *dev)
2357 {
2358         drm_radeon_private_t *dev_priv = dev->dev_private;
2359         static struct card_info card;
2360         int ret;
2361
2362         card.dev = dev;
2363         card.reg_read = cail_reg_read;
2364         card.reg_write = cail_reg_write;
2365         card.mc_read = cail_mc_read;
2366         card.mc_write = cail_mc_write;
2367
2368         ret = radeon_get_bios(dev);
2369         if (!ret)
2370                 return -1;
2371
2372         if (dev_priv->is_atom_bios) {
2373                 dev_priv->mode_info.atom_context = atom_parse(&card, dev_priv->bios);
2374                 radeon_get_clock_info(dev);
2375         }
2376         return 0;
2377 }
2378
2379
2380 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2381 {
2382         drm_radeon_private_t *dev_priv;
2383         int ret = 0;
2384
2385         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2386         if (dev_priv == NULL)
2387                 return -ENOMEM;
2388
2389         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2390         dev->dev_private = (void *)dev_priv;
2391         dev_priv->flags = flags;
2392
2393         switch (flags & RADEON_FAMILY_MASK) {
2394         case CHIP_R100:
2395         case CHIP_RV200:
2396         case CHIP_R200:
2397         case CHIP_R300:
2398         case CHIP_R350:
2399         case CHIP_R420:
2400         case CHIP_RV410:
2401         case CHIP_RV515:
2402         case CHIP_R520:
2403         case CHIP_RV570:
2404         case CHIP_R580:
2405                 dev_priv->flags |= RADEON_HAS_HIERZ;
2406                 break;
2407         default:
2408                 /* all other chips have no hierarchical z buffer */
2409                 break;
2410         }
2411
2412         dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
2413         if (drm_device_is_agp(dev))
2414                 dev_priv->flags |= RADEON_IS_AGP;
2415         else if (drm_device_is_pcie(dev))
2416                 dev_priv->flags |= RADEON_IS_PCIE;
2417         else
2418                 dev_priv->flags |= RADEON_IS_PCI;
2419
2420
2421
2422         DRM_DEBUG("%s card detected\n",
2423                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2424
2425         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2426                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2427                          _DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio);
2428         if (ret != 0)
2429                 return ret;
2430
2431         if (drm_core_check_feature(dev, DRIVER_MODESET))
2432                 radeon_modeset_preinit(dev);
2433
2434
2435         radeon_get_vram_type(dev);
2436
2437         dev_priv->pll_errata = 0;
2438
2439         if (dev_priv->chip_family == CHIP_R300 &&
2440             (RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11)
2441                 dev_priv->pll_errata |= CHIP_ERRATA_R300_CG;
2442
2443         if (dev_priv->chip_family == CHIP_RV200 ||
2444             dev_priv->chip_family == CHIP_RS200)
2445                 dev_priv->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2446
2447
2448         if (dev_priv->chip_family == CHIP_RV100 ||
2449             dev_priv->chip_family == CHIP_RS100 ||
2450             dev_priv->chip_family == CHIP_RS200)
2451                 dev_priv->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2452
2453
2454         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2455                 if ((dev_priv->flags & RADEON_IS_MOBILITY) && !radeon_is_avivo(dev_priv)) {
2456                         radeon_set_dynamic_clock(dev, radeon_dynclks);
2457                 } else if (radeon_is_avivo(dev_priv)) {
2458                         if (radeon_dynclks) {
2459                                 radeon_atom_static_pwrmgt_setup(dev, 1);
2460                                 radeon_atom_dyn_clk_setup(dev, 1);
2461                         }
2462                 }
2463                 radeon_force_some_clocks(dev);
2464         }
2465
2466         /* init memory manager - start with all of VRAM and a 32MB GART aperture for now */
2467         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2468
2469         drm_bo_driver_init(dev);
2470
2471         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2472
2473                 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
2474                 dev_priv->fb_size =
2475                         ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
2476                         - dev_priv->fb_location;
2477                 radeon_gem_mm_init(dev);
2478                 radeon_modeset_init(dev);
2479
2480                 radeon_modeset_cp_init(dev);
2481                 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
2482
2483                 drm_irq_install(dev);
2484         }
2485
2486
2487         return ret;
2488 }
2489
2490
2491 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2492 {
2493         struct drm_radeon_master_private *master_priv;
2494         unsigned long sareapage;
2495         int ret;
2496
2497         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
2498         if (!master_priv)
2499                 return -ENOMEM;
2500
2501         /* prebuild the SAREA */
2502         sareapage = max(SAREA_MAX, PAGE_SIZE);
2503         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
2504                          &master_priv->sarea);
2505         if (ret) {
2506                 DRM_ERROR("SAREA setup failed\n");
2507                 return ret;
2508         }
2509         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2510         master_priv->sarea_priv->pfCurrentPage = 0;
2511
2512         master->driver_priv = master_priv;
2513         return 0;
2514 }
2515
2516 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2517 {
2518         struct drm_radeon_master_private *master_priv = master->driver_priv;
2519         struct drm_radeon_private *dev_priv = dev->dev_private;
2520
2521         if (!master_priv)
2522                 return;
2523
2524         if (master_priv->sarea_priv &&
2525             master_priv->sarea_priv->pfCurrentPage != 0)
2526                 radeon_cp_dispatch_flip(dev, master);
2527
2528         master_priv->sarea_priv = NULL;
2529         if (master_priv->sarea)
2530                 drm_rmmap(dev, master_priv->sarea);
2531
2532         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
2533
2534         master->driver_priv = NULL;
2535 }
2536 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2537  * have to find them.
2538  */
2539 int radeon_driver_firstopen(struct drm_device *dev)
2540 {
2541         int ret;
2542         drm_local_map_t *map;
2543         drm_radeon_private_t *dev_priv = dev->dev_private;
2544
2545         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2546
2547         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2548                 radeon_gem_mm_init(dev);
2549
2550         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2551                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2552                          _DRM_WRITE_COMBINING, &map);
2553         if (ret != 0)
2554                 return ret;
2555
2556         return 0;
2557 }
2558
2559 int radeon_driver_unload(struct drm_device *dev)
2560 {
2561         drm_radeon_private_t *dev_priv = dev->dev_private;
2562
2563         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2564                 drm_irq_uninstall(dev);
2565                 radeon_modeset_cleanup(dev);
2566                 radeon_gem_mm_fini(dev);
2567         }
2568
2569         drm_bo_driver_finish(dev);
2570         drm_rmmap(dev, dev_priv->mmio);
2571
2572         DRM_DEBUG("\n");
2573         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2574
2575         dev->dev_private = NULL;
2576         return 0;
2577 }
2578
2579 void radeon_gart_flush(struct drm_device *dev)
2580 {
2581         drm_radeon_private_t *dev_priv = dev->dev_private;
2582
2583         if (dev_priv->flags & RADEON_IS_IGPGART) {
2584                 IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
2585                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
2586                 IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
2587                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
2588         } else if (dev_priv->flags & RADEON_IS_PCIE) {
2589                 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
2590                 tmp |= RADEON_PCIE_TX_GART_INVALIDATE_TLB;
2591                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
2592                 tmp &= ~RADEON_PCIE_TX_GART_INVALIDATE_TLB;
2593                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
2594         } else {
2595
2596
2597         }
2598
2599 }