shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "drm_sarea.h"
  35 #include "radeon_drm.h"
  36 #include "radeon_drv.h"
  37 #include "r300_reg.h"
  38
  39 #include "radeon_microcode.h"
  40 #define RADEON_FIFO_DEBUG       0
  41
  42 static int radeon_do_cleanup_cp(struct drm_device * dev);
  43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  44
  45 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  46 {
  47         u32 ret;
  48         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  49         ret = RADEON_READ(R520_MC_IND_DATA);
  50         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  51         return ret;
  52 }
  53
  54 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  55 {
  56         u32 ret;
  57         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  58         ret = RADEON_READ(RS480_NB_MC_DATA);
  59         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  60         return ret;
  61 }
  62
  63 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  64 {
  65         u32 ret;
  66         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  67         ret = RADEON_READ(RS690_MC_DATA);
  68         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  69         return ret;
  70 }
  71
  72 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  73 {
  74         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  75             return RS690_READ_MCIND(dev_priv, addr);
  76         else
  77             return RS480_READ_MCIND(dev_priv, addr);
  78 }
  79
  80 u32 radeon_read_mc_reg(drm_radeon_private_t *dev_priv, int addr)
  81 {
  82         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  83                 return IGP_READ_MCIND(dev_priv, addr);
  84         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515)
  85                 return R500_READ_MCIND(dev_priv, addr);
  86         return 0;
  87 }
  88
  89 void radeon_write_mc_reg(drm_radeon_private_t *dev_priv, u32 addr, u32 val)
  90 {
  91         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
  92                 IGP_WRITE_MCIND(addr, val);
  93         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515)
  94                 R500_WRITE_MCIND(addr, val);
  95 }
  96
  97 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  98 {
  99
 100         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 101                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 102         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 103                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 104         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 105                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 106         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 107                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 108         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 109                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 110         else
 111                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 112 }
 113
 114 void radeon_read_agp_location(drm_radeon_private_t *dev_priv, u32 *agp_lo, u32 *agp_hi)
 115 {
 116         if (dev_priv->chip_family == CHIP_RV770) {
 117                 *agp_lo = RADEON_READ(R600_MC_VM_AGP_BOT);
 118                 *agp_hi = RADEON_READ(R600_MC_VM_AGP_TOP);
 119         } else if (dev_priv->chip_family == CHIP_R600) {
 120                 *agp_lo = RADEON_READ(R600_MC_VM_AGP_BOT);
 121                 *agp_hi = RADEON_READ(R600_MC_VM_AGP_TOP);
 122         } else if (dev_priv->chip_family == CHIP_RV515) {
 123                 *agp_lo = radeon_read_mc_reg(dev_priv, RV515_MC_AGP_LOCATION);
 124                 *agp_hi = 0;
 125         } else if (dev_priv->chip_family == CHIP_RS600) {
 126                 *agp_lo = 0;
 127                 *agp_hi = 0;
 128         } else if (dev_priv->chip_family == CHIP_RS690 ||
 129                    dev_priv->chip_family == CHIP_RS740) {
 130                 *agp_lo = radeon_read_mc_reg(dev_priv, RS690_MC_AGP_LOCATION);
 131                 *agp_hi = 0;
 132         } else if (dev_priv->chip_family >= CHIP_R520) {
 133                 *agp_lo = radeon_read_mc_reg(dev_priv, R520_MC_AGP_LOCATION);
 134                 *agp_hi = 0;
 135         } else {
 136                 *agp_lo = RADEON_READ(RADEON_MC_AGP_LOCATION);
 137                 *agp_hi = 0;
 138         }
 139 }
 140
 141 void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 142 {
 143         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 144                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 145         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 146                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 147         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 148                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 149         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 150                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 151         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 152                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 153         else
 154                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 155 }
 156
 157 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc, u32 agp_loc_hi)
 158 {
 159         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 160                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 161         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 162                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 163         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 164                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc);
 165                 RADEON_WRITE(R600_MC_VM_AGP_TOP, agp_loc_hi);
 166         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 167                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 168         else
 169                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 170 }
 171
 172 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 173 {
 174         u32 agp_base_hi = upper_32_bits(agp_base);
 175         u32 agp_base_lo = agp_base & 0xffffffff;
 176
 177         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 178                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 179                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 180         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 181                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 182                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 183         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 184                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 185                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 186         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 187                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 188                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 189                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 190         } else {
 191                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 192                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 193                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 194         }
 195 }
 196
 197 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 198 {
 199         u32 tmp;
 200         /* Turn on bus mastering */
 201         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 202             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 203                 /* rs600/rs690/rs740 */
 204                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 205                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 206         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 207                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 208                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 209                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 210                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 211                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 212                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 213         } /* PCIE cards appears to not need this */
 214 }
 215
 216 void radeon_pll_errata_after_index(struct drm_radeon_private *dev_priv)
 217 {
 218         if (!(dev_priv->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS))
 219                 return;
 220
 221         (void)RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 222         (void)RADEON_READ(RADEON_CRTC_GEN_CNTL);
 223 }
 224
 225 void radeon_pll_errata_after_data(struct drm_radeon_private *dev_priv)
 226 {
 227         /* This workarounds is necessary on RV100, RS100 and RS200 chips
 228          * or the chip could hang on a subsequent access
 229          */
 230         if (dev_priv->pll_errata & CHIP_ERRATA_PLL_DELAY)
 231                 udelay(5000);
 232
 233         /* This function is required to workaround a hardware bug in some (all?)
 234          * revisions of the R300.  This workaround should be called after every
 235          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
 236          * may not be correct.
 237          */
 238         if (dev_priv->pll_errata & CHIP_ERRATA_R300_CG) {
 239                 uint32_t save, tmp;
 240
 241                 save = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 242                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
 243                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, tmp);
 244                 tmp = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 245                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, save);
 246         }
 247 }
 248
 249 u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
 250 {
 251         uint32_t data;
 252
 253         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
 254         radeon_pll_errata_after_index(dev_priv);
 255         data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 256         radeon_pll_errata_after_data(dev_priv);
 257         return data;
 258 }
 259
 260 void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data)
 261 {
 262         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f) | RADEON_PLL_WR_EN));
 263         radeon_pll_errata_after_index(dev_priv);
 264         RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, data);
 265         radeon_pll_errata_after_data(dev_priv);
 266 }
 267
 268 u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 269 {
 270         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 271         return RADEON_READ(RADEON_PCIE_DATA);
 272 }
 273
 274 /* ATOM accessor methods */
 275 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
 276 {
 277         uint32_t ret = radeon_read_mc_reg(info->dev->dev_private, reg);
 278
 279         //      DRM_DEBUG("(%x) = %x\n", reg, ret);
 280         return ret;
 281 }
 282
 283 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
 284 {
 285   //    DRM_DEBUG("(%x,  %x)\n", reg, val);
 286         radeon_write_mc_reg(info->dev->dev_private, reg, val);
 287 }
 288
 289 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
 290 {
 291         drm_radeon_private_t *dev_priv = info->dev->dev_private;
 292
 293         //      DRM_DEBUG("(%x,  %x)\n", reg*4, val);
 294         RADEON_WRITE(reg*4, val);
 295 }
 296
 297 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
 298 {
 299         uint32_t ret;
 300         drm_radeon_private_t *dev_priv = info->dev->dev_private;
 301
 302         ret = RADEON_READ(reg*4);
 303         //      DRM_DEBUG("(%x) = %x\n", reg*4, ret);
 304         return ret;
 305 }
 306
 307 #if RADEON_FIFO_DEBUG
 308 static void radeon_status(drm_radeon_private_t * dev_priv)
 309 {
 310         printk("%s:\n", __FUNCTION__);
 311         printk("RBBM_STATUS = 0x%08x\n",
 312                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 313         printk("CP_RB_RTPR = 0x%08x\n",
 314                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 315         printk("CP_RB_WTPR = 0x%08x\n",
 316                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 317         printk("AIC_CNTL = 0x%08x\n",
 318                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 319         printk("AIC_STAT = 0x%08x\n",
 320                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 321         printk("AIC_PT_BASE = 0x%08x\n",
 322                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 323         printk("TLB_ADDR = 0x%08x\n",
 324                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 325         printk("TLB_DATA = 0x%08x\n",
 326                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 327 }
 328 #endif
 329
 330 /* ================================================================
 331  * Engine, FIFO control
 332  */
 333
 334 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 335 {
 336         u32 tmp;
 337         int i;
 338
 339         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 340
 341         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 342                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 343                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 344                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 345
 346                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 347                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 348                               & RADEON_RB3D_DC_BUSY)) {
 349                                 return 0;
 350                         }
 351                         DRM_UDELAY(1);
 352                 }
 353         } else {
 354                 /* don't flush or purge cache here or lockup */
 355                 return 0;
 356         }
 357
 358 #if RADEON_FIFO_DEBUG
 359         DRM_ERROR("failed!\n");
 360         radeon_status(dev_priv);
 361 #endif
 362         return -EBUSY;
 363 }
 364
 365 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 366 {
 367         int i;
 368
 369         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 370
 371         for (i = 0; i < dev_priv->usec_timeout; i++) {
 372                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 373                              & RADEON_RBBM_FIFOCNT_MASK);
 374                 if (slots >= entries)
 375                         return 0;
 376                 DRM_UDELAY(1);
 377         }
 378         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
 379                  RADEON_READ(RADEON_RBBM_STATUS),
 380                  RADEON_READ(R300_VAP_CNTL_STATUS));
 381
 382 #if RADEON_FIFO_DEBUG
 383         DRM_ERROR("failed!\n");
 384         radeon_status(dev_priv);
 385 #endif
 386         return -EBUSY;
 387 }
 388
 389 int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 390 {
 391         int i, ret;
 392
 393         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 394
 395         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 396         if (ret)
 397                 return ret;
 398
 399         for (i = 0; i < dev_priv->usec_timeout; i++) {
 400                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 401                       & RADEON_RBBM_ACTIVE)) {
 402                         radeon_do_pixcache_flush(dev_priv);
 403                         return 0;
 404                 }
 405                 DRM_UDELAY(1);
 406         }
 407         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 408                  RADEON_READ(RADEON_RBBM_STATUS),
 409                  RADEON_READ(R300_VAP_CNTL_STATUS));
 410
 411 #if RADEON_FIFO_DEBUG
 412         DRM_ERROR("failed!\n");
 413         radeon_status(dev_priv);
 414 #endif
 415         return -EBUSY;
 416 }
 417
 418 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 419 {
 420         uint32_t gb_tile_config, gb_pipe_sel = 0;
 421
 422         /* RS4xx/RS6xx/R4xx/R5xx */
 423         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 424                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 425                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 426         } else {
 427                 /* R3xx */
 428                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 429                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 430                         dev_priv->num_gb_pipes = 2;
 431                 } else {
 432                         /* R3Vxx */
 433                         dev_priv->num_gb_pipes = 1;
 434                 }
 435         }
 436         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 437
 438         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 439
 440         switch(dev_priv->num_gb_pipes) {
 441         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 442         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 443         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 444         default:
 445         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 446         }
 447
 448         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 449                 RADEON_WRITE_PLL(dev_priv, R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 450                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 451         }
 452         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 453         radeon_do_wait_for_idle(dev_priv);
 454         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 455         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 456                                                R300_DC_AUTOFLUSH_ENABLE |
 457                                                R300_DC_DC_DISABLE_IGNORE_PE));
 458
 459
 460 }
 461
 462 /* ================================================================
 463  * CP control, initialization
 464  */
 465
 466 /* Load the microcode for the CP */
 467 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 468 {
 469         int i;
 470         DRM_DEBUG("\n");
 471
 472         radeon_do_wait_for_idle(dev_priv);
 473
 474         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 475
 476         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 477             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 478             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 479             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 480             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 481                 DRM_INFO("Loading R100 Microcode\n");
 482                 for (i = 0; i < 256; i++) {
 483                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 484                                      R100_cp_microcode[i][1]);
 485                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 486                                      R100_cp_microcode[i][0]);
 487                 }
 488         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 489                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 490                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 491                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 492                 DRM_INFO("Loading R200 Microcode\n");
 493                 for (i = 0; i < 256; i++) {
 494                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 495                                      R200_cp_microcode[i][1]);
 496                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 497                                      R200_cp_microcode[i][0]);
 498                 }
 499         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 500                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 501                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 502                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 503                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 504                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 505                 DRM_INFO("Loading R300 Microcode\n");
 506                 for (i = 0; i < 256; i++) {
 507                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 508                                      R300_cp_microcode[i][1]);
 509                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 510                                      R300_cp_microcode[i][0]);
 511                 }
 512         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 513                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 514                 DRM_INFO("Loading R400 Microcode\n");
 515                 for (i = 0; i < 256; i++) {
 516                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 517                                      R420_cp_microcode[i][1]);
 518                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 519                                      R420_cp_microcode[i][0]);
 520                 }
 521         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
 522                 DRM_INFO("Loading RS690 Microcode\n");
 523                 for (i = 0; i < 256; i++) {
 524                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 525                                      RS690_cp_microcode[i][1]);
 526                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 527                                      RS690_cp_microcode[i][0]);
 528                 }
 529         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 530                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 531                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 532                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 533                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 534                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 535                 DRM_INFO("Loading R500 Microcode\n");
 536                 for (i = 0; i < 256; i++) {
 537                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 538                                      R520_cp_microcode[i][1]);
 539                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 540                                      R520_cp_microcode[i][0]);
 541                 }
 542         }
 543 }
 544
 545 /* Flush any pending commands to the CP.  This should only be used just
 546  * prior to a wait for idle, as it informs the engine that the command
 547  * stream is ending.
 548  */
 549 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 550 {
 551         DRM_DEBUG("\n");
 552 #if 0
 553         u32 tmp;
 554         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 555         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 556 #endif
 557 }
 558
 559 /* Wait for the CP to go idle.
 560  */
 561 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 562 {
 563         RING_LOCALS;
 564         DRM_DEBUG("\n");
 565
 566         BEGIN_RING(6);
 567
 568         RADEON_PURGE_CACHE();
 569         RADEON_PURGE_ZCACHE();
 570         RADEON_WAIT_UNTIL_IDLE();
 571
 572         ADVANCE_RING();
 573         COMMIT_RING();
 574
 575         return radeon_do_wait_for_idle(dev_priv);
 576 }
 577
 578 /* Start the Command Processor.
 579  */
 580 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 581 {
 582         RING_LOCALS;
 583         DRM_DEBUG("\n");
 584
 585         radeon_do_wait_for_idle(dev_priv);
 586
 587         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 588
 589         dev_priv->cp_running = 1;
 590
 591         BEGIN_RING(8);
 592         /* isync can only be written through cp on r5xx write it here */
 593         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 594         if (dev_priv->chip_family > CHIP_RV280)
 595                 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 596                          RADEON_ISYNC_ANY3D_IDLE2D |
 597                          RADEON_ISYNC_WAIT_IDLEGUI |
 598                  dev_priv->mm_enabled ? 0 : RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 599         else
 600         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 601                  RADEON_ISYNC_ANY3D_IDLE2D |
 602                  RADEON_ISYNC_WAIT_IDLEGUI);
 603         RADEON_PURGE_CACHE();
 604         RADEON_PURGE_ZCACHE();
 605         RADEON_WAIT_UNTIL_IDLE();
 606         ADVANCE_RING();
 607         COMMIT_RING();
 608
 609         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 610 }
 611
 612 /* Reset the Command Processor.  This will not flush any pending
 613  * commands, so you must wait for the CP command stream to complete
 614  * before calling this routine.
 615  */
 616 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 617 {
 618         u32 cur_read_ptr;
 619         DRM_DEBUG("\n");
 620
 621         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 622         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 623         SET_RING_HEAD(dev_priv, cur_read_ptr);
 624         dev_priv->ring.tail = cur_read_ptr;
 625 }
 626
 627 /* Stop the Command Processor.  This will not flush any pending
 628  * commands, so you must flush the command stream and wait for the CP
 629  * to go idle before calling this routine.
 630  */
 631 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 632 {
 633         DRM_DEBUG("\n");
 634
 635         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 636
 637         dev_priv->cp_running = 0;
 638 }
 639
 640 /* Reset the engine.  This will stop the CP if it is running.
 641  */
 642 static int radeon_do_engine_reset(struct drm_device * dev)
 643 {
 644         drm_radeon_private_t *dev_priv = dev->dev_private;
 645         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 646         DRM_DEBUG("\n");
 647
 648         radeon_do_pixcache_flush(dev_priv);
 649
 650         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 651                 /* may need something similar for newer chips */
 652                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 653                 mclk_cntl = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
 654
 655                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, (mclk_cntl |
 656                                                               RADEON_FORCEON_MCLKA |
 657                                                               RADEON_FORCEON_MCLKB |
 658                                                               RADEON_FORCEON_YCLKA |
 659                                                               RADEON_FORCEON_YCLKB |
 660                                                               RADEON_FORCEON_MC |
 661                                                               RADEON_FORCEON_AIC));
 662         }
 663
 664         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 665
 666         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 667                                               RADEON_SOFT_RESET_CP |
 668                                               RADEON_SOFT_RESET_HI |
 669                                               RADEON_SOFT_RESET_SE |
 670                                               RADEON_SOFT_RESET_RE |
 671                                               RADEON_SOFT_RESET_PP |
 672                                               RADEON_SOFT_RESET_E2 |
 673                                               RADEON_SOFT_RESET_RB));
 674         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 675         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 676                                               ~(RADEON_SOFT_RESET_CP |
 677                                                 RADEON_SOFT_RESET_HI |
 678                                                 RADEON_SOFT_RESET_SE |
 679                                                 RADEON_SOFT_RESET_RE |
 680                                                 RADEON_SOFT_RESET_PP |
 681                                                 RADEON_SOFT_RESET_E2 |
 682                                                 RADEON_SOFT_RESET_RB)));
 683         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 684
 685         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 686                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, mclk_cntl);
 687                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 688                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 689         }
 690
 691         /* setup the raster pipes */
 692         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 693             radeon_init_pipes(dev_priv);
 694
 695         /* Reset the CP ring */
 696         radeon_do_cp_reset(dev_priv);
 697
 698         /* The CP is no longer running after an engine reset */
 699         dev_priv->cp_running = 0;
 700
 701         /* Reset any pending vertex, indirect buffers */
 702         if (dev->dma)
 703                 radeon_freelist_reset(dev);
 704
 705         return 0;
 706 }
 707
 708 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 709                                        drm_radeon_private_t * dev_priv)
 710 {
 711         u32 ring_start, cur_read_ptr;
 712
 713         /* Initialize the memory controller. With new memory map, the fb location
 714          * is not changed, it should have been properly initialized already. Part
 715          * of the problem is that the code below is bogus, assuming the GART is
 716          * always appended to the fb which is not necessarily the case
 717          */
 718         if (!dev_priv->new_memmap)
 719                 radeon_write_fb_location(dev_priv,
 720                                          ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 721                                          | (dev_priv->fb_location >> 16));
 722
 723         if (dev_priv->mm.ring.bo) {
 724                 ring_start = dev_priv->mm.ring.bo->offset +
 725                         dev_priv->gart_vm_start;
 726         } else
 727 #if __OS_HAS_AGP
 728         if (dev_priv->flags & RADEON_IS_AGP) {
 729                 radeon_write_agp_base(dev_priv, dev->agp->base);
 730
 731                 radeon_write_agp_location(dev_priv,
 732                              (((dev_priv->gart_vm_start - 1 +
 733                                 dev_priv->gart_size) & 0xffff0000) |
 734                               (dev_priv->gart_vm_start >> 16)), 0);
 735
 736                 ring_start = (dev_priv->cp_ring->offset
 737                               - dev->agp->base
 738                               + dev_priv->gart_vm_start);
 739         } else
 740 #endif
 741                 ring_start = (dev_priv->cp_ring->offset
 742                               - (unsigned long)dev->sg->virtual
 743                               + dev_priv->gart_vm_start);
 744
 745         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 746
 747         /* Set the write pointer delay */
 748         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 749
 750         /* Initialize the ring buffer's read and write pointers */
 751         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 752         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 753         SET_RING_HEAD(dev_priv, cur_read_ptr);
 754         dev_priv->ring.tail = cur_read_ptr;
 755
 756
 757         if (dev_priv->mm.ring_read.bo) {
 758                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 759                              dev_priv->mm.ring_read.bo->offset +
 760                              dev_priv->gart_vm_start);
 761         } else
 762 #if __OS_HAS_AGP
 763         if (dev_priv->flags & RADEON_IS_AGP) {
 764                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 765                              dev_priv->ring_rptr->offset
 766                              - dev->agp->base + dev_priv->gart_vm_start);
 767         } else
 768 #endif
 769         {
 770                 struct drm_sg_mem *entry = dev->sg;
 771                 unsigned long tmp_ofs, page_ofs;
 772
 773                 tmp_ofs = dev_priv->ring_rptr->offset -
 774                                 (unsigned long)dev->sg->virtual;
 775                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 776
 777                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 778                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 779                           (unsigned long)entry->busaddr[page_ofs],
 780                           entry->handle + tmp_ofs);
 781         }
 782
 783         /* Set ring buffer size */
 784 #ifdef __BIG_ENDIAN
 785         RADEON_WRITE(RADEON_CP_RB_CNTL,
 786                      RADEON_BUF_SWAP_32BIT |
 787                      (dev_priv->ring.fetch_size_l2ow << 18) |
 788                      (dev_priv->ring.rptr_update_l2qw << 8) |
 789                      dev_priv->ring.size_l2qw);
 790 #else
 791         RADEON_WRITE(RADEON_CP_RB_CNTL,
 792                      (dev_priv->ring.fetch_size_l2ow << 18) |
 793                      (dev_priv->ring.rptr_update_l2qw << 8) |
 794                      dev_priv->ring.size_l2qw);
 795 #endif
 796
 797         /* Initialize the scratch register pointer.  This will cause
 798          * the scratch register values to be written out to memory
 799          * whenever they are updated.
 800          *
 801          * We simply put this behind the ring read pointer, this works
 802          * with PCI GART as well as (whatever kind of) AGP GART
 803          */
 804         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 805                      + RADEON_SCRATCH_REG_OFFSET);
 806
 807         if (dev_priv->mm.ring_read.bo)
 808                 dev_priv->scratch = ((__volatile__ u32 *)
 809                                      dev_priv->mm.ring_read.kmap.virtual +
 810                                      (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 811         else
 812                 dev_priv->scratch = ((__volatile__ u32 *)
 813                                      dev_priv->ring_rptr->handle +
 814                                      (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 815
 816         if (dev_priv->chip_family >= CHIP_R300)
 817                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7f);
 818         else
 819                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x1f);
 820
 821         radeon_enable_bm(dev_priv);
 822
 823         dev_priv->scratch[0] = 0;
 824         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 825
 826         dev_priv->scratch[1] = 0;
 827         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 828
 829         dev_priv->scratch[2] = 0;
 830         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 831
 832         dev_priv->scratch[3] = 0;
 833         RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
 834
 835         dev_priv->scratch[4] = 0;
 836         RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
 837
 838         dev_priv->scratch[6] = 0;
 839         RADEON_WRITE(RADEON_SCRATCH_REG6, 0);
 840
 841         radeon_do_wait_for_idle(dev_priv);
 842
 843         /* Sync everything up */
 844         if (dev_priv->chip_family > CHIP_RV280) {
 845         RADEON_WRITE(RADEON_ISYNC_CNTL,
 846                      (RADEON_ISYNC_ANY2D_IDLE3D |
 847                       RADEON_ISYNC_ANY3D_IDLE2D |
 848                       RADEON_ISYNC_WAIT_IDLEGUI |
 849                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 850         } else {
 851         RADEON_WRITE(RADEON_ISYNC_CNTL,
 852                      (RADEON_ISYNC_ANY2D_IDLE3D |
 853                       RADEON_ISYNC_ANY3D_IDLE2D |
 854                       RADEON_ISYNC_WAIT_IDLEGUI));
 855         }
 856 }
 857
 858 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 859 {
 860         u32 tmp, scratch1_store;
 861         void *ring_read_ptr;
 862
 863         if (dev_priv->mm.ring_read.bo)
 864                 ring_read_ptr = dev_priv->mm.ring_read.kmap.virtual;
 865         else
 866                 ring_read_ptr = dev_priv->ring_rptr->handle;
 867
 868         scratch1_store = RADEON_READ(RADEON_SCRATCH_REG1);
 869         /* Writeback doesn't seem to work everywhere, test it here and possibly
 870          * enable it if it appears to work
 871          */
 872         writel(0, ring_read_ptr + RADEON_SCRATCHOFF(1));
 873         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 874
 875         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 876                 if (readl(ring_read_ptr + RADEON_SCRATCHOFF(1)) ==
 877                     0xdeadbeef)
 878                         break;
 879                 DRM_UDELAY(1);
 880         }
 881
 882         if (tmp < dev_priv->usec_timeout) {
 883                 dev_priv->writeback_works = 1;
 884                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 885         } else {
 886                 dev_priv->writeback_works = 0;
 887                 DRM_INFO("writeback test failed\n");
 888         }
 889         if (radeon_no_wb == 1) {
 890                 dev_priv->writeback_works = 0;
 891                 DRM_INFO("writeback forced off\n");
 892         }
 893
 894         /* write back previous value */
 895         RADEON_WRITE(RADEON_SCRATCH_REG1, scratch1_store);
 896
 897         if (!dev_priv->writeback_works) {
 898                 /* Disable writeback to avoid unnecessary bus master transfers */
 899                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
 900                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 901         }
 902 }
 903
 904 /* Enable or disable IGP GART on the chip */
 905 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 906 {
 907         u32 temp;
 908
 909         if (on) {
 910                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 911                          dev_priv->gart_vm_start,
 912                          (long)dev_priv->gart_info.bus_addr,
 913                          dev_priv->gart_size);
 914
 915                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 916
 917                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
 918                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 919                                                              RS690_BLOCK_GFX_D3_EN));
 920                 else
 921                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 922
 923                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 924                                                                RS480_VA_SIZE_32MB));
 925
 926                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 927                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 928                                                         RS480_TLB_ENABLE |
 929                                                         RS480_GTW_LAC_EN |
 930                                                         RS480_1LEVEL_GART));
 931
 932                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 933                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 934                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 935
 936                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 937                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 938                                                       RS480_REQ_TYPE_SNOOP_DIS));
 939
 940                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 941
 942                 dev_priv->gart_size = 32*1024*1024;
 943                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 944                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 945
 946                 radeon_write_agp_location(dev_priv, temp, 0);
 947
 948                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 949                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 950                                                                RS480_VA_SIZE_32MB));
 951
 952                 do {
 953                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 954                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 955                                 break;
 956                         DRM_UDELAY(1);
 957                 } while(1);
 958
 959                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 960                                 RS480_GART_CACHE_INVALIDATE);
 961
 962                 do {
 963                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 964                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 965                                 break;
 966                         DRM_UDELAY(1);
 967                 } while(1);
 968
 969                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 970         } else {
 971                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 972         }
 973 }
 974
 975 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 976 {
 977         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 978         if (on) {
 979
 980                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 981                           dev_priv->gart_vm_start,
 982                           (long)dev_priv->gart_info.bus_addr,
 983                           dev_priv->gart_size);
 984                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 985                                   dev_priv->gart_vm_start);
 986                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 987                                   dev_priv->gart_info.bus_addr);
 988                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 989                                   dev_priv->gart_vm_start);
 990                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 991                                   dev_priv->gart_vm_start +
 992                                   dev_priv->gart_size - 1);
 993
 994                 radeon_write_agp_location(dev_priv, 0xffffffc0, 0); /* ?? */
 995
 996                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 997                                   RADEON_PCIE_TX_GART_EN);
 998         } else {
 999                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1000                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1001         }
1002 }
1003
1004 /* Enable or disable PCI GART on the chip */
1005 void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1006 {
1007         u32 tmp;
1008
1009         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1010             (dev_priv->flags & RADEON_IS_IGPGART)) {
1011                 radeon_set_igpgart(dev_priv, on);
1012                 return;
1013         }
1014
1015         if (dev_priv->flags & RADEON_IS_PCIE) {
1016                 radeon_set_pciegart(dev_priv, on);
1017                 return;
1018         }
1019
1020         tmp = RADEON_READ(RADEON_AIC_CNTL);
1021
1022         if (on) {
1023                 RADEON_WRITE(RADEON_AIC_CNTL,
1024                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1025
1026                 /* set PCI GART page-table base address
1027                  */
1028                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1029
1030                 /* set address range for PCI address translate
1031                  */
1032                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1033                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1034                              + dev_priv->gart_size - 1);
1035
1036                 /* Turn off AGP aperture -- is this required for PCI GART?
1037                  */
1038                 radeon_write_agp_location(dev_priv, 0xffffffc0, 0);
1039                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1040         } else {
1041                 RADEON_WRITE(RADEON_AIC_CNTL,
1042                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1043         }
1044 }
1045
1046 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1047                              struct drm_file *file_priv)
1048 {
1049         drm_radeon_private_t *dev_priv = dev->dev_private;
1050         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1051
1052         DRM_DEBUG("\n");
1053
1054         /* if we require new memory map but we don't have it fail */
1055         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1056                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1057                 radeon_do_cleanup_cp(dev);
1058                 return -EINVAL;
1059         }
1060
1061         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
1062         {
1063                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1064                 dev_priv->flags &= ~RADEON_IS_AGP;
1065         }
1066         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1067                  && !init->is_pci)
1068         {
1069                 DRM_DEBUG("Restoring AGP flag\n");
1070                 dev_priv->flags |= RADEON_IS_AGP;
1071         }
1072
1073         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1074                 DRM_ERROR("PCI GART memory not allocated!\n");
1075                 radeon_do_cleanup_cp(dev);
1076                 return -EINVAL;
1077         }
1078
1079         dev_priv->usec_timeout = init->usec_timeout;
1080         if (dev_priv->usec_timeout < 1 ||
1081             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1082                 DRM_DEBUG("TIMEOUT problem!\n");
1083                 radeon_do_cleanup_cp(dev);
1084                 return -EINVAL;
1085         }
1086
1087         /* Enable vblank on CRTC1 for older X servers
1088          */
1089         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1090
1091         dev_priv->do_boxes = 0;
1092         dev_priv->cp_mode = init->cp_mode;
1093
1094         /* We don't support anything other than bus-mastering ring mode,
1095          * but the ring can be in either AGP or PCI space for the ring
1096          * read pointer.
1097          */
1098         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1099             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1100                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1101                 radeon_do_cleanup_cp(dev);
1102                 return -EINVAL;
1103         }
1104
1105         switch (init->fb_bpp) {
1106         case 16:
1107                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1108                 break;
1109         case 32:
1110         default:
1111                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1112                 break;
1113         }
1114         dev_priv->front_offset = init->front_offset;
1115         dev_priv->front_pitch = init->front_pitch;
1116         dev_priv->back_offset = init->back_offset;
1117         dev_priv->back_pitch = init->back_pitch;
1118
1119         switch (init->depth_bpp) {
1120         case 16:
1121                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1122                 break;
1123         case 32:
1124         default:
1125                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1126                 break;
1127         }
1128         dev_priv->depth_offset = init->depth_offset;
1129         dev_priv->depth_pitch = init->depth_pitch;
1130
1131         /* Hardware state for depth clears.  Remove this if/when we no
1132          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1133          * all values to prevent unwanted 3D state from slipping through
1134          * and screwing with the clear operation.
1135          */
1136         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1137                                            (dev_priv->color_fmt << 10) |
1138                                            (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
1139
1140         dev_priv->depth_clear.rb3d_zstencilcntl =
1141             (dev_priv->depth_fmt |
1142              RADEON_Z_TEST_ALWAYS |
1143              RADEON_STENCIL_TEST_ALWAYS |
1144              RADEON_STENCIL_S_FAIL_REPLACE |
1145              RADEON_STENCIL_ZPASS_REPLACE |
1146              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1147
1148         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1149                                          RADEON_BFACE_SOLID |
1150                                          RADEON_FFACE_SOLID |
1151                                          RADEON_FLAT_SHADE_VTX_LAST |
1152                                          RADEON_DIFFUSE_SHADE_FLAT |
1153                                          RADEON_ALPHA_SHADE_FLAT |
1154                                          RADEON_SPECULAR_SHADE_FLAT |
1155                                          RADEON_FOG_SHADE_FLAT |
1156                                          RADEON_VTX_PIX_CENTER_OGL |
1157                                          RADEON_ROUND_MODE_TRUNC |
1158                                          RADEON_ROUND_PREC_8TH_PIX);
1159
1160
1161         dev_priv->ring_offset = init->ring_offset;
1162         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1163         dev_priv->buffers_offset = init->buffers_offset;
1164         dev_priv->gart_textures_offset = init->gart_textures_offset;
1165
1166         master_priv->sarea = drm_getsarea(dev);
1167         if (!master_priv->sarea) {
1168                 DRM_ERROR("could not find sarea!\n");
1169                 radeon_do_cleanup_cp(dev);
1170                 return -EINVAL;
1171         }
1172
1173         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1174         if (!dev_priv->cp_ring) {
1175                 DRM_ERROR("could not find cp ring region!\n");
1176                 radeon_do_cleanup_cp(dev);
1177                 return -EINVAL;
1178         }
1179         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1180         if (!dev_priv->ring_rptr) {
1181                 DRM_ERROR("could not find ring read pointer!\n");
1182                 radeon_do_cleanup_cp(dev);
1183                 return -EINVAL;
1184         }
1185         dev->agp_buffer_token = init->buffers_offset;
1186         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1187         if (!dev->agp_buffer_map) {
1188                 DRM_ERROR("could not find dma buffer region!\n");
1189                 radeon_do_cleanup_cp(dev);
1190                 return -EINVAL;
1191         }
1192
1193         if (init->gart_textures_offset) {
1194                 dev_priv->gart_textures =
1195                     drm_core_findmap(dev, init->gart_textures_offset);
1196                 if (!dev_priv->gart_textures) {
1197                         DRM_ERROR("could not find GART texture region!\n");
1198                         radeon_do_cleanup_cp(dev);
1199                         return -EINVAL;
1200                 }
1201         }
1202
1203 #if __OS_HAS_AGP
1204         if (dev_priv->flags & RADEON_IS_AGP) {
1205                 drm_core_ioremap(dev_priv->cp_ring, dev);
1206                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1207                 drm_core_ioremap(dev->agp_buffer_map, dev);
1208                 if (!dev_priv->cp_ring->handle ||
1209                     !dev_priv->ring_rptr->handle ||
1210                     !dev->agp_buffer_map->handle) {
1211                         DRM_ERROR("could not find ioremap agp regions!\n");
1212                         radeon_do_cleanup_cp(dev);
1213                         return -EINVAL;
1214                 }
1215         } else
1216 #endif
1217         {
1218                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1219                 dev_priv->ring_rptr->handle =
1220                     (void *)dev_priv->ring_rptr->offset;
1221                 dev->agp_buffer_map->handle =
1222                     (void *)dev->agp_buffer_map->offset;
1223
1224                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1225                           dev_priv->cp_ring->handle);
1226                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1227                           dev_priv->ring_rptr->handle);
1228                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1229                           dev->agp_buffer_map->handle);
1230         }
1231
1232         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1233         dev_priv->fb_size =
1234                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1235                 - dev_priv->fb_location;
1236
1237         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1238                                         ((dev_priv->front_offset
1239                                           + dev_priv->fb_location) >> 10));
1240
1241         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1242                                        ((dev_priv->back_offset
1243                                          + dev_priv->fb_location) >> 10));
1244
1245         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1246                                         ((dev_priv->depth_offset
1247                                           + dev_priv->fb_location) >> 10));
1248
1249         dev_priv->gart_size = init->gart_size;
1250
1251         /* New let's set the memory map ... */
1252         if (dev_priv->new_memmap) {
1253                 u32 base = 0;
1254
1255                 DRM_INFO("Setting GART location based on new memory map\n");
1256
1257                 /* If using AGP, try to locate the AGP aperture at the same
1258                  * location in the card and on the bus, though we have to
1259                  * align it down.
1260                  */
1261 #if __OS_HAS_AGP
1262                 if (dev_priv->flags & RADEON_IS_AGP) {
1263                         base = dev->agp->base;
1264                         /* Check if valid */
1265                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1266                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1267                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1268                                          dev->agp->base);
1269                                 base = 0;
1270                         }
1271                 }
1272 #endif
1273                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1274                 if (base == 0) {
1275                         base = dev_priv->fb_location + dev_priv->fb_size;
1276                         if (base < dev_priv->fb_location ||
1277                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1278                                 base = dev_priv->fb_location
1279                                         - dev_priv->gart_size;
1280                 }
1281                 dev_priv->gart_vm_start = base & 0xffc00000u;
1282                 if (dev_priv->gart_vm_start != base)
1283                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1284                                  base, dev_priv->gart_vm_start);
1285         } else {
1286                 DRM_INFO("Setting GART location based on old memory map\n");
1287                 dev_priv->gart_vm_start = dev_priv->fb_location +
1288                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1289         }
1290
1291 #if __OS_HAS_AGP
1292         if (dev_priv->flags & RADEON_IS_AGP)
1293                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1294                                                  - dev->agp->base
1295                                                  + dev_priv->gart_vm_start);
1296         else
1297 #endif
1298                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1299                                         - (unsigned long)dev->sg->virtual
1300                                         + dev_priv->gart_vm_start);
1301
1302         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1303         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1304         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1305                   dev_priv->gart_buffers_offset);
1306
1307         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1308         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1309                               + init->ring_size / sizeof(u32));
1310         dev_priv->ring.size = init->ring_size;
1311         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1312
1313         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1314         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1315
1316         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1317         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1318
1319         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1320
1321         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1322
1323 #if __OS_HAS_AGP
1324         if (dev_priv->flags & RADEON_IS_AGP) {
1325                 /* Turn off PCI GART */
1326                 radeon_set_pcigart(dev_priv, 0);
1327         } else
1328 #endif
1329         {
1330                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1331                 /* if we have an offset set from userspace */
1332                 if (dev_priv->pcigart_offset_set) {
1333                         /* if it came from userspace - remap it */
1334                         if (dev_priv->pcigart_offset_set == 1) {
1335                                 dev_priv->gart_info.bus_addr =
1336                                         dev_priv->pcigart_offset + dev_priv->fb_location;
1337                                 dev_priv->gart_info.mapping.offset =
1338                                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1339                                 dev_priv->gart_info.mapping.size =
1340                                         dev_priv->gart_info.table_size;
1341
1342                                 /* this is done by the mm now */
1343                                 drm_core_ioremap(&dev_priv->gart_info.mapping, dev);
1344                                 dev_priv->gart_info.addr =
1345                                         dev_priv->gart_info.mapping.handle;
1346
1347                                 memset(dev_priv->gart_info.addr, 0, dev_priv->gart_info.table_size);
1348                                 if (dev_priv->flags & RADEON_IS_PCIE)
1349                                         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1350                                 else
1351                                         dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1352                                 dev_priv->gart_info.gart_table_location =
1353                                         DRM_ATI_GART_FB;
1354
1355                                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1356                                           dev_priv->gart_info.addr,
1357                                           dev_priv->pcigart_offset);
1358                         }
1359                 } else {
1360
1361                         if (dev_priv->flags & RADEON_IS_PCIE) {
1362                                 DRM_ERROR
1363                                     ("Cannot use PCI Express without GART in FB memory\n");
1364                                 radeon_do_cleanup_cp(dev);
1365                                 return -EINVAL;
1366                         }
1367                         if (dev_priv->flags & RADEON_IS_IGPGART)
1368                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1369                         else
1370                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1371                         dev_priv->gart_info.gart_table_location =
1372                             DRM_ATI_GART_MAIN;
1373                         dev_priv->gart_info.addr = NULL;
1374                         dev_priv->gart_info.bus_addr = 0;
1375
1376                 }
1377
1378                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1379                         DRM_ERROR("failed to init PCI GART!\n");
1380                         radeon_do_cleanup_cp(dev);
1381                         return -ENOMEM;
1382                 }
1383
1384                 /* Turn on PCI GART */
1385                 radeon_set_pcigart(dev_priv, 1);
1386         }
1387
1388         /* Start with assuming that writeback doesn't work */
1389         dev_priv->writeback_works = 0;
1390
1391         radeon_cp_load_microcode(dev_priv);
1392         radeon_cp_init_ring_buffer(dev, dev_priv);
1393
1394         dev_priv->last_buf = 0;
1395
1396         radeon_do_engine_reset(dev);
1397         radeon_test_writeback(dev_priv);
1398
1399         return 0;
1400 }
1401
1402 static int radeon_do_cleanup_cp(struct drm_device * dev)
1403 {
1404         drm_radeon_private_t *dev_priv = dev->dev_private;
1405         DRM_DEBUG("\n");
1406
1407         /* Make sure interrupts are disabled here because the uninstall ioctl
1408          * may not have been called from userspace and after dev_private
1409          * is freed, it's too late.
1410          */
1411         if (dev->irq_enabled)
1412                 drm_irq_uninstall(dev);
1413
1414 #if __OS_HAS_AGP
1415         if (dev_priv->flags & RADEON_IS_AGP) {
1416                 if (dev_priv->cp_ring != NULL) {
1417                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1418                         dev_priv->cp_ring = NULL;
1419                 }
1420                 if (dev_priv->ring_rptr != NULL) {
1421                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1422                         dev_priv->ring_rptr = NULL;
1423                 }
1424                 if (dev->agp_buffer_map != NULL) {
1425                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1426                         dev->agp_buffer_map = NULL;
1427                 }
1428         } else
1429 #endif
1430         {
1431
1432                 if (dev_priv->gart_info.bus_addr) {
1433                         /* Turn off PCI GART */
1434                         radeon_set_pcigart(dev_priv, 0);
1435                         drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1436                 }
1437
1438                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1439                 {
1440                         if (dev_priv->pcigart_offset_set == 1) {
1441                                 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1442                                 dev_priv->gart_info.addr = NULL;
1443                                 dev_priv->pcigart_offset_set = 0;
1444                         }
1445                 }
1446         }
1447         /* only clear to the start of flags */
1448         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1449
1450         return 0;
1451 }
1452
1453 /* This code will reinit the Radeon CP hardware after a resume from disc.
1454  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1455  * here we make sure that all Radeon hardware initialisation is re-done without
1456  * affecting running applications.
1457  *
1458  * Charl P. Botha <http://cpbotha.net>
1459  */
1460 static int radeon_do_resume_cp(struct drm_device * dev)
1461 {
1462         drm_radeon_private_t *dev_priv = dev->dev_private;
1463
1464         if (!dev_priv) {
1465                 DRM_ERROR("Called with no initialization\n");
1466                 return -EINVAL;
1467         }
1468
1469         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1470
1471 #if __OS_HAS_AGP
1472         if (dev_priv->flags & RADEON_IS_AGP) {
1473                 /* Turn off PCI GART */
1474                 radeon_set_pcigart(dev_priv, 0);
1475         } else
1476 #endif
1477         {
1478                 /* Turn on PCI GART */
1479                 radeon_set_pcigart(dev_priv, 1);
1480         }
1481
1482         radeon_cp_load_microcode(dev_priv);
1483         radeon_cp_init_ring_buffer(dev, dev_priv);
1484
1485         radeon_do_engine_reset(dev);
1486         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1487
1488         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1489
1490         return 0;
1491 }
1492
1493 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1494 {
1495         drm_radeon_init_t *init = data;
1496
1497         /* on a modesetting driver ignore this stuff */
1498         if (drm_core_check_feature(dev, DRIVER_MODESET))
1499                 return 0;
1500
1501         LOCK_TEST_WITH_RETURN(dev, file_priv);
1502
1503         if (init->func == RADEON_INIT_R300_CP)
1504                 r300_init_reg_flags(dev);
1505
1506         switch (init->func) {
1507         case RADEON_INIT_CP:
1508         case RADEON_INIT_R200_CP:
1509         case RADEON_INIT_R300_CP:
1510                 return radeon_do_init_cp(dev, init, file_priv);
1511         case RADEON_CLEANUP_CP:
1512                 return radeon_do_cleanup_cp(dev);
1513         }
1514
1515         return -EINVAL;
1516 }
1517
1518 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1519 {
1520         drm_radeon_private_t *dev_priv = dev->dev_private;
1521         DRM_DEBUG("\n");
1522
1523         if (drm_core_check_feature(dev, DRIVER_MODESET))
1524                 return 0;
1525
1526         LOCK_TEST_WITH_RETURN(dev, file_priv);
1527
1528         if (dev_priv->cp_running) {
1529                 DRM_DEBUG("while CP running\n");
1530                 return 0;
1531         }
1532         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1533                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1534                           dev_priv->cp_mode);
1535                 return 0;
1536         }
1537
1538         radeon_do_cp_start(dev_priv);
1539
1540         return 0;
1541 }
1542
1543 /* Stop the CP.  The engine must have been idled before calling this
1544  * routine.
1545  */
1546 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1547 {
1548         drm_radeon_private_t *dev_priv = dev->dev_private;
1549         drm_radeon_cp_stop_t *stop = data;
1550         int ret;
1551         DRM_DEBUG("\n");
1552
1553         if (drm_core_check_feature(dev, DRIVER_MODESET))
1554                 return 0;
1555
1556         LOCK_TEST_WITH_RETURN(dev, file_priv);
1557
1558         if (!dev_priv->cp_running)
1559                 return 0;
1560
1561         /* Flush any pending CP commands.  This ensures any outstanding
1562          * commands are exectuted by the engine before we turn it off.
1563          */
1564         if (stop->flush) {
1565                 radeon_do_cp_flush(dev_priv);
1566         }
1567
1568         /* If we fail to make the engine go idle, we return an error
1569          * code so that the DRM ioctl wrapper can try again.
1570          */
1571         if (stop->idle) {
1572                 ret = radeon_do_cp_idle(dev_priv);
1573                 if (ret)
1574                         return ret;
1575         }
1576
1577         /* Finally, we can turn off the CP.  If the engine isn't idle,
1578          * we will get some dropped triangles as they won't be fully
1579          * rendered before the CP is shut down.
1580          */
1581         radeon_do_cp_stop(dev_priv);
1582
1583         /* Reset the engine */
1584         radeon_do_engine_reset(dev);
1585
1586         return 0;
1587 }
1588
1589 void radeon_do_release(struct drm_device * dev)
1590 {
1591         drm_radeon_private_t *dev_priv = dev->dev_private;
1592         int i, ret;
1593
1594         if (drm_core_check_feature(dev, DRIVER_MODESET))
1595                 return;
1596
1597         if (dev_priv) {
1598                 if (dev_priv->cp_running) {
1599                         /* Stop the cp */
1600                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1601                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1602 #ifdef __linux__
1603                                 schedule();
1604 #else
1605 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1606                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1607                                        1);
1608 #else
1609                                 tsleep(&ret, PZERO, "rdnrel", 1);
1610 #endif
1611 #endif
1612                         }
1613                         radeon_do_cp_stop(dev_priv);
1614                         radeon_do_engine_reset(dev);
1615                 }
1616
1617                 /* Disable *all* interrupts */
1618                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1619                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1620
1621                 if (dev_priv->mmio) {   /* remove all surfaces */
1622                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1623                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1624                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1625                                              16 * i, 0);
1626                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1627                                              16 * i, 0);
1628                         }
1629                 }
1630
1631                 /* Free memory heap structures */
1632                 radeon_mem_takedown(&(dev_priv->gart_heap));
1633                 radeon_mem_takedown(&(dev_priv->fb_heap));
1634
1635                 if (dev_priv->user_mm_enable) {
1636                         radeon_gem_mm_fini(dev);
1637                         dev_priv->user_mm_enable = false;
1638                 }
1639
1640                 /* deallocate kernel resources */
1641                 radeon_do_cleanup_cp(dev);
1642         }
1643 }
1644
1645 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1646  */
1647 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1648 {
1649         drm_radeon_private_t *dev_priv = dev->dev_private;
1650         DRM_DEBUG("\n");
1651
1652         if (drm_core_check_feature(dev, DRIVER_MODESET))
1653                 return 0;
1654
1655         LOCK_TEST_WITH_RETURN(dev, file_priv);
1656
1657         if (!dev_priv) {
1658                 DRM_DEBUG("called before init done\n");
1659                 return -EINVAL;
1660         }
1661
1662         radeon_do_cp_reset(dev_priv);
1663
1664         /* The CP is no longer running after an engine reset */
1665         dev_priv->cp_running = 0;
1666
1667         return 0;
1668 }
1669
1670 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1671 {
1672         drm_radeon_private_t *dev_priv = dev->dev_private;
1673         DRM_DEBUG("\n");
1674
1675
1676         if (!drm_core_check_feature(dev, DRIVER_MODESET))
1677                 LOCK_TEST_WITH_RETURN(dev, file_priv);
1678
1679         return radeon_do_cp_idle(dev_priv);
1680 }
1681
1682 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1683  */
1684 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1685 {
1686
1687         if (drm_core_check_feature(dev, DRIVER_MODESET))
1688                 return 0;
1689
1690         return radeon_do_resume_cp(dev);
1691 }
1692
1693 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1694 {
1695         DRM_DEBUG("\n");
1696
1697         if (drm_core_check_feature(dev, DRIVER_MODESET))
1698                 return 0;
1699
1700         LOCK_TEST_WITH_RETURN(dev, file_priv);
1701
1702         return radeon_do_engine_reset(dev);
1703 }
1704
1705 /* ================================================================
1706  * Fullscreen mode
1707  */
1708
1709 /* KW: Deprecated to say the least:
1710  */
1711 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1712 {
1713         return 0;
1714 }
1715
1716 /* ================================================================
1717  * Freelist management
1718  */
1719
1720 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1721  *   bufs until freelist code is used.  Note this hides a problem with
1722  *   the scratch register * (used to keep track of last buffer
1723  *   completed) being written to before * the last buffer has actually
1724  *   completed rendering.
1725  *
1726  * KW:  It's also a good way to find free buffers quickly.
1727  *
1728  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1729  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1730  * we essentially have to do this, else old clients will break.
1731  *
1732  * However, it does leave open a potential deadlock where all the
1733  * buffers are held by other clients, which can't release them because
1734  * they can't get the lock.
1735  */
1736
1737 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1738 {
1739         struct drm_device_dma *dma = dev->dma;
1740         drm_radeon_private_t *dev_priv = dev->dev_private;
1741         drm_radeon_buf_priv_t *buf_priv;
1742         struct drm_buf *buf;
1743         int i, t;
1744         int start;
1745
1746         if (++dev_priv->last_buf >= dma->buf_count)
1747                 dev_priv->last_buf = 0;
1748
1749         start = dev_priv->last_buf;
1750
1751         for (t = 0; t < dev_priv->usec_timeout; t++) {
1752                 u32 done_age = GET_SCRATCH(1);
1753                 DRM_DEBUG("done_age = %d\n", done_age);
1754                 for (i = start; i < dma->buf_count; i++) {
1755                         buf = dma->buflist[i];
1756                         buf_priv = buf->dev_private;
1757                         if (buf->file_priv == NULL || (buf->pending &&
1758                                                        buf_priv->age <=
1759                                                        done_age)) {
1760                                 dev_priv->stats.requested_bufs++;
1761                                 buf->pending = 0;
1762                                 return buf;
1763                         }
1764                         start = 0;
1765                 }
1766
1767                 if (t) {
1768                         DRM_UDELAY(1);
1769                         dev_priv->stats.freelist_loops++;
1770                 }
1771         }
1772
1773         DRM_DEBUG("returning NULL!\n");
1774         return NULL;
1775 }
1776
1777 #if 0
1778 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1779 {
1780         struct drm_device_dma *dma = dev->dma;
1781         drm_radeon_private_t *dev_priv = dev->dev_private;
1782         drm_radeon_buf_priv_t *buf_priv;
1783         struct drm_buf *buf;
1784         int i, t;
1785         int start;
1786         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1787
1788         if (++dev_priv->last_buf >= dma->buf_count)
1789                 dev_priv->last_buf = 0;
1790
1791         start = dev_priv->last_buf;
1792         dev_priv->stats.freelist_loops++;
1793
1794         for (t = 0; t < 2; t++) {
1795                 for (i = start; i < dma->buf_count; i++) {
1796                         buf = dma->buflist[i];
1797                         buf_priv = buf->dev_private;
1798                         if (buf->file_priv == 0 || (buf->pending &&
1799                                                     buf_priv->age <=
1800                                                     done_age)) {
1801                                 dev_priv->stats.requested_bufs++;
1802                                 buf->pending = 0;
1803                                 return buf;
1804                         }
1805                 }
1806                 start = 0;
1807         }
1808
1809         return NULL;
1810 }
1811 #endif
1812
1813 void radeon_freelist_reset(struct drm_device * dev)
1814 {
1815         struct drm_device_dma *dma = dev->dma;
1816         drm_radeon_private_t *dev_priv = dev->dev_private;
1817         int i;
1818
1819         dev_priv->last_buf = 0;
1820         for (i = 0; i < dma->buf_count; i++) {
1821                 struct drm_buf *buf = dma->buflist[i];
1822                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1823                 buf_priv->age = 0;
1824         }
1825 }
1826
1827 /* ================================================================
1828  * CP command submission
1829  */
1830
1831 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1832 {
1833         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1834         int i;
1835         u32 last_head = GET_RING_HEAD(dev_priv);
1836
1837         for (i = 0; i < dev_priv->usec_timeout; i++) {
1838                 u32 head = GET_RING_HEAD(dev_priv);
1839
1840                 ring->space = (head - ring->tail) * sizeof(u32);
1841                 if (ring->space <= 0)
1842                         ring->space += ring->size;
1843                 if (ring->space > n)
1844                         return 0;
1845
1846                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1847
1848                 if (head != last_head)
1849                         i = 0;
1850                 last_head = head;
1851
1852                 DRM_UDELAY(1);
1853         }
1854
1855         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1856 #if RADEON_FIFO_DEBUG
1857         radeon_status(dev_priv);
1858         DRM_ERROR("failed!\n");
1859 #endif
1860         return -EBUSY;
1861 }
1862
1863 static int radeon_cp_get_buffers(struct drm_device *dev,
1864                                  struct drm_file *file_priv,
1865                                  struct drm_dma * d)
1866 {
1867         int i;
1868         struct drm_buf *buf;
1869
1870         for (i = d->granted_count; i < d->request_count; i++) {
1871                 buf = radeon_freelist_get(dev);
1872                 if (!buf)
1873                         return -EBUSY;  /* NOTE: broken client */
1874
1875                 buf->file_priv = file_priv;
1876
1877                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1878                                      sizeof(buf->idx)))
1879                         return -EFAULT;
1880                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1881                                      sizeof(buf->total)))
1882                         return -EFAULT;
1883
1884                 d->granted_count++;
1885         }
1886         return 0;
1887 }
1888
1889 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1890 {
1891         struct drm_device_dma *dma = dev->dma;
1892         int ret = 0;
1893         struct drm_dma *d = data;
1894
1895         LOCK_TEST_WITH_RETURN(dev, file_priv);
1896
1897         /* Please don't send us buffers.
1898          */
1899         if (d->send_count != 0) {
1900                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1901                           DRM_CURRENTPID, d->send_count);
1902                 return -EINVAL;
1903         }
1904
1905         /* We'll send you buffers.
1906          */
1907         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1908                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1909                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1910                 return -EINVAL;
1911         }
1912
1913         d->granted_count = 0;
1914
1915         if (d->request_count) {
1916                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1917         }
1918
1919         return ret;
1920 }
1921
1922 static void radeon_get_vram_type(struct drm_device *dev)
1923 {
1924         struct drm_radeon_private *dev_priv = dev->dev_private;
1925         uint32_t tmp;
1926
1927         if (dev_priv->flags & RADEON_IS_IGP || (dev_priv->chip_family >= CHIP_R300))
1928                 dev_priv->is_ddr = true;
1929         else if (RADEON_READ(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1930                 dev_priv->is_ddr = true;
1931         else
1932                 dev_priv->is_ddr = false;
1933
1934         if ((dev_priv->chip_family >= CHIP_R600) &&
1935             (dev_priv->chip_family <= CHIP_RV635)) {
1936                 int chansize;
1937
1938                 tmp = RADEON_READ(R600_RAMCFG);
1939                 if (tmp & R600_CHANSIZE_OVERRIDE)
1940                         chansize = 16;
1941                 else if (tmp & R600_CHANSIZE)
1942                         chansize = 64;
1943                 else
1944                         chansize = 32;
1945
1946                 if (dev_priv->chip_family == CHIP_R600)
1947                         dev_priv->ram_width = 8 * chansize;
1948                 else if (dev_priv->chip_family == CHIP_RV670)
1949                         dev_priv->ram_width = 4 * chansize;
1950                 else if ((dev_priv->chip_family == CHIP_RV610) ||
1951                          (dev_priv->chip_family == CHIP_RV620))
1952                         dev_priv->ram_width = chansize;
1953                 else if ((dev_priv->chip_family == CHIP_RV630) ||
1954                          (dev_priv->chip_family == CHIP_RV635))
1955                         dev_priv->ram_width = 2 * chansize;
1956         } else if (dev_priv->chip_family == CHIP_RV515) {
1957                 tmp = radeon_read_mc_reg(dev_priv, RV515_MC_CNTL);
1958                 tmp &= RV515_MEM_NUM_CHANNELS_MASK;
1959                 switch (tmp) {
1960                 case 0: dev_priv->ram_width = 64; break;
1961                 case 1: dev_priv->ram_width = 128; break;
1962                 default: dev_priv->ram_width = 128; break;
1963                 }
1964         } else if ((dev_priv->chip_family >= CHIP_R520) &&
1965                    (dev_priv->chip_family <= CHIP_RV570)) {
1966                 tmp = radeon_read_mc_reg(dev_priv, R520_MC_CNTL0);
1967                 switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) {
1968                 case 0: dev_priv->ram_width = 32; break;
1969                 case 1: dev_priv->ram_width = 64; break;
1970                 case 2: dev_priv->ram_width = 128; break;
1971                 case 3: dev_priv->ram_width = 256; break;
1972                 default: dev_priv->ram_width = 128; break;
1973                 }
1974         } else if ((dev_priv->chip_family == CHIP_RV100) ||
1975                    (dev_priv->chip_family == CHIP_RS100) ||
1976                    (dev_priv->chip_family == CHIP_RS200)) {
1977                 tmp = RADEON_READ(RADEON_MEM_CNTL);
1978                 if (tmp & RV100_HALF_MODE)
1979                         dev_priv->ram_width = 32;
1980                 else
1981                         dev_priv->ram_width = 64;
1982
1983                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
1984                         dev_priv->ram_width /= 4;
1985                         dev_priv->is_ddr = true;
1986                 }
1987         } else if (dev_priv->chip_family <= CHIP_RV280) {
1988                 tmp = RADEON_READ(RADEON_MEM_CNTL);
1989                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK)
1990                         dev_priv->ram_width = 128;
1991                 else
1992                         dev_priv->ram_width = 64;
1993         } else {
1994                 /* newer IGPs */
1995                 dev_priv->ram_width = 128;
1996         }
1997         DRM_DEBUG("RAM width %d bits %cDR\n", dev_priv->ram_width, dev_priv->is_ddr ? 'D' : 'S');
1998 }
1999
2000 static void radeon_force_some_clocks(struct drm_device *dev)
2001 {
2002         struct drm_radeon_private *dev_priv = dev->dev_private;
2003         uint32_t tmp;
2004
2005         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2006         tmp |= RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_VIP;
2007         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2008 }
2009
2010 static void radeon_set_dynamic_clock(struct drm_device *dev, int mode)
2011 {
2012         struct drm_radeon_private *dev_priv = dev->dev_private;
2013         uint32_t tmp;
2014
2015         switch(mode) {
2016         case 0:
2017                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
2018                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2019                         tmp |= (RADEON_SCLK_FORCE_CP   | RADEON_SCLK_FORCE_HDP |
2020                                 RADEON_SCLK_FORCE_DISP1 | RADEON_SCLK_FORCE_TOP |
2021                                 RADEON_SCLK_FORCE_E2   | RADEON_SCLK_FORCE_SE  |
2022                                 RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_VIP |
2023                                 RADEON_SCLK_FORCE_RE   | RADEON_SCLK_FORCE_PB  |
2024                                 RADEON_SCLK_FORCE_TAM  | RADEON_SCLK_FORCE_TDM |
2025                                 RADEON_SCLK_FORCE_RB);
2026                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2027                 } else if (dev_priv->chip_family == CHIP_RV350) {
2028                         /* for RV350/M10, no delays are required. */
2029                         tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2030                         tmp |= (R300_SCLK_FORCE_TCL |
2031                                 R300_SCLK_FORCE_GA |
2032                                 R300_SCLK_FORCE_CBA);
2033                         RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2034
2035                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2036                         tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
2037                                  RADEON_SCLK_FORCE_HDP   | RADEON_SCLK_FORCE_DISP1   |
2038                                  RADEON_SCLK_FORCE_TOP   | RADEON_SCLK_FORCE_E2      |
2039                                  R300_SCLK_FORCE_VAP     | RADEON_SCLK_FORCE_IDCT    |
2040                                  RADEON_SCLK_FORCE_VIP   | R300_SCLK_FORCE_SR        |
2041                                  R300_SCLK_FORCE_PX      | R300_SCLK_FORCE_TX        |
2042                                  R300_SCLK_FORCE_US      | RADEON_SCLK_FORCE_TV_SCLK |
2043                                  R300_SCLK_FORCE_SU      | RADEON_SCLK_FORCE_OV0);
2044                         tmp |=  RADEON_DYN_STOP_LAT_MASK;
2045                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2046
2047                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2048                         tmp &= ~RADEON_SCLK_MORE_FORCEON;
2049                         tmp |= RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
2050                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2051
2052                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2053                         tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
2054                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
2055                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2056
2057                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2058                         tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
2059                                 RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2060                                 RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
2061                                 R300_DVOCLK_ALWAYS_ONb            |
2062                                 RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2063                                 RADEON_PIXCLK_GV_ALWAYS_ONb       |
2064                                 R300_PIXCLK_DVO_ALWAYS_ONb        |
2065                                 RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2066                                 RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
2067                                 R300_PIXCLK_TRANS_ALWAYS_ONb      |
2068                                 R300_PIXCLK_TVO_ALWAYS_ONb        |
2069                                 R300_P2G2CLK_ALWAYS_ONb           |
2070                                 R300_P2G2CLK_ALWAYS_ONb);
2071                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2072                 } else {
2073                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2074                         tmp |= (RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_E2);
2075                         tmp |= RADEON_SCLK_FORCE_SE;
2076
2077                         if ( dev_priv->flags & RADEON_SINGLE_CRTC ) {
2078                                 tmp |= ( RADEON_SCLK_FORCE_RB    |
2079                                          RADEON_SCLK_FORCE_TDM   |
2080                                          RADEON_SCLK_FORCE_TAM   |
2081                                          RADEON_SCLK_FORCE_PB    |
2082                                          RADEON_SCLK_FORCE_RE    |
2083                                          RADEON_SCLK_FORCE_VIP   |
2084                                          RADEON_SCLK_FORCE_IDCT  |
2085                                          RADEON_SCLK_FORCE_TOP   |
2086                                          RADEON_SCLK_FORCE_DISP1 |
2087                                          RADEON_SCLK_FORCE_DISP2 |
2088                                          RADEON_SCLK_FORCE_HDP    );
2089                         } else if ((dev_priv->chip_family == CHIP_R300) ||
2090                                    (dev_priv->chip_family == CHIP_R350)) {
2091                                 tmp |= ( RADEON_SCLK_FORCE_HDP   |
2092                                          RADEON_SCLK_FORCE_DISP1 |
2093                                          RADEON_SCLK_FORCE_DISP2 |
2094                                          RADEON_SCLK_FORCE_TOP   |
2095                                          RADEON_SCLK_FORCE_IDCT  |
2096                                          RADEON_SCLK_FORCE_VIP);
2097                         }
2098
2099                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2100
2101                         udelay(16000);
2102
2103                         if ((dev_priv->chip_family == CHIP_R300) ||
2104                             (dev_priv->chip_family == CHIP_R350)) {
2105                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2106                                 tmp |= ( R300_SCLK_FORCE_TCL |
2107                                          R300_SCLK_FORCE_GA  |
2108                                          R300_SCLK_FORCE_CBA);
2109                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2110                                 udelay(16000);
2111                         }
2112
2113                         if (dev_priv->flags & RADEON_IS_IGP) {
2114                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2115                                 tmp &= ~(RADEON_FORCEON_MCLKA |
2116                                          RADEON_FORCEON_YCLKA);
2117                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, tmp);
2118                                 udelay(16000);
2119                         }
2120
2121                         if ((dev_priv->chip_family == CHIP_RV200) ||
2122                             (dev_priv->chip_family == CHIP_RV250) ||
2123                             (dev_priv->chip_family == CHIP_RV280)) {
2124                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2125                                 tmp |= RADEON_SCLK_MORE_FORCEON;
2126                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2127                                 udelay(16000);
2128                         }
2129
2130                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2131                         tmp &= ~(RADEON_PIX2CLK_ALWAYS_ONb         |
2132                                  RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2133                                  RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2134                                  RADEON_PIXCLK_GV_ALWAYS_ONb       |
2135                                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
2136                                  RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2137                                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
2138
2139                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2140                         udelay(16000);
2141
2142                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2143                         tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb  |
2144                                  RADEON_PIXCLK_DAC_ALWAYS_ONb);
2145                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2146                 }
2147                 DRM_DEBUG("Dynamic Clock Scaling Disabled\n");
2148                 break;
2149         case 1:
2150                 if (dev_priv->flags & RADEON_SINGLE_CRTC) {
2151                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2152                         if ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) >
2153                             RADEON_CFG_ATI_REV_A13) {
2154                                 tmp &= ~(RADEON_SCLK_FORCE_CP | RADEON_SCLK_FORCE_RB);
2155                         }
2156                         tmp &= ~(RADEON_SCLK_FORCE_HDP  | RADEON_SCLK_FORCE_DISP1 |
2157                                  RADEON_SCLK_FORCE_TOP  | RADEON_SCLK_FORCE_SE   |
2158                                  RADEON_SCLK_FORCE_IDCT | RADEON_SCLK_FORCE_RE   |
2159                                  RADEON_SCLK_FORCE_PB   | RADEON_SCLK_FORCE_TAM  |
2160                                  RADEON_SCLK_FORCE_TDM);
2161                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2162                 } else if ((dev_priv->chip_family == CHIP_R300) ||
2163                            (dev_priv->chip_family == CHIP_R350) ||
2164                            (dev_priv->chip_family == CHIP_RV350)) {
2165                         if (dev_priv->chip_family == CHIP_RV350) {
2166                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2167                                 tmp &= ~(R300_SCLK_FORCE_TCL |
2168                                          R300_SCLK_FORCE_GA  |
2169                                          R300_SCLK_FORCE_CBA);
2170                                 tmp |=  (R300_SCLK_TCL_MAX_DYN_STOP_LAT |
2171                                          R300_SCLK_GA_MAX_DYN_STOP_LAT  |
2172                                          R300_SCLK_CBA_MAX_DYN_STOP_LAT);
2173                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2174
2175                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2176                                 tmp &= ~(RADEON_SCLK_FORCE_DISP2 | RADEON_SCLK_FORCE_CP      |
2177                                          RADEON_SCLK_FORCE_HDP   | RADEON_SCLK_FORCE_DISP1   |
2178                                          RADEON_SCLK_FORCE_TOP   | RADEON_SCLK_FORCE_E2      |
2179                                          R300_SCLK_FORCE_VAP     | RADEON_SCLK_FORCE_IDCT    |
2180                                          RADEON_SCLK_FORCE_VIP   | R300_SCLK_FORCE_SR        |
2181                                          R300_SCLK_FORCE_PX      | R300_SCLK_FORCE_TX        |
2182                                          R300_SCLK_FORCE_US      | RADEON_SCLK_FORCE_TV_SCLK |
2183                                          R300_SCLK_FORCE_SU      | RADEON_SCLK_FORCE_OV0);
2184                                 tmp |=  RADEON_DYN_STOP_LAT_MASK;
2185                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2186
2187                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2188                                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
2189                                 tmp |=  RADEON_SCLK_MORE_MAX_DYN_STOP_LAT;
2190                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2191
2192                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2193                                 tmp |= (RADEON_PIXCLK_ALWAYS_ONb |
2194                                         RADEON_PIXCLK_DAC_ALWAYS_ONb);
2195                                 RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2196
2197                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2198                                 tmp |= (RADEON_PIX2CLK_ALWAYS_ONb         |
2199                                         RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2200                                         RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb |
2201                                         R300_DVOCLK_ALWAYS_ONb            |
2202                                         RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2203                                         RADEON_PIXCLK_GV_ALWAYS_ONb       |
2204                                         R300_PIXCLK_DVO_ALWAYS_ONb        |
2205                                         RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2206                                         RADEON_PIXCLK_TMDS_ALWAYS_ONb     |
2207                                         R300_PIXCLK_TRANS_ALWAYS_ONb      |
2208                                         R300_PIXCLK_TVO_ALWAYS_ONb        |
2209                                         R300_P2G2CLK_ALWAYS_ONb           |
2210                                         R300_P2G2CLK_ALWAYS_ONb);
2211                                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2212
2213                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_MISC);
2214                                 tmp |= (RADEON_MC_MCLK_DYN_ENABLE |
2215                                         RADEON_IO_MCLK_DYN_ENABLE);
2216                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_MISC, tmp);
2217
2218                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2219                                 tmp |= (RADEON_FORCEON_MCLKA |
2220                                         RADEON_FORCEON_MCLKB);
2221
2222                                 tmp &= ~(RADEON_FORCEON_YCLKA  |
2223                                          RADEON_FORCEON_YCLKB  |
2224                                          RADEON_FORCEON_MC);
2225
2226                                 /* Some releases of vbios have set DISABLE_MC_MCLKA
2227                                    and DISABLE_MC_MCLKB bits in the vbios table.  Setting these
2228                                    bits will cause H/W hang when reading video memory with dynamic clocking
2229                                    enabled. */
2230                                 if ((tmp & R300_DISABLE_MC_MCLKA) &&
2231                                     (tmp & R300_DISABLE_MC_MCLKB)) {
2232                                         /* If both bits are set, then check the active channels */
2233                                         tmp = RADEON_READ_PLL(dev_priv, RADEON_MCLK_CNTL);
2234                                         if (dev_priv->ram_width == 64) {
2235                                                 if (RADEON_READ(RADEON_MEM_CNTL) & R300_MEM_USE_CD_CH_ONLY)
2236                                                         tmp &= ~R300_DISABLE_MC_MCLKB;
2237                                                 else
2238                                                         tmp &= ~R300_DISABLE_MC_MCLKA;
2239                                         } else {
2240                                                 tmp &= ~(R300_DISABLE_MC_MCLKA |
2241                                                          R300_DISABLE_MC_MCLKB);
2242                                         }
2243                                 }
2244
2245                                 RADEON_WRITE_PLL(dev_priv, RADEON_MCLK_CNTL, tmp);
2246                         } else {
2247                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2248                                 tmp &= ~(R300_SCLK_FORCE_VAP);
2249                                 tmp |= RADEON_SCLK_FORCE_CP;
2250                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2251                                 udelay(15000);
2252
2253                                 tmp = RADEON_READ_PLL(dev_priv, R300_SCLK_CNTL2);
2254                                 tmp &= ~(R300_SCLK_FORCE_TCL |
2255                                          R300_SCLK_FORCE_GA  |
2256                                          R300_SCLK_FORCE_CBA);
2257                                 RADEON_WRITE_PLL(dev_priv, R300_SCLK_CNTL2, tmp);
2258                         }
2259                 } else {
2260                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL);
2261                         tmp &= ~(RADEON_ACTIVE_HILO_LAT_MASK     |
2262                                  RADEON_DISP_DYN_STOP_LAT_MASK   |
2263                                  RADEON_DYN_STOP_MODE_MASK);
2264
2265                         tmp |= (RADEON_ENGIN_DYNCLK_MODE |
2266                                 (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT));
2267                         RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PWRMGT_CNTL, tmp);
2268                         udelay(15000);
2269
2270                         tmp = RADEON_READ_PLL(dev_priv, RADEON_CLK_PIN_CNTL);
2271                         tmp |= RADEON_SCLK_DYN_START_CNTL;
2272                         RADEON_WRITE_PLL(dev_priv, RADEON_CLK_PIN_CNTL, tmp);
2273                         udelay(15000);
2274
2275                         /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200
2276                            to lockup randomly, leave them as set by BIOS.
2277                         */
2278                         tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_CNTL);
2279                         /*tmp &= RADEON_SCLK_SRC_SEL_MASK;*/
2280                         tmp &= ~RADEON_SCLK_FORCEON_MASK;
2281
2282                         /*RAGE_6::A11 A12 A12N1 A13, RV250::A11 A12, R300*/
2283                         if (((dev_priv->chip_family == CHIP_RV250) &&
2284                              ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2285                               RADEON_CFG_ATI_REV_A13)) ||
2286                             ((dev_priv->chip_family == CHIP_RV100) &&
2287                              ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <=
2288                               RADEON_CFG_ATI_REV_A13))){
2289                                 tmp |= RADEON_SCLK_FORCE_CP;
2290                                 tmp |= RADEON_SCLK_FORCE_VIP;
2291                         }
2292
2293                         RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_CNTL, tmp);
2294
2295                         if ((dev_priv->chip_family == CHIP_RV200) ||
2296                             (dev_priv->chip_family == CHIP_RV250) ||
2297                             (dev_priv->chip_family == CHIP_RV280)) {
2298                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_SCLK_MORE_CNTL);
2299                                 tmp &= ~RADEON_SCLK_MORE_FORCEON;
2300
2301                                 /* RV200::A11 A12 RV250::A11 A12 */
2302                                 if (((dev_priv->chip_family == CHIP_RV200) ||
2303                                      (dev_priv->chip_family == CHIP_RV250)) &&
2304                                     ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2305                                      RADEON_CFG_ATI_REV_A13)) {
2306                                         tmp |= RADEON_SCLK_MORE_FORCEON;
2307                                 }
2308                                 RADEON_WRITE_PLL(dev_priv, RADEON_SCLK_MORE_CNTL, tmp);
2309                                 udelay(15000);
2310                         }
2311
2312                         /* RV200::A11 A12, RV250::A11 A12 */
2313                         if (((dev_priv->chip_family == CHIP_RV200) ||
2314                              (dev_priv->chip_family == CHIP_RV250)) &&
2315                             ((RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) <
2316                              RADEON_CFG_ATI_REV_A13)) {
2317                                 tmp = RADEON_READ_PLL(dev_priv, RADEON_PLL_PWRMGT_CNTL);
2318                                 tmp |= RADEON_TCL_BYPASS_DISABLE;
2319                                 RADEON_WRITE_PLL(dev_priv, RADEON_PLL_PWRMGT_CNTL, tmp);
2320                         }
2321                         udelay(15000);
2322
2323                         /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK)*/
2324                         tmp = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
2325                         tmp |=  (RADEON_PIX2CLK_ALWAYS_ONb         |
2326                                  RADEON_PIX2CLK_DAC_ALWAYS_ONb     |
2327                                  RADEON_PIXCLK_BLEND_ALWAYS_ONb    |
2328                                  RADEON_PIXCLK_GV_ALWAYS_ONb       |
2329                                  RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb |
2330                                  RADEON_PIXCLK_LVDS_ALWAYS_ONb     |
2331                                  RADEON_PIXCLK_TMDS_ALWAYS_ONb);
2332
2333                         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
2334                         udelay(15000);
2335
2336                         tmp = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
2337                         tmp |= (RADEON_PIXCLK_ALWAYS_ONb  |
2338                                 RADEON_PIXCLK_DAC_ALWAYS_ONb);
2339
2340                         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
2341                         udelay(15000);
2342                 }
2343                 DRM_DEBUG("Dynamic Clock Scaling Enabled\n");
2344                 break;
2345         default:
2346                 break;
2347         }
2348
2349 }
2350
2351 int radeon_modeset_cp_suspend(struct drm_device *dev)
2352 {
2353         drm_radeon_private_t *dev_priv = dev->dev_private;
2354         int ret;
2355
2356         ret = radeon_do_cp_idle(dev_priv);
2357         if (ret)
2358                 DRM_ERROR("failed to idle CP on suspend\n");
2359
2360         radeon_do_cp_stop(dev_priv);
2361         radeon_do_engine_reset(dev);
2362         if (dev_priv->flags & RADEON_IS_AGP) {
2363         } else {
2364                 radeon_set_pcigart(dev_priv, 0);
2365         }
2366
2367         return 0;
2368 }
2369
2370 int radeon_modeset_cp_resume(struct drm_device *dev)
2371 {
2372         drm_radeon_private_t *dev_priv = dev->dev_private;
2373
2374         radeon_do_wait_for_idle(dev_priv);
2375 #if __OS_HAS_AGP
2376         if (dev_priv->flags & RADEON_IS_AGP) {
2377                 /* Turn off PCI GART */
2378                 radeon_set_pcigart(dev_priv, 0);
2379         } else
2380 #endif
2381         {
2382                 /* Turn on PCI GART */
2383                 radeon_set_pcigart(dev_priv, 1);
2384         }
2385         radeon_gart_flush(dev);
2386
2387         radeon_cp_load_microcode(dev_priv);
2388         radeon_cp_init_ring_buffer(dev, dev_priv);
2389
2390         radeon_do_engine_reset(dev);
2391
2392         radeon_test_writeback(dev_priv);
2393
2394         radeon_do_cp_start(dev_priv);
2395         return 0;
2396 }
2397
2398 #if __OS_HAS_AGP
2399 int radeon_modeset_agp_init(struct drm_device *dev)
2400 {
2401         drm_radeon_private_t *dev_priv = dev->dev_private;
2402         struct drm_agp_mode mode;
2403         struct drm_agp_info info;
2404         int ret;
2405         int default_mode;
2406         uint32_t agp_status;
2407         bool is_v3;
2408
2409         /* Acquire AGP. */
2410         ret = drm_agp_acquire(dev);
2411         if (ret) {
2412                 DRM_ERROR("Unable to acquire AGP: %d\n", ret);
2413                 return ret;
2414         }
2415
2416         ret = drm_agp_info(dev, &info);
2417         if (ret) {
2418                 DRM_ERROR("Unable to get AGP info: %d\n", ret);
2419                 return ret;
2420         }
2421
2422         mode.mode = info.mode;
2423
2424         agp_status = (RADEON_READ(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
2425         is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
2426
2427         if (is_v3) {
2428                 default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
2429         } else {
2430                 if (agp_status & RADEON_AGP_4X_MODE) default_mode = 4;
2431                 else if (agp_status & RADEON_AGP_2X_MODE) default_mode = 2;
2432                 else default_mode = 1;
2433         }
2434
2435         if (radeon_agpmode > 0) {
2436                 if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
2437                     (radeon_agpmode > (is_v3 ? 8 : 4)) ||
2438                     (radeon_agpmode & (radeon_agpmode - 1))) {
2439                         DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
2440                                   radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
2441                                   default_mode);
2442                         radeon_agpmode = default_mode;
2443                 }
2444                 else
2445                         DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
2446         } else
2447                 radeon_agpmode = default_mode;
2448
2449         mode.mode &= ~RADEON_AGP_MODE_MASK;
2450         if (is_v3) {
2451                 switch(radeon_agpmode) {
2452                 case 8:
2453                         mode.mode |= RADEON_AGPv3_8X_MODE;
2454                         break;
2455                 case 4:
2456                 default:
2457                         mode.mode |= RADEON_AGPv3_4X_MODE;
2458                         break;
2459                 }
2460         } else {
2461                 switch(radeon_agpmode) {
2462                 case 4: mode.mode |= RADEON_AGP_4X_MODE;
2463                 case 2: mode.mode |= RADEON_AGP_2X_MODE;
2464                 case 1:
2465                 default:
2466                         mode.mode |= RADEON_AGP_1X_MODE;
2467                         break;
2468                 }
2469         }
2470
2471         mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
2472
2473         ret = drm_agp_enable(dev, mode);
2474         if (ret) {
2475                 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
2476                 return ret;
2477         }
2478
2479         /* workaround some hw issues */
2480         if (dev_priv->chip_family < CHIP_R200) {
2481                 RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000);
2482         }
2483         return 0;
2484 }
2485
2486 void radeon_modeset_agp_destroy(struct drm_device *dev)
2487 {
2488         if (dev->agp->acquired)
2489                 drm_agp_release(dev);
2490 }
2491 #endif
2492
2493 int radeon_modeset_cp_init(struct drm_device *dev)
2494 {
2495         drm_radeon_private_t *dev_priv = dev->dev_private;
2496
2497         /* allocate a ring and ring rptr bits from GART space */
2498         /* these are allocated in GEM files */
2499
2500         /* Start with assuming that writeback doesn't work */
2501         dev_priv->writeback_works = 0;
2502
2503         if (dev_priv->chip_family > CHIP_R600)
2504                 return 0;
2505
2506         dev_priv->usec_timeout = RADEON_DEFAULT_CP_TIMEOUT;
2507         dev_priv->ring.size = RADEON_DEFAULT_RING_SIZE;
2508         dev_priv->cp_mode = RADEON_CSQ_PRIBM_INDBM;
2509
2510         dev_priv->ring.start = (u32 *)(void *)(unsigned long)dev_priv->mm.ring.kmap.virtual;
2511         dev_priv->ring.end = (u32 *)(void *)(unsigned long)dev_priv->mm.ring.kmap.virtual +
2512                 dev_priv->ring.size / sizeof(u32);
2513         dev_priv->ring.size_l2qw = drm_order(dev_priv->ring.size / 8);
2514         dev_priv->ring.rptr_update = 4096;
2515         dev_priv->ring.rptr_update_l2qw = drm_order(4096 / 8);
2516         dev_priv->ring.fetch_size = 32;
2517         dev_priv->ring.fetch_size_l2ow = drm_order(32 / 16);
2518         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2519         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2520
2521         dev_priv->new_memmap = true;
2522
2523         r300_init_reg_flags(dev);
2524
2525 #if __OS_HAS_AGP
2526         if (dev_priv->flags & RADEON_IS_AGP)
2527                 radeon_modeset_agp_init(dev);
2528 #endif
2529
2530         return radeon_modeset_cp_resume(dev);
2531 }
2532
2533 static bool radeon_get_bios(struct drm_device *dev)
2534 {
2535         drm_radeon_private_t *dev_priv = dev->dev_private;
2536         u8 __iomem *bios;
2537         size_t size;
2538         uint16_t tmp;
2539
2540         bios = pci_map_rom(dev->pdev, &size);
2541         if (!bios)
2542                 return -1;
2543
2544         dev_priv->bios = kmalloc(size, GFP_KERNEL);
2545         if (!dev_priv->bios) {
2546                 pci_unmap_rom(dev->pdev, bios);
2547                 return -1;
2548         }
2549
2550         memcpy(dev_priv->bios, bios, size);
2551
2552         pci_unmap_rom(dev->pdev, bios);
2553
2554         if (dev_priv->bios[0] != 0x55 || dev_priv->bios[1] != 0xaa)
2555                 goto free_bios;
2556
2557         dev_priv->bios_header_start = radeon_bios16(dev_priv, 0x48);
2558
2559         if (!dev_priv->bios_header_start)
2560                 goto free_bios;
2561
2562         tmp = dev_priv->bios_header_start + 4;
2563
2564         if (!memcmp(dev_priv->bios + tmp, "ATOM", 4) ||
2565             !memcmp(dev_priv->bios + tmp, "MOTA", 4))
2566                 dev_priv->is_atom_bios = true;
2567         else
2568                 dev_priv->is_atom_bios = false;
2569
2570         DRM_DEBUG("%sBIOS detected\n", dev_priv->is_atom_bios ? "ATOM" : "COM");
2571         return true;
2572 free_bios:
2573         kfree(dev_priv->bios);
2574         dev_priv->bios = NULL;
2575         return false;
2576 }
2577
2578 int radeon_modeset_preinit(struct drm_device *dev)
2579 {
2580         drm_radeon_private_t *dev_priv = dev->dev_private;
2581         static struct card_info card;
2582         int ret;
2583
2584         card.dev = dev;
2585         card.reg_read = cail_reg_read;
2586         card.reg_write = cail_reg_write;
2587         card.mc_read = cail_mc_read;
2588         card.mc_write = cail_mc_write;
2589
2590         ret = radeon_get_bios(dev);
2591         if (!ret)
2592                 return -1;
2593
2594         if (dev_priv->is_atom_bios) {
2595                 dev_priv->mode_info.atom_context = atom_parse(&card, dev_priv->bios);
2596                 radeon_atom_initialize_bios_scratch_regs(dev);
2597         } else
2598                 radeon_combios_initialize_bios_scratch_regs(dev);
2599
2600         radeon_get_clock_info(dev);
2601
2602         return 0;
2603 }
2604
2605 int radeon_static_clocks_init(struct drm_device *dev)
2606 {
2607         drm_radeon_private_t *dev_priv = dev->dev_private;
2608
2609         if (radeon_dynclks != -1) {
2610
2611                 if (dev_priv->chip_family == CHIP_RS400 ||
2612                     dev_priv->chip_family == CHIP_RS480)
2613                         radeon_dynclks = 0;
2614
2615                 if ((dev_priv->flags & RADEON_IS_MOBILITY) && !radeon_is_avivo(dev_priv)) {
2616                         radeon_set_dynamic_clock(dev, radeon_dynclks);
2617                 } else if (radeon_is_avivo(dev_priv)) {
2618                         if (radeon_dynclks) {
2619                                 radeon_atom_static_pwrmgt_setup(dev, 1);
2620                                 radeon_atom_dyn_clk_setup(dev, 1);
2621                         }
2622                 }
2623         }
2624         if (radeon_is_r300(dev_priv) || radeon_is_rv100(dev_priv))
2625                 radeon_force_some_clocks(dev);
2626         return 0;
2627 }
2628
2629 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2630 {
2631         drm_radeon_private_t *dev_priv;
2632         int ret = 0;
2633
2634         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2635         if (dev_priv == NULL)
2636                 return -ENOMEM;
2637
2638         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2639         dev->dev_private = (void *)dev_priv;
2640         dev_priv->flags = flags;
2641
2642         switch (flags & RADEON_FAMILY_MASK) {
2643         case CHIP_R100:
2644         case CHIP_RV200:
2645         case CHIP_R200:
2646         case CHIP_R300:
2647         case CHIP_R350:
2648         case CHIP_R420:
2649         case CHIP_RV410:
2650         case CHIP_RV515:
2651         case CHIP_R520:
2652         case CHIP_RV570:
2653         case CHIP_R580:
2654                 dev_priv->flags |= RADEON_HAS_HIERZ;
2655                 break;
2656         default:
2657                 /* all other chips have no hierarchical z buffer */
2658                 break;
2659         }
2660
2661         dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
2662         if (drm_device_is_agp(dev))
2663                 dev_priv->flags |= RADEON_IS_AGP;
2664         else if (drm_device_is_pcie(dev))
2665                 dev_priv->flags |= RADEON_IS_PCIE;
2666         else
2667                 dev_priv->flags |= RADEON_IS_PCI;
2668
2669         DRM_DEBUG("%s card detected\n",
2670                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2671
2672         if (dev_priv->flags & RADEON_IS_AGP) {
2673
2674                 /* disable AGP for any chips after RV280 if not specified */
2675                 if ((dev_priv->chip_family > CHIP_RV280) && (radeon_agpmode == 0))
2676                         radeon_agpmode = -1;
2677
2678                 if (radeon_agpmode == -1) {
2679                         DRM_INFO("Forcing AGP to PCI mode\n");
2680                         dev_priv->flags &= ~RADEON_IS_AGP;
2681                 }
2682         }
2683
2684
2685         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2686                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2687                          _DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio);
2688         if (ret != 0)
2689                 return ret;
2690
2691         if (drm_core_check_feature(dev, DRIVER_MODESET))
2692                 radeon_modeset_preinit(dev);
2693
2694         radeon_get_vram_type(dev);
2695
2696         dev_priv->pll_errata = 0;
2697
2698         if (dev_priv->chip_family == CHIP_R300 &&
2699             (RADEON_READ(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11)
2700                 dev_priv->pll_errata |= CHIP_ERRATA_R300_CG;
2701
2702         if (dev_priv->chip_family == CHIP_RV200 ||
2703             dev_priv->chip_family == CHIP_RS200)
2704                 dev_priv->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2705
2706
2707         if (dev_priv->chip_family == CHIP_RV100 ||
2708             dev_priv->chip_family == CHIP_RS100 ||
2709             dev_priv->chip_family == CHIP_RS200)
2710                 dev_priv->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2711
2712
2713         if (drm_core_check_feature(dev, DRIVER_MODESET))
2714                 radeon_static_clocks_init(dev);
2715
2716         /* init memory manager - start with all of VRAM and a 32MB GART aperture for now */
2717         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2718
2719         drm_bo_driver_init(dev);
2720
2721         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2722
2723                 ret = radeon_gem_mm_init(dev);
2724                 if (ret)
2725                         goto modeset_fail;
2726                 radeon_modeset_init(dev);
2727
2728                 radeon_modeset_cp_init(dev);
2729                 dev->devname = kstrdup(DRIVER_NAME, GFP_KERNEL);
2730
2731                 drm_irq_install(dev);
2732         }
2733
2734
2735         return ret;
2736 modeset_fail:
2737         dev->driver->driver_features &= ~DRIVER_MODESET;
2738         drm_put_minor(&dev->control);
2739         return ret;
2740 }
2741
2742
2743 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2744 {
2745         struct drm_radeon_master_private *master_priv;
2746         unsigned long sareapage;
2747         int ret;
2748
2749         master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
2750         if (!master_priv)
2751                 return -ENOMEM;
2752
2753         /* prebuild the SAREA */
2754         sareapage = max(SAREA_MAX, PAGE_SIZE);
2755         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
2756                          &master_priv->sarea);
2757         if (ret) {
2758                 DRM_ERROR("SAREA setup failed\n");
2759                 return ret;
2760         }
2761         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2762         master_priv->sarea_priv->pfCurrentPage = 0;
2763
2764         master->driver_priv = master_priv;
2765         return 0;
2766 }
2767
2768 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2769 {
2770         struct drm_radeon_master_private *master_priv = master->driver_priv;
2771
2772         if (!master_priv)
2773                 return;
2774
2775         if (master_priv->sarea_priv &&
2776             master_priv->sarea_priv->pfCurrentPage != 0)
2777                 radeon_cp_dispatch_flip(dev, master);
2778
2779         master_priv->sarea_priv = NULL;
2780         if (master_priv->sarea)
2781                 drm_rmmap_locked(dev, master_priv->sarea);
2782
2783         drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
2784
2785         master->driver_priv = NULL;
2786 }
2787 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2788  * have to find them.
2789  */
2790 int radeon_driver_firstopen(struct drm_device *dev)
2791 {
2792         drm_radeon_private_t *dev_priv = dev->dev_private;
2793
2794         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2795
2796         return 0;
2797 }
2798
2799 int radeon_driver_unload(struct drm_device *dev)
2800 {
2801         drm_radeon_private_t *dev_priv = dev->dev_private;
2802
2803         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2804                 drm_irq_uninstall(dev);
2805                 radeon_modeset_cleanup(dev);
2806                 radeon_gem_mm_fini(dev);
2807 #if __OS_HAS_AGP
2808                 if (dev_priv->flags & RADEON_IS_AGP)
2809                         radeon_modeset_agp_destroy(dev);
2810 #endif
2811         }
2812
2813         drm_bo_driver_finish(dev);
2814         drm_rmmap(dev, dev_priv->mmio);
2815
2816         DRM_DEBUG("\n");
2817         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2818
2819         dev->dev_private = NULL;
2820         return 0;
2821 }
2822
2823 void radeon_gart_flush(struct drm_device *dev)
2824 {
2825         drm_radeon_private_t *dev_priv = dev->dev_private;
2826
2827         if (dev_priv->flags & RADEON_IS_IGPGART) {
2828                 IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
2829                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE);
2830                 IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
2831                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
2832         } else if (dev_priv->flags & RADEON_IS_PCIE) {
2833                 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
2834                 tmp |= RADEON_PCIE_TX_GART_INVALIDATE_TLB;
2835                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
2836                 tmp &= ~RADEON_PCIE_TX_GART_INVALIDATE_TLB;
2837                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
2838         } else {
2839
2840
2841         }
2842
2843 }