shared-core/radeon_cp.c

   1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
   2 /*
   3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   5  * Copyright 2007 Advanced Micro Devices, Inc.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the "Software"),
  10  * to deal in the Software without restriction, including without limitation
  11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12  * and/or sell copies of the Software, and to permit persons to whom the
  13  * Software is furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the next
  16  * paragraph) shall be included in all copies or substantial portions of the
  17  * Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25  * DEALINGS IN THE SOFTWARE.
  26  *
  27  * Authors:
  28  *    Kevin E. Martin <martin@valinux.com>
  29  *    Gareth Hughes <gareth@valinux.com>
  30  */
  31
  32 #include "drmP.h"
  33 #include "drm.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36 #include "r300_reg.h"
  37
  38 #include "radeon_microcode.h"
  39 #define RADEON_FIFO_DEBUG       0
  40
  41 static int radeon_do_cleanup_cp(struct drm_device * dev);
  42 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  43
  44 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  45 {
  46         u32 ret;
  47         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
  48         ret = RADEON_READ(R520_MC_IND_DATA);
  49         RADEON_WRITE(R520_MC_IND_INDEX, 0);
  50         return ret;
  51 }
  52
  53 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  54 {
  55         u32 ret;
  56         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
  57         ret = RADEON_READ(RS480_NB_MC_DATA);
  58         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
  59         return ret;
  60 }
  61
  62 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  63 {
  64         u32 ret;
  65         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
  66         ret = RADEON_READ(RS690_MC_DATA);
  67         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
  68         return ret;
  69 }
  70
  71 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
  72 {
  73         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  74             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  75             return RS690_READ_MCIND(dev_priv, addr);
  76         else
  77             return RS480_READ_MCIND(dev_priv, addr);
  78 }
  79
  80 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
  81 {
  82
  83         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  84                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
  85         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  86                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
  87                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
  88         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
  89                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
  90         else
  91                 return RADEON_READ(RADEON_MC_FB_LOCATION);
  92 }
  93
  94 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
  95 {
  96         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
  97                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
  98         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
  99                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 100                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 101         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 102                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 103         else
 104                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 105 }
 106
 107 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 108 {
 109         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 110                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 111         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 112                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 113                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 114         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 115                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 116         else
 117                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 118 }
 119
 120 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 121 {
 122         u32 agp_base_hi = upper_32_bits(agp_base);
 123         u32 agp_base_lo = agp_base & 0xffffffff;
 124
 125         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 126                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 127                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 128         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 129                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 130                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 131                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 132         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 133                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 134                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 135         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 136                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 137                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 138                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 139         } else {
 140                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 141                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 142                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 143         }
 144 }
 145
 146 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 147 {
 148         drm_radeon_private_t *dev_priv = dev->dev_private;
 149
 150         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 151         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 152 }
 153
 154 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 155 {
 156         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 157         return RADEON_READ(RADEON_PCIE_DATA);
 158 }
 159
 160 #if RADEON_FIFO_DEBUG
 161 static void radeon_status(drm_radeon_private_t * dev_priv)
 162 {
 163         printk("%s:\n", __FUNCTION__);
 164         printk("RBBM_STATUS = 0x%08x\n",
 165                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 166         printk("CP_RB_RTPR = 0x%08x\n",
 167                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 168         printk("CP_RB_WTPR = 0x%08x\n",
 169                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 170         printk("AIC_CNTL = 0x%08x\n",
 171                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 172         printk("AIC_STAT = 0x%08x\n",
 173                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 174         printk("AIC_PT_BASE = 0x%08x\n",
 175                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 176         printk("TLB_ADDR = 0x%08x\n",
 177                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 178         printk("TLB_DATA = 0x%08x\n",
 179                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 180 }
 181 #endif
 182
 183 /* ================================================================
 184  * Engine, FIFO control
 185  */
 186
 187 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 188 {
 189         u32 tmp;
 190         int i;
 191
 192         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 193
 194         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 195                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 196                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 197                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 198
 199                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 200                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 201                               & RADEON_RB3D_DC_BUSY)) {
 202                                 return 0;
 203                         }
 204                         DRM_UDELAY(1);
 205                 }
 206         } else {
 207                 /* don't flush or purge cache here or lockup */
 208                 return 0;
 209         }
 210
 211 #if RADEON_FIFO_DEBUG
 212         DRM_ERROR("failed!\n");
 213         radeon_status(dev_priv);
 214 #endif
 215         return -EBUSY;
 216 }
 217
 218 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 219 {
 220         int i;
 221
 222         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 223
 224         for (i = 0; i < dev_priv->usec_timeout; i++) {
 225                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 226                              & RADEON_RBBM_FIFOCNT_MASK);
 227                 if (slots >= entries)
 228                         return 0;
 229                 DRM_UDELAY(1);
 230         }
 231         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
 232                  RADEON_READ(RADEON_RBBM_STATUS),
 233                  RADEON_READ(R300_VAP_CNTL_STATUS));
 234
 235 #if RADEON_FIFO_DEBUG
 236         DRM_ERROR("failed!\n");
 237         radeon_status(dev_priv);
 238 #endif
 239         return -EBUSY;
 240 }
 241
 242 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 243 {
 244         int i, ret;
 245
 246         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 247
 248         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 249         if (ret)
 250                 return ret;
 251
 252         for (i = 0; i < dev_priv->usec_timeout; i++) {
 253                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 254                       & RADEON_RBBM_ACTIVE)) {
 255                         radeon_do_pixcache_flush(dev_priv);
 256                         return 0;
 257                 }
 258                 DRM_UDELAY(1);
 259         }
 260         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
 261                  RADEON_READ(RADEON_RBBM_STATUS),
 262                  RADEON_READ(R300_VAP_CNTL_STATUS));
 263
 264 #if RADEON_FIFO_DEBUG
 265         DRM_ERROR("failed!\n");
 266         radeon_status(dev_priv);
 267 #endif
 268         return -EBUSY;
 269 }
 270
 271 static void radeon_init_pipes(drm_radeon_private_t * dev_priv)
 272 {
 273         uint32_t gb_tile_config, gb_pipe_sel = 0;
 274
 275         /* RS4xx/RS6xx/R4xx/R5xx */
 276         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 277                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 278                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 279         } else {
 280                 /* R3xx */
 281                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 282                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 283                         dev_priv->num_gb_pipes = 2;
 284                 } else {
 285                         /* R3Vxx */
 286                         dev_priv->num_gb_pipes = 1;
 287                 }
 288         }
 289         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 290
 291         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 292
 293         switch(dev_priv->num_gb_pipes) {
 294         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 295         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 296         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 297         default:
 298         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 299         }
 300
 301         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 302                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 303                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 304         }
 305         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 306         radeon_do_wait_for_idle(dev_priv);
 307         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 308         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 309                                                R300_DC_AUTOFLUSH_ENABLE |
 310                                                R300_DC_DC_DISABLE_IGNORE_PE));
 311
 312
 313 }
 314
 315 /* ================================================================
 316  * CP control, initialization
 317  */
 318
 319 /* Load the microcode for the CP */
 320 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 321 {
 322         int i;
 323         DRM_DEBUG("\n");
 324
 325         radeon_do_wait_for_idle(dev_priv);
 326
 327         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 328
 329         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
 330             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
 331             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
 332             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
 333             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
 334                 DRM_INFO("Loading R100 Microcode\n");
 335                 for (i = 0; i < 256; i++) {
 336                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 337                                      R100_cp_microcode[i][1]);
 338                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 339                                      R100_cp_microcode[i][0]);
 340                 }
 341         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
 342                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
 343                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
 344                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
 345                 DRM_INFO("Loading R200 Microcode\n");
 346                 for (i = 0; i < 256; i++) {
 347                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 348                                      R200_cp_microcode[i][1]);
 349                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 350                                      R200_cp_microcode[i][0]);
 351                 }
 352         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 353                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
 354                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
 355                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
 356                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 357                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 358                 DRM_INFO("Loading R300 Microcode\n");
 359                 for (i = 0; i < 256; i++) {
 360                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 361                                      R300_cp_microcode[i][1]);
 362                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 363                                      R300_cp_microcode[i][0]);
 364                 }
 365         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 366                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
 367                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
 368                 DRM_INFO("Loading R400 Microcode\n");
 369                 for (i = 0; i < 256; i++) {
 370                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 371                                      R420_cp_microcode[i][1]);
 372                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 373                                      R420_cp_microcode[i][0]);
 374                 }
 375         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 376                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 377                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 378                 for (i = 0; i < 256; i++) {
 379                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 380                                      RS690_cp_microcode[i][1]);
 381                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 382                                      RS690_cp_microcode[i][0]);
 383                 }
 384         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
 385                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
 386                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
 387                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
 388                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
 389                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
 390                 DRM_INFO("Loading R500 Microcode\n");
 391                 for (i = 0; i < 256; i++) {
 392                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
 393                                      R520_cp_microcode[i][1]);
 394                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
 395                                      R520_cp_microcode[i][0]);
 396                 }
 397         }
 398 }
 399
 400 /* Flush any pending commands to the CP.  This should only be used just
 401  * prior to a wait for idle, as it informs the engine that the command
 402  * stream is ending.
 403  */
 404 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 405 {
 406         DRM_DEBUG("\n");
 407 #if 0
 408         u32 tmp;
 409
 410         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 411         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 412 #endif
 413 }
 414
 415 /* Wait for the CP to go idle.
 416  */
 417 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 418 {
 419         RING_LOCALS;
 420         DRM_DEBUG("\n");
 421
 422         BEGIN_RING(6);
 423
 424         RADEON_PURGE_CACHE();
 425         RADEON_PURGE_ZCACHE();
 426         RADEON_WAIT_UNTIL_IDLE();
 427
 428         ADVANCE_RING();
 429         COMMIT_RING();
 430
 431         return radeon_do_wait_for_idle(dev_priv);
 432 }
 433
 434 /* Start the Command Processor.
 435  */
 436 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 437 {
 438         RING_LOCALS;
 439         DRM_DEBUG("\n");
 440
 441         radeon_do_wait_for_idle(dev_priv);
 442
 443         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 444
 445         dev_priv->cp_running = 1;
 446
 447         BEGIN_RING(8);
 448         /* isync can only be written through cp on r5xx write it here */
 449         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 450         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 451                  RADEON_ISYNC_ANY3D_IDLE2D |
 452                  RADEON_ISYNC_WAIT_IDLEGUI |
 453                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 454         RADEON_PURGE_CACHE();
 455         RADEON_PURGE_ZCACHE();
 456         RADEON_WAIT_UNTIL_IDLE();
 457         ADVANCE_RING();
 458         COMMIT_RING();
 459
 460         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 461 }
 462
 463 /* Reset the Command Processor.  This will not flush any pending
 464  * commands, so you must wait for the CP command stream to complete
 465  * before calling this routine.
 466  */
 467 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 468 {
 469         u32 cur_read_ptr;
 470         DRM_DEBUG("\n");
 471
 472         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 473         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 474         SET_RING_HEAD(dev_priv, cur_read_ptr);
 475         dev_priv->ring.tail = cur_read_ptr;
 476 }
 477
 478 /* Stop the Command Processor.  This will not flush any pending
 479  * commands, so you must flush the command stream and wait for the CP
 480  * to go idle before calling this routine.
 481  */
 482 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 483 {
 484         DRM_DEBUG("\n");
 485
 486         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 487
 488         dev_priv->cp_running = 0;
 489 }
 490
 491 /* Reset the engine.  This will stop the CP if it is running.
 492  */
 493 static int radeon_do_engine_reset(struct drm_device * dev)
 494 {
 495         drm_radeon_private_t *dev_priv = dev->dev_private;
 496         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 497         DRM_DEBUG("\n");
 498
 499         radeon_do_pixcache_flush(dev_priv);
 500
 501         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 502                 /* may need something similar for newer chips */
 503                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 504                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 505
 506                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 507                                                     RADEON_FORCEON_MCLKA |
 508                                                     RADEON_FORCEON_MCLKB |
 509                                                     RADEON_FORCEON_YCLKA |
 510                                                     RADEON_FORCEON_YCLKB |
 511                                                     RADEON_FORCEON_MC |
 512                                                     RADEON_FORCEON_AIC));
 513         }
 514
 515         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 516
 517         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 518                                               RADEON_SOFT_RESET_CP |
 519                                               RADEON_SOFT_RESET_HI |
 520                                               RADEON_SOFT_RESET_SE |
 521                                               RADEON_SOFT_RESET_RE |
 522                                               RADEON_SOFT_RESET_PP |
 523                                               RADEON_SOFT_RESET_E2 |
 524                                               RADEON_SOFT_RESET_RB));
 525         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 526         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 527                                               ~(RADEON_SOFT_RESET_CP |
 528                                                 RADEON_SOFT_RESET_HI |
 529                                                 RADEON_SOFT_RESET_SE |
 530                                                 RADEON_SOFT_RESET_RE |
 531                                                 RADEON_SOFT_RESET_PP |
 532                                                 RADEON_SOFT_RESET_E2 |
 533                                                 RADEON_SOFT_RESET_RB)));
 534         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 535
 536         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 537                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 538                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 539                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 540         }
 541
 542         /* setup the raster pipes */
 543         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 544             radeon_init_pipes(dev_priv);
 545
 546         /* Reset the CP ring */
 547         radeon_do_cp_reset(dev_priv);
 548
 549         /* The CP is no longer running after an engine reset */
 550         dev_priv->cp_running = 0;
 551
 552         /* Reset any pending vertex, indirect buffers */
 553         radeon_freelist_reset(dev);
 554
 555         return 0;
 556 }
 557
 558 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 559                                        drm_radeon_private_t * dev_priv)
 560 {
 561         u32 ring_start, cur_read_ptr;
 562         u32 tmp;
 563
 564         /* Initialize the memory controller. With new memory map, the fb location
 565          * is not changed, it should have been properly initialized already. Part
 566          * of the problem is that the code below is bogus, assuming the GART is
 567          * always appended to the fb which is not necessarily the case
 568          */
 569         if (!dev_priv->new_memmap)
 570                 radeon_write_fb_location(dev_priv,
 571                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 572                              | (dev_priv->fb_location >> 16));
 573
 574 #if __OS_HAS_AGP
 575         if (dev_priv->flags & RADEON_IS_AGP) {
 576                 radeon_write_agp_base(dev_priv, dev->agp->base);
 577
 578                 radeon_write_agp_location(dev_priv,
 579                              (((dev_priv->gart_vm_start - 1 +
 580                                 dev_priv->gart_size) & 0xffff0000) |
 581                               (dev_priv->gart_vm_start >> 16)));
 582
 583                 ring_start = (dev_priv->cp_ring->offset
 584                               - dev->agp->base
 585                               + dev_priv->gart_vm_start);
 586         } else
 587 #endif
 588                 ring_start = (dev_priv->cp_ring->offset
 589                               - (unsigned long)dev->sg->virtual
 590                               + dev_priv->gart_vm_start);
 591
 592         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 593
 594         /* Set the write pointer delay */
 595         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 596
 597         /* Initialize the ring buffer's read and write pointers */
 598         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 599         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 600         SET_RING_HEAD(dev_priv, cur_read_ptr);
 601         dev_priv->ring.tail = cur_read_ptr;
 602
 603 #if __OS_HAS_AGP
 604         if (dev_priv->flags & RADEON_IS_AGP) {
 605                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 606                              dev_priv->ring_rptr->offset
 607                              - dev->agp->base + dev_priv->gart_vm_start);
 608         } else
 609 #endif
 610         {
 611                 struct drm_sg_mem *entry = dev->sg;
 612                 unsigned long tmp_ofs, page_ofs;
 613
 614                 tmp_ofs = dev_priv->ring_rptr->offset -
 615                                 (unsigned long)dev->sg->virtual;
 616                 page_ofs = tmp_ofs >> PAGE_SHIFT;
 617
 618                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
 619                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
 620                           (unsigned long)entry->busaddr[page_ofs],
 621                           entry->handle + tmp_ofs);
 622         }
 623
 624         /* Set ring buffer size */
 625 #ifdef __BIG_ENDIAN
 626         RADEON_WRITE(RADEON_CP_RB_CNTL,
 627                      RADEON_BUF_SWAP_32BIT |
 628                      (dev_priv->ring.fetch_size_l2ow << 18) |
 629                      (dev_priv->ring.rptr_update_l2qw << 8) |
 630                      dev_priv->ring.size_l2qw);
 631 #else
 632         RADEON_WRITE(RADEON_CP_RB_CNTL,
 633                      (dev_priv->ring.fetch_size_l2ow << 18) |
 634                      (dev_priv->ring.rptr_update_l2qw << 8) |
 635                      dev_priv->ring.size_l2qw);
 636 #endif
 637
 638         /* Initialize the scratch register pointer.  This will cause
 639          * the scratch register values to be written out to memory
 640          * whenever they are updated.
 641          *
 642          * We simply put this behind the ring read pointer, this works
 643          * with PCI GART as well as (whatever kind of) AGP GART
 644          */
 645         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 646                      + RADEON_SCRATCH_REG_OFFSET);
 647
 648         dev_priv->scratch = ((__volatile__ u32 *)
 649                              dev_priv->ring_rptr->handle +
 650                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
 651
 652         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 653
 654         /* Turn on bus mastering */
 655         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 656             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 657                 /* rs600/rs690/rs740 */
 658                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 659                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 660         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 661                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 662                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 663                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 664                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 665                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 666                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 667         } /* PCIE cards appears to not need this */
 668
 669         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
 670         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
 671
 672         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
 673         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
 674                      dev_priv->sarea_priv->last_dispatch);
 675
 676         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
 677         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
 678
 679         radeon_do_wait_for_idle(dev_priv);
 680
 681         /* Sync everything up */
 682         RADEON_WRITE(RADEON_ISYNC_CNTL,
 683                      (RADEON_ISYNC_ANY2D_IDLE3D |
 684                       RADEON_ISYNC_ANY3D_IDLE2D |
 685                       RADEON_ISYNC_WAIT_IDLEGUI |
 686                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 687
 688 }
 689
 690 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 691 {
 692         u32 tmp;
 693
 694         /* Writeback doesn't seem to work everywhere, test it here and possibly
 695          * enable it if it appears to work
 696          */
 697         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
 698         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 699
 700         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 701                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
 702                     0xdeadbeef)
 703                         break;
 704                 DRM_UDELAY(1);
 705         }
 706
 707         if (tmp < dev_priv->usec_timeout) {
 708                 dev_priv->writeback_works = 1;
 709                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 710         } else {
 711                 dev_priv->writeback_works = 0;
 712                 DRM_INFO("writeback test failed\n");
 713         }
 714         if (radeon_no_wb == 1) {
 715                 dev_priv->writeback_works = 0;
 716                 DRM_INFO("writeback forced off\n");
 717         }
 718
 719         if (!dev_priv->writeback_works) {
 720                 /* Disable writeback to avoid unnecessary bus master transfers */
 721                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | RADEON_RB_NO_UPDATE);
 722                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 723         }
 724 }
 725
 726 /* Enable or disable IGP GART on the chip */
 727 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 728 {
 729         u32 temp;
 730
 731         if (on) {
 732                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 733                          dev_priv->gart_vm_start,
 734                          (long)dev_priv->gart_info.bus_addr,
 735                          dev_priv->gart_size);
 736
 737                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 738
 739                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 740                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 741                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 742                                                              RS690_BLOCK_GFX_D3_EN));
 743                 else
 744                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 745
 746                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 747                                                                RS480_VA_SIZE_32MB));
 748
 749                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 750                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 751                                                         RS480_TLB_ENABLE |
 752                                                         RS480_GTW_LAC_EN |
 753                                                         RS480_1LEVEL_GART));
 754
 755                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 756                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 757                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 758
 759                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 760                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 761                                                       RS480_REQ_TYPE_SNOOP_DIS));
 762
 763                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 764
 765                 dev_priv->gart_size = 32*1024*1024;
 766                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 767                         0xffff0000) | (dev_priv->gart_vm_start >> 16));
 768
 769                 radeon_write_agp_location(dev_priv, temp);
 770
 771                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 772                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 773                                                                RS480_VA_SIZE_32MB));
 774
 775                 do {
 776                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 777                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 778                                 break;
 779                         DRM_UDELAY(1);
 780                 } while(1);
 781
 782                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 783                                 RS480_GART_CACHE_INVALIDATE);
 784
 785                 do {
 786                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 787                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 788                                 break;
 789                         DRM_UDELAY(1);
 790                 } while(1);
 791
 792                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 793         } else {
 794                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 795         }
 796 }
 797
 798 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 799 {
 800         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 801         if (on) {
 802
 803                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 804                           dev_priv->gart_vm_start,
 805                           (long)dev_priv->gart_info.bus_addr,
 806                           dev_priv->gart_size);
 807                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 808                                   dev_priv->gart_vm_start);
 809                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 810                                   dev_priv->gart_info.bus_addr);
 811                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
 812                                   dev_priv->gart_vm_start);
 813                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
 814                                   dev_priv->gart_vm_start +
 815                                   dev_priv->gart_size - 1);
 816
 817                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
 818
 819                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 820                                   RADEON_PCIE_TX_GART_EN);
 821         } else {
 822                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
 823                                   tmp & ~RADEON_PCIE_TX_GART_EN);
 824         }
 825 }
 826
 827 /* Enable or disable PCI GART on the chip */
 828 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
 829 {
 830         u32 tmp;
 831
 832         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 833             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
 834             (dev_priv->flags & RADEON_IS_IGPGART)) {
 835                 radeon_set_igpgart(dev_priv, on);
 836                 return;
 837         }
 838
 839         if (dev_priv->flags & RADEON_IS_PCIE) {
 840                 radeon_set_pciegart(dev_priv, on);
 841                 return;
 842         }
 843
 844         tmp = RADEON_READ(RADEON_AIC_CNTL);
 845
 846         if (on) {
 847                 RADEON_WRITE(RADEON_AIC_CNTL,
 848                              tmp | RADEON_PCIGART_TRANSLATE_EN);
 849
 850                 /* set PCI GART page-table base address
 851                  */
 852                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
 853
 854                 /* set address range for PCI address translate
 855                  */
 856                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
 857                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
 858                              + dev_priv->gart_size - 1);
 859
 860                 /* Turn off AGP aperture -- is this required for PCI GART?
 861                  */
 862                 radeon_write_agp_location(dev_priv, 0xffffffc0);
 863                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
 864         } else {
 865                 RADEON_WRITE(RADEON_AIC_CNTL,
 866                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 867         }
 868 }
 869
 870 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
 871 {
 872         drm_radeon_private_t *dev_priv = dev->dev_private;
 873
 874         DRM_DEBUG("\n");
 875
 876         /* if we require new memory map but we don't have it fail */
 877         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
 878                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
 879                 radeon_do_cleanup_cp(dev);
 880                 return -EINVAL;
 881         }
 882
 883         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP))
 884         {
 885                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
 886                 dev_priv->flags &= ~RADEON_IS_AGP;
 887         }
 888         else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
 889                  && !init->is_pci)
 890         {
 891                 DRM_DEBUG("Restoring AGP flag\n");
 892                 dev_priv->flags |= RADEON_IS_AGP;
 893         }
 894
 895         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
 896                 DRM_ERROR("PCI GART memory not allocated!\n");
 897                 radeon_do_cleanup_cp(dev);
 898                 return -EINVAL;
 899         }
 900
 901         dev_priv->usec_timeout = init->usec_timeout;
 902         if (dev_priv->usec_timeout < 1 ||
 903             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
 904                 DRM_DEBUG("TIMEOUT problem!\n");
 905                 radeon_do_cleanup_cp(dev);
 906                 return -EINVAL;
 907         }
 908
 909         /* Enable vblank on CRTC1 for older X servers
 910          */
 911         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
 912
 913         dev_priv->do_boxes = 0;
 914         dev_priv->cp_mode = init->cp_mode;
 915
 916         /* We don't support anything other than bus-mastering ring mode,
 917          * but the ring can be in either AGP or PCI space for the ring
 918          * read pointer.
 919          */
 920         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
 921             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
 922                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
 923                 radeon_do_cleanup_cp(dev);
 924                 return -EINVAL;
 925         }
 926
 927         switch (init->fb_bpp) {
 928         case 16:
 929                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
 930                 break;
 931         case 32:
 932         default:
 933                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
 934                 break;
 935         }
 936         dev_priv->front_offset = init->front_offset;
 937         dev_priv->front_pitch = init->front_pitch;
 938         dev_priv->back_offset = init->back_offset;
 939         dev_priv->back_pitch = init->back_pitch;
 940
 941         switch (init->depth_bpp) {
 942         case 16:
 943                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
 944                 break;
 945         case 32:
 946         default:
 947                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
 948                 break;
 949         }
 950         dev_priv->depth_offset = init->depth_offset;
 951         dev_priv->depth_pitch = init->depth_pitch;
 952
 953         /* Hardware state for depth clears.  Remove this if/when we no
 954          * longer clear the depth buffer with a 3D rectangle.  Hard-code
 955          * all values to prevent unwanted 3D state from slipping through
 956          * and screwing with the clear operation.
 957          */
 958         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
 959                                            (dev_priv->color_fmt << 10) |
 960                                            (dev_priv->chip_family < CHIP_R200 ? RADEON_ZBLOCK16 : 0));
 961
 962         dev_priv->depth_clear.rb3d_zstencilcntl =
 963             (dev_priv->depth_fmt |
 964              RADEON_Z_TEST_ALWAYS |
 965              RADEON_STENCIL_TEST_ALWAYS |
 966              RADEON_STENCIL_S_FAIL_REPLACE |
 967              RADEON_STENCIL_ZPASS_REPLACE |
 968              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
 969
 970         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
 971                                          RADEON_BFACE_SOLID |
 972                                          RADEON_FFACE_SOLID |
 973                                          RADEON_FLAT_SHADE_VTX_LAST |
 974                                          RADEON_DIFFUSE_SHADE_FLAT |
 975                                          RADEON_ALPHA_SHADE_FLAT |
 976                                          RADEON_SPECULAR_SHADE_FLAT |
 977                                          RADEON_FOG_SHADE_FLAT |
 978                                          RADEON_VTX_PIX_CENTER_OGL |
 979                                          RADEON_ROUND_MODE_TRUNC |
 980                                          RADEON_ROUND_PREC_8TH_PIX);
 981
 982
 983         dev_priv->ring_offset = init->ring_offset;
 984         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
 985         dev_priv->buffers_offset = init->buffers_offset;
 986         dev_priv->gart_textures_offset = init->gart_textures_offset;
 987
 988         dev_priv->sarea = drm_getsarea(dev);
 989         if (!dev_priv->sarea) {
 990                 DRM_ERROR("could not find sarea!\n");
 991                 radeon_do_cleanup_cp(dev);
 992                 return -EINVAL;
 993         }
 994
 995         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
 996         if (!dev_priv->cp_ring) {
 997                 DRM_ERROR("could not find cp ring region!\n");
 998                 radeon_do_cleanup_cp(dev);
 999                 return -EINVAL;
1000         }
1001         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1002         if (!dev_priv->ring_rptr) {
1003                 DRM_ERROR("could not find ring read pointer!\n");
1004                 radeon_do_cleanup_cp(dev);
1005                 return -EINVAL;
1006         }
1007         dev->agp_buffer_token = init->buffers_offset;
1008         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1009         if (!dev->agp_buffer_map) {
1010                 DRM_ERROR("could not find dma buffer region!\n");
1011                 radeon_do_cleanup_cp(dev);
1012                 return -EINVAL;
1013         }
1014
1015         if (init->gart_textures_offset) {
1016                 dev_priv->gart_textures =
1017                     drm_core_findmap(dev, init->gart_textures_offset);
1018                 if (!dev_priv->gart_textures) {
1019                         DRM_ERROR("could not find GART texture region!\n");
1020                         radeon_do_cleanup_cp(dev);
1021                         return -EINVAL;
1022                 }
1023         }
1024
1025         dev_priv->sarea_priv =
1026             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1027                                     init->sarea_priv_offset);
1028
1029 #if __OS_HAS_AGP
1030         if (dev_priv->flags & RADEON_IS_AGP) {
1031                 drm_core_ioremap(dev_priv->cp_ring, dev);
1032                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1033                 drm_core_ioremap(dev->agp_buffer_map, dev);
1034                 if (!dev_priv->cp_ring->handle ||
1035                     !dev_priv->ring_rptr->handle ||
1036                     !dev->agp_buffer_map->handle) {
1037                         DRM_ERROR("could not find ioremap agp regions!\n");
1038                         radeon_do_cleanup_cp(dev);
1039                         return -EINVAL;
1040                 }
1041         } else
1042 #endif
1043         {
1044                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1045                 dev_priv->ring_rptr->handle =
1046                     (void *)dev_priv->ring_rptr->offset;
1047                 dev->agp_buffer_map->handle =
1048                     (void *)dev->agp_buffer_map->offset;
1049
1050                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1051                           dev_priv->cp_ring->handle);
1052                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1053                           dev_priv->ring_rptr->handle);
1054                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1055                           dev->agp_buffer_map->handle);
1056         }
1057
1058         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1059         dev_priv->fb_size =
1060                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1061                 - dev_priv->fb_location;
1062
1063         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1064                                         ((dev_priv->front_offset
1065                                           + dev_priv->fb_location) >> 10));
1066
1067         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1068                                        ((dev_priv->back_offset
1069                                          + dev_priv->fb_location) >> 10));
1070
1071         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1072                                         ((dev_priv->depth_offset
1073                                           + dev_priv->fb_location) >> 10));
1074
1075         dev_priv->gart_size = init->gart_size;
1076
1077         /* New let's set the memory map ... */
1078         if (dev_priv->new_memmap) {
1079                 u32 base = 0;
1080
1081                 DRM_INFO("Setting GART location based on new memory map\n");
1082
1083                 /* If using AGP, try to locate the AGP aperture at the same
1084                  * location in the card and on the bus, though we have to
1085                  * align it down.
1086                  */
1087 #if __OS_HAS_AGP
1088                 if (dev_priv->flags & RADEON_IS_AGP) {
1089                         base = dev->agp->base;
1090                         /* Check if valid */
1091                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1092                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1093                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1094                                          dev->agp->base);
1095                                 base = 0;
1096                         }
1097                 }
1098 #endif
1099                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1100                 if (base == 0) {
1101                         base = dev_priv->fb_location + dev_priv->fb_size;
1102                         if (base < dev_priv->fb_location ||
1103                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1104                                 base = dev_priv->fb_location
1105                                         - dev_priv->gart_size;
1106                 }
1107                 dev_priv->gart_vm_start = base & 0xffc00000u;
1108                 if (dev_priv->gart_vm_start != base)
1109                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1110                                  base, dev_priv->gart_vm_start);
1111         } else {
1112                 DRM_INFO("Setting GART location based on old memory map\n");
1113                 dev_priv->gart_vm_start = dev_priv->fb_location +
1114                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1115         }
1116
1117 #if __OS_HAS_AGP
1118         if (dev_priv->flags & RADEON_IS_AGP)
1119                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1120                                                  - dev->agp->base
1121                                                  + dev_priv->gart_vm_start);
1122         else
1123 #endif
1124                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1125                                         - (unsigned long)dev->sg->virtual
1126                                         + dev_priv->gart_vm_start);
1127
1128         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1129         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1130         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1131                   dev_priv->gart_buffers_offset);
1132
1133         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1134         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1135                               + init->ring_size / sizeof(u32));
1136         dev_priv->ring.size = init->ring_size;
1137         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1138
1139         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1140         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1141
1142         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1143         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1144
1145         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1146
1147         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1148
1149 #if __OS_HAS_AGP
1150         if (dev_priv->flags & RADEON_IS_AGP) {
1151                 /* Turn off PCI GART */
1152                 radeon_set_pcigart(dev_priv, 0);
1153         } else
1154 #endif
1155         {
1156                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1157                 /* if we have an offset set from userspace */
1158                 if (dev_priv->pcigart_offset_set) {
1159                         dev_priv->gart_info.bus_addr =
1160                             dev_priv->pcigart_offset + dev_priv->fb_location;
1161                         dev_priv->gart_info.mapping.offset =
1162                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1163                         dev_priv->gart_info.mapping.size =
1164                             dev_priv->gart_info.table_size;
1165
1166                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1167                         dev_priv->gart_info.addr =
1168                             dev_priv->gart_info.mapping.handle;
1169
1170                         if (dev_priv->flags & RADEON_IS_PCIE)
1171                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1172                         else
1173                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1174                         dev_priv->gart_info.gart_table_location =
1175                             DRM_ATI_GART_FB;
1176
1177                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1178                                   dev_priv->gart_info.addr,
1179                                   dev_priv->pcigart_offset);
1180                 } else {
1181                         if (dev_priv->flags & RADEON_IS_IGPGART)
1182                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1183                         else
1184                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1185                         dev_priv->gart_info.gart_table_location =
1186                             DRM_ATI_GART_MAIN;
1187                         dev_priv->gart_info.addr = NULL;
1188                         dev_priv->gart_info.bus_addr = 0;
1189                         if (dev_priv->flags & RADEON_IS_PCIE) {
1190                                 DRM_ERROR
1191                                     ("Cannot use PCI Express without GART in FB memory\n");
1192                                 radeon_do_cleanup_cp(dev);
1193                                 return -EINVAL;
1194                         }
1195                 }
1196
1197                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1198                         DRM_ERROR("failed to init PCI GART!\n");
1199                         radeon_do_cleanup_cp(dev);
1200                         return -ENOMEM;
1201                 }
1202
1203                 /* Turn on PCI GART */
1204                 radeon_set_pcigart(dev_priv, 1);
1205         }
1206
1207         /* Start with assuming that writeback doesn't work */
1208         dev_priv->writeback_works = 0;
1209
1210         radeon_cp_load_microcode(dev_priv);
1211         radeon_cp_init_ring_buffer(dev, dev_priv);
1212
1213         dev_priv->last_buf = 0;
1214
1215         radeon_do_engine_reset(dev);
1216         radeon_test_writeback(dev_priv);
1217
1218         return 0;
1219 }
1220
1221 static int radeon_do_cleanup_cp(struct drm_device * dev)
1222 {
1223         drm_radeon_private_t *dev_priv = dev->dev_private;
1224         DRM_DEBUG("\n");
1225
1226         /* Make sure interrupts are disabled here because the uninstall ioctl
1227          * may not have been called from userspace and after dev_private
1228          * is freed, it's too late.
1229          */
1230         if (dev->irq_enabled)
1231                 drm_irq_uninstall(dev);
1232
1233 #if __OS_HAS_AGP
1234         if (dev_priv->flags & RADEON_IS_AGP) {
1235                 if (dev_priv->cp_ring != NULL) {
1236                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1237                         dev_priv->cp_ring = NULL;
1238                 }
1239                 if (dev_priv->ring_rptr != NULL) {
1240                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1241                         dev_priv->ring_rptr = NULL;
1242                 }
1243                 if (dev->agp_buffer_map != NULL) {
1244                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1245                         dev->agp_buffer_map = NULL;
1246                 }
1247         } else
1248 #endif
1249         {
1250
1251                 if (dev_priv->gart_info.bus_addr) {
1252                         /* Turn off PCI GART */
1253                         radeon_set_pcigart(dev_priv, 0);
1254                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1255                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1256                 }
1257
1258                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1259                 {
1260                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1261                         dev_priv->gart_info.addr = 0;
1262                 }
1263         }
1264         /* only clear to the start of flags */
1265         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1266
1267         return 0;
1268 }
1269
1270 /* This code will reinit the Radeon CP hardware after a resume from disc.
1271  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1272  * here we make sure that all Radeon hardware initialisation is re-done without
1273  * affecting running applications.
1274  *
1275  * Charl P. Botha <http://cpbotha.net>
1276  */
1277 static int radeon_do_resume_cp(struct drm_device * dev)
1278 {
1279         drm_radeon_private_t *dev_priv = dev->dev_private;
1280
1281         if (!dev_priv) {
1282                 DRM_ERROR("Called with no initialization\n");
1283                 return -EINVAL;
1284         }
1285
1286         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1287
1288 #if __OS_HAS_AGP
1289         if (dev_priv->flags & RADEON_IS_AGP) {
1290                 /* Turn off PCI GART */
1291                 radeon_set_pcigart(dev_priv, 0);
1292         } else
1293 #endif
1294         {
1295                 /* Turn on PCI GART */
1296                 radeon_set_pcigart(dev_priv, 1);
1297         }
1298
1299         radeon_cp_load_microcode(dev_priv);
1300         radeon_cp_init_ring_buffer(dev, dev_priv);
1301
1302         radeon_do_engine_reset(dev);
1303         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1304
1305         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1306
1307         return 0;
1308 }
1309
1310 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1311 {
1312         drm_radeon_init_t *init = data;
1313
1314         LOCK_TEST_WITH_RETURN(dev, file_priv);
1315
1316         if (init->func == RADEON_INIT_R300_CP)
1317                 r300_init_reg_flags(dev);
1318
1319         switch (init->func) {
1320         case RADEON_INIT_CP:
1321         case RADEON_INIT_R200_CP:
1322         case RADEON_INIT_R300_CP:
1323                 return radeon_do_init_cp(dev, init);
1324         case RADEON_CLEANUP_CP:
1325                 return radeon_do_cleanup_cp(dev);
1326         }
1327
1328         return -EINVAL;
1329 }
1330
1331 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1332 {
1333         drm_radeon_private_t *dev_priv = dev->dev_private;
1334         DRM_DEBUG("\n");
1335
1336         LOCK_TEST_WITH_RETURN(dev, file_priv);
1337
1338         if (dev_priv->cp_running) {
1339                 DRM_DEBUG("while CP running\n");
1340                 return 0;
1341         }
1342         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1343                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1344                           dev_priv->cp_mode);
1345                 return 0;
1346         }
1347
1348         radeon_do_cp_start(dev_priv);
1349
1350         return 0;
1351 }
1352
1353 /* Stop the CP.  The engine must have been idled before calling this
1354  * routine.
1355  */
1356 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1357 {
1358         drm_radeon_private_t *dev_priv = dev->dev_private;
1359         drm_radeon_cp_stop_t *stop = data;
1360         int ret;
1361         DRM_DEBUG("\n");
1362
1363         LOCK_TEST_WITH_RETURN(dev, file_priv);
1364
1365         if (!dev_priv->cp_running)
1366                 return 0;
1367
1368         /* Flush any pending CP commands.  This ensures any outstanding
1369          * commands are exectuted by the engine before we turn it off.
1370          */
1371         if (stop->flush) {
1372                 radeon_do_cp_flush(dev_priv);
1373         }
1374
1375         /* If we fail to make the engine go idle, we return an error
1376          * code so that the DRM ioctl wrapper can try again.
1377          */
1378         if (stop->idle) {
1379                 ret = radeon_do_cp_idle(dev_priv);
1380                 if (ret)
1381                         return ret;
1382         }
1383
1384         /* Finally, we can turn off the CP.  If the engine isn't idle,
1385          * we will get some dropped triangles as they won't be fully
1386          * rendered before the CP is shut down.
1387          */
1388         radeon_do_cp_stop(dev_priv);
1389
1390         /* Reset the engine */
1391         radeon_do_engine_reset(dev);
1392
1393         return 0;
1394 }
1395
1396 void radeon_do_release(struct drm_device * dev)
1397 {
1398         drm_radeon_private_t *dev_priv = dev->dev_private;
1399         int i, ret;
1400
1401         if (dev_priv) {
1402                 if (dev_priv->cp_running) {
1403                         /* Stop the cp */
1404                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1405                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1406 #ifdef __linux__
1407                                 schedule();
1408 #else
1409 #if defined(__FreeBSD__) && __FreeBSD_version > 500000
1410                                 mtx_sleep(&ret, &dev->dev_lock, PZERO, "rdnrel",
1411                                        1);
1412 #else
1413                                 tsleep(&ret, PZERO, "rdnrel", 1);
1414 #endif
1415 #endif
1416                         }
1417                         radeon_do_cp_stop(dev_priv);
1418                         radeon_do_engine_reset(dev);
1419                 }
1420
1421                 /* Disable *all* interrupts */
1422                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1423                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1424
1425                 if (dev_priv->mmio) {   /* remove all surfaces */
1426                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1427                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1428                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1429                                              16 * i, 0);
1430                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1431                                              16 * i, 0);
1432                         }
1433                 }
1434
1435                 /* Free memory heap structures */
1436                 radeon_mem_takedown(&(dev_priv->gart_heap));
1437                 radeon_mem_takedown(&(dev_priv->fb_heap));
1438
1439                 /* deallocate kernel resources */
1440                 radeon_do_cleanup_cp(dev);
1441         }
1442 }
1443
1444 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1445  */
1446 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1447 {
1448         drm_radeon_private_t *dev_priv = dev->dev_private;
1449         DRM_DEBUG("\n");
1450
1451         LOCK_TEST_WITH_RETURN(dev, file_priv);
1452
1453         if (!dev_priv) {
1454                 DRM_DEBUG("called before init done\n");
1455                 return -EINVAL;
1456         }
1457
1458         radeon_do_cp_reset(dev_priv);
1459
1460         /* The CP is no longer running after an engine reset */
1461         dev_priv->cp_running = 0;
1462
1463         return 0;
1464 }
1465
1466 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1467 {
1468         drm_radeon_private_t *dev_priv = dev->dev_private;
1469         DRM_DEBUG("\n");
1470
1471         LOCK_TEST_WITH_RETURN(dev, file_priv);
1472
1473         return radeon_do_cp_idle(dev_priv);
1474 }
1475
1476 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1477  */
1478 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1479 {
1480
1481         return radeon_do_resume_cp(dev);
1482 }
1483
1484 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1485 {
1486         DRM_DEBUG("\n");
1487
1488         LOCK_TEST_WITH_RETURN(dev, file_priv);
1489
1490         return radeon_do_engine_reset(dev);
1491 }
1492
1493 /* ================================================================
1494  * Fullscreen mode
1495  */
1496
1497 /* KW: Deprecated to say the least:
1498  */
1499 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1500 {
1501         return 0;
1502 }
1503
1504 /* ================================================================
1505  * Freelist management
1506  */
1507
1508 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1509  *   bufs until freelist code is used.  Note this hides a problem with
1510  *   the scratch register * (used to keep track of last buffer
1511  *   completed) being written to before * the last buffer has actually
1512  *   completed rendering.
1513  *
1514  * KW:  It's also a good way to find free buffers quickly.
1515  *
1516  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1517  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1518  * we essentially have to do this, else old clients will break.
1519  *
1520  * However, it does leave open a potential deadlock where all the
1521  * buffers are held by other clients, which can't release them because
1522  * they can't get the lock.
1523  */
1524
1525 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1526 {
1527         struct drm_device_dma *dma = dev->dma;
1528         drm_radeon_private_t *dev_priv = dev->dev_private;
1529         drm_radeon_buf_priv_t *buf_priv;
1530         struct drm_buf *buf;
1531         int i, t;
1532         int start;
1533
1534         if (++dev_priv->last_buf >= dma->buf_count)
1535                 dev_priv->last_buf = 0;
1536
1537         start = dev_priv->last_buf;
1538
1539         for (t = 0; t < dev_priv->usec_timeout; t++) {
1540                 u32 done_age = GET_SCRATCH(1);
1541                 DRM_DEBUG("done_age = %d\n", done_age);
1542                 for (i = start; i < dma->buf_count; i++) {
1543                         buf = dma->buflist[i];
1544                         buf_priv = buf->dev_private;
1545                         if (buf->file_priv == NULL || (buf->pending &&
1546                                                        buf_priv->age <=
1547                                                        done_age)) {
1548                                 dev_priv->stats.requested_bufs++;
1549                                 buf->pending = 0;
1550                                 return buf;
1551                         }
1552                         start = 0;
1553                 }
1554
1555                 if (t) {
1556                         DRM_UDELAY(1);
1557                         dev_priv->stats.freelist_loops++;
1558                 }
1559         }
1560
1561         DRM_DEBUG("returning NULL!\n");
1562         return NULL;
1563 }
1564
1565 #if 0
1566 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1567 {
1568         struct drm_device_dma *dma = dev->dma;
1569         drm_radeon_private_t *dev_priv = dev->dev_private;
1570         drm_radeon_buf_priv_t *buf_priv;
1571         struct drm_buf *buf;
1572         int i, t;
1573         int start;
1574         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1575
1576         if (++dev_priv->last_buf >= dma->buf_count)
1577                 dev_priv->last_buf = 0;
1578
1579         start = dev_priv->last_buf;
1580         dev_priv->stats.freelist_loops++;
1581
1582         for (t = 0; t < 2; t++) {
1583                 for (i = start; i < dma->buf_count; i++) {
1584                         buf = dma->buflist[i];
1585                         buf_priv = buf->dev_private;
1586                         if (buf->file_priv == 0 || (buf->pending &&
1587                                                     buf_priv->age <=
1588                                                     done_age)) {
1589                                 dev_priv->stats.requested_bufs++;
1590                                 buf->pending = 0;
1591                                 return buf;
1592                         }
1593                 }
1594                 start = 0;
1595         }
1596
1597         return NULL;
1598 }
1599 #endif
1600
1601 void radeon_freelist_reset(struct drm_device * dev)
1602 {
1603         struct drm_device_dma *dma = dev->dma;
1604         drm_radeon_private_t *dev_priv = dev->dev_private;
1605         int i;
1606
1607         dev_priv->last_buf = 0;
1608         for (i = 0; i < dma->buf_count; i++) {
1609                 struct drm_buf *buf = dma->buflist[i];
1610                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1611                 buf_priv->age = 0;
1612         }
1613 }
1614
1615 /* ================================================================
1616  * CP command submission
1617  */
1618
1619 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1620 {
1621         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1622         int i;
1623         u32 last_head = GET_RING_HEAD(dev_priv);
1624
1625         for (i = 0; i < dev_priv->usec_timeout; i++) {
1626                 u32 head = GET_RING_HEAD(dev_priv);
1627
1628                 ring->space = (head - ring->tail) * sizeof(u32);
1629                 if (ring->space <= 0)
1630                         ring->space += ring->size;
1631                 if (ring->space > n)
1632                         return 0;
1633
1634                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1635
1636                 if (head != last_head)
1637                         i = 0;
1638                 last_head = head;
1639
1640                 DRM_UDELAY(1);
1641         }
1642
1643         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1644 #if RADEON_FIFO_DEBUG
1645         radeon_status(dev_priv);
1646         DRM_ERROR("failed!\n");
1647 #endif
1648         return -EBUSY;
1649 }
1650
1651 static int radeon_cp_get_buffers(struct drm_device *dev,
1652                                  struct drm_file *file_priv,
1653                                  struct drm_dma * d)
1654 {
1655         int i;
1656         struct drm_buf *buf;
1657
1658         for (i = d->granted_count; i < d->request_count; i++) {
1659                 buf = radeon_freelist_get(dev);
1660                 if (!buf)
1661                         return -EBUSY;  /* NOTE: broken client */
1662
1663                 buf->file_priv = file_priv;
1664
1665                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1666                                      sizeof(buf->idx)))
1667                         return -EFAULT;
1668                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1669                                      sizeof(buf->total)))
1670                         return -EFAULT;
1671
1672                 d->granted_count++;
1673         }
1674         return 0;
1675 }
1676
1677 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1678 {
1679         struct drm_device_dma *dma = dev->dma;
1680         int ret = 0;
1681         struct drm_dma *d = data;
1682
1683         LOCK_TEST_WITH_RETURN(dev, file_priv);
1684
1685         /* Please don't send us buffers.
1686          */
1687         if (d->send_count != 0) {
1688                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1689                           DRM_CURRENTPID, d->send_count);
1690                 return -EINVAL;
1691         }
1692
1693         /* We'll send you buffers.
1694          */
1695         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1696                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1697                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1698                 return -EINVAL;
1699         }
1700
1701         d->granted_count = 0;
1702
1703         if (d->request_count) {
1704                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1705         }
1706
1707         return ret;
1708 }
1709
1710 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1711 {
1712         drm_radeon_private_t *dev_priv;
1713         int ret = 0;
1714
1715         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1716         if (dev_priv == NULL)
1717                 return -ENOMEM;
1718
1719         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1720         dev->dev_private = (void *)dev_priv;
1721         dev_priv->flags = flags;
1722
1723         switch (flags & RADEON_FAMILY_MASK) {
1724         case CHIP_R100:
1725         case CHIP_RV200:
1726         case CHIP_R200:
1727         case CHIP_R300:
1728         case CHIP_R350:
1729         case CHIP_R420:
1730         case CHIP_R423:
1731         case CHIP_RV410:
1732         case CHIP_RV515:
1733         case CHIP_R520:
1734         case CHIP_RV570:
1735         case CHIP_R580:
1736                 dev_priv->flags |= RADEON_HAS_HIERZ;
1737                 break;
1738         default:
1739                 /* all other chips have no hierarchical z buffer */
1740                 break;
1741         }
1742
1743         dev_priv->chip_family = flags & RADEON_FAMILY_MASK;
1744         if (drm_device_is_agp(dev))
1745                 dev_priv->flags |= RADEON_IS_AGP;
1746         else if (drm_device_is_pcie(dev))
1747                 dev_priv->flags |= RADEON_IS_PCIE;
1748         else
1749                 dev_priv->flags |= RADEON_IS_PCI;
1750
1751         DRM_DEBUG("%s card detected\n",
1752                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1753         return ret;
1754 }
1755
1756 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1757  * have to find them.
1758  */
1759 int radeon_driver_firstopen(struct drm_device *dev)
1760 {
1761         int ret;
1762         drm_local_map_t *map;
1763         drm_radeon_private_t *dev_priv = dev->dev_private;
1764
1765         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1766
1767         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1768                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1769                          _DRM_READ_ONLY, &dev_priv->mmio);
1770         if (ret != 0)
1771                 return ret;
1772
1773         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1774         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1775                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1776                          _DRM_WRITE_COMBINING, &map);
1777         if (ret != 0)
1778                 return ret;
1779
1780         return 0;
1781 }
1782
1783 int radeon_driver_unload(struct drm_device *dev)
1784 {
1785         drm_radeon_private_t *dev_priv = dev->dev_private;
1786
1787         DRM_DEBUG("\n");
1788         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1789
1790         dev->dev_private = NULL;
1791         return 0;
1792 }